Patent
US 10,600,816ARRAY SUBSTRATE COMPRISING GRAPHENE CONDUCTIVE LAYER AND MANUFACTURING METHOD OF THE SAME
Huafei XIE
US
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Patent
Atlas literature
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US 10,600,816Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 SVG 16002220.06-07-2018.JI₄SUOYNRXEAPX3.SPEC.2.svg 1.25 4.7 Black and white
FIG. 2 SVG 16002220.06-07-2018.JI₄SUOYNRXEAPX3.SPEC.3.svg 1.54 5.03 Black and white
FIG. 3 SVG 16002220.06-07-2018.JI₄SUOYNRXEAPX3.SPEC.4.svg 1.38 5.39 Black and white
FIG. 4 SVG 16002220.06-07-2018.JI₄SUOYNRXEAPX3.SPEC.5.svg 2.27 5.64 Black and white
FIG. 5 SVG 16002220.06-07-2018.JI₄SUOYNRXEAPX3.SPEC.6.svg 9.96 7.51 Black and white SVG 16002220.06-07-2018.JI₄SUOYNRXEAPX3.SPEC.7.svg 2.59 7.51 Black and …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An array substrate, comprising a substrate, an active layer disposed on the substrate, a conductive layer, a source and a drain, wherein the conductive layer is disposed on two opposite sides of the active layer and is in contact with the active layer, the conductive layer forms a gap on the active layer to expose a partial surface of the active layer, the source and the drain are respectively disposed on the conductive layer on two opposite sides of the active layer.
The array substrate according to claim 1, wherein a material of the conductive layer is graphene.
A display panel, comprising the array substrate according to claim 1, a color filter substrate, and a liquid crystal molecule layer sealed between the array substrate and the color filter substrate.
A manufacturing method of an array substrate, comprising: providing a substrate and disposing an active layer thereon; forming a conductive layer in contact with the active layer on two opposite sides of the active layer, wherein the conductive layer forms a gap on the active layer to expose a partial surface of the active layer; and forming a source and a drain respectively on the conductive layer on the two opposite sides of the active layer.
The manufacturing method of an array substrate according to claim 11, wherein the step of forming a conductive layer in contact with the active layer on two opposite sides of the active layer comprises depositing a bottom gate on the substrate, and depositing a gate insulating layer covering the bottom gate.
The manufacturing method of an array substrate according to claim 11, wherein the step of forming a source and a drain respectively on the conductive layer on the two opposite sides of the active layer further comprises depositing an insulating protective layer between the source, the drain and the gap on the active layer, depositing a top gate on the insulating protective layer and depositing a passivation protective layer covering the top gate on the top gate.
The manufacturing method of an array substrate according to claim 11, wherein a photoresist is used to protect the gap on the active layer, the substrate is immersed into the conductive layer solution to deposit the conductive layer, after the deposition was completed, the substrate was baked at 150 0C for 30 minutes to remove excess conductive layer solution for drying the substrate. What is claimed is:
6 14 16. Canceled
Layer stacks claimed or described, ordered top of device to substrate.
array substrate (generic)
array substrate (bottom-gate configuration)
Materials described outside the worked examples.
active layer material
carbon nanotube
graphene
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,600,816Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 SVG 16002220.06-07-2018.JI₄SUOYNRXEAPX3.SPEC.2.svg 1.25 4.7 Black and white
FIG. 2 SVG 16002220.06-07-2018.JI₄SUOYNRXEAPX3.SPEC.3.svg 1.54 5.03 Black and white
FIG. 3 SVG 16002220.06-07-2018.JI₄SUOYNRXEAPX3.SPEC.4.svg 1.38 5.39 Black and white
FIG. 4 SVG 16002220.06-07-2018.JI₄SUOYNRXEAPX3.SPEC.5.svg 2.27 5.64 Black and white
FIG. 5 SVG 16002220.06-07-2018.JI₄SUOYNRXEAPX3.SPEC.6.svg 9.96 7.51 Black and white SVG 16002220.06-07-2018.JI₄SUOYNRXEAPX3.SPEC.7.svg 2.59 7.51 Black and …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An array substrate, comprising a substrate, an active layer disposed on the substrate, a conductive layer, a source and a drain, wherein the conductive layer is disposed on two opposite sides of the active layer and is in contact with the active layer, the conductive layer forms a gap on the active layer to expose a partial surface of the active layer, the source and the drain are respectively disposed on the conductive layer on two opposite sides of the active layer.
The array substrate according to claim 1, wherein a material of the conductive layer is graphene.
A display panel, comprising the array substrate according to claim 1, a color filter substrate, and a liquid crystal molecule layer sealed between the array substrate and the color filter substrate.
A manufacturing method of an array substrate, comprising: providing a substrate and disposing an active layer thereon; forming a conductive layer in contact with the active layer on two opposite sides of the active layer, wherein the conductive layer forms a gap on the active layer to expose a partial surface of the active layer; and forming a source and a drain respectively on the conductive layer on the two opposite sides of the active layer.
The manufacturing method of an array substrate according to claim 11, wherein the step of forming a conductive layer in contact with the active layer on two opposite sides of the active layer comprises depositing a bottom gate on the substrate, and depositing a gate insulating layer covering the bottom gate.
The manufacturing method of an array substrate according to claim 11, wherein the step of forming a source and a drain respectively on the conductive layer on the two opposite sides of the active layer further comprises depositing an insulating protective layer between the source, the drain and the gap on the active layer, depositing a top gate on the insulating protective layer and depositing a passivation protective layer covering the top gate on the top gate.
The manufacturing method of an array substrate according to claim 11, wherein a photoresist is used to protect the gap on the active layer, the substrate is immersed into the conductive layer solution to deposit the conductive layer, after the deposition was completed, the substrate was baked at 150 0C for 30 minutes to remove excess conductive layer solution for drying the substrate. What is claimed is:
6 14 16. Canceled
Layer stacks claimed or described, ordered top of device to substrate.
array substrate (generic)
array substrate (bottom-gate configuration)
Materials described outside the worked examples.
active layer material
carbon nanotube
graphene
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,600,816Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 SVG 16002220.06-07-2018.JI₄SUOYNRXEAPX3.SPEC.2.svg 1.25 4.7 Black and white
FIG. 2 SVG 16002220.06-07-2018.JI₄SUOYNRXEAPX3.SPEC.3.svg 1.54 5.03 Black and white
FIG. 3 SVG 16002220.06-07-2018.JI₄SUOYNRXEAPX3.SPEC.4.svg 1.38 5.39 Black and white
FIG. 4 SVG 16002220.06-07-2018.JI₄SUOYNRXEAPX3.SPEC.5.svg 2.27 5.64 Black and white
FIG. 5 SVG 16002220.06-07-2018.JI₄SUOYNRXEAPX3.SPEC.6.svg 9.96 7.51 Black and white SVG 16002220.06-07-2018.JI₄SUOYNRXEAPX3.SPEC.7.svg 2.59 7.51 Black and …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An array substrate, comprising a substrate, an active layer disposed on the substrate, a conductive layer, a source and a drain, wherein the conductive layer is disposed on two opposite sides of the active layer and is in contact with the active layer, the conductive layer forms a gap on the active layer to expose a partial surface of the active layer, the source and the drain are respectively disposed on the conductive layer on two opposite sides of the active layer.
The array substrate according to claim 1, wherein a material of the conductive layer is graphene.
A display panel, comprising the array substrate according to claim 1, a color filter substrate, and a liquid crystal molecule layer sealed between the array substrate and the color filter substrate.
A manufacturing method of an array substrate, comprising: providing a substrate and disposing an active layer thereon; forming a conductive layer in contact with the active layer on two opposite sides of the active layer, wherein the conductive layer forms a gap on the active layer to expose a partial surface of the active layer; and forming a source and a drain respectively on the conductive layer on the two opposite sides of the active layer.
The manufacturing method of an array substrate according to claim 11, wherein the step of forming a conductive layer in contact with the active layer on two opposite sides of the active layer comprises depositing a bottom gate on the substrate, and depositing a gate insulating layer covering the bottom gate.
The manufacturing method of an array substrate according to claim 11, wherein the step of forming a source and a drain respectively on the conductive layer on the two opposite sides of the active layer further comprises depositing an insulating protective layer between the source, the drain and the gap on the active layer, depositing a top gate on the insulating protective layer and depositing a passivation protective layer covering the top gate on the top gate.
The manufacturing method of an array substrate according to claim 11, wherein a photoresist is used to protect the gap on the active layer, the substrate is immersed into the conductive layer solution to deposit the conductive layer, after the deposition was completed, the substrate was baked at 150 0C for 30 minutes to remove excess conductive layer solution for drying the substrate. What is claimed is:
6 14 16. Canceled
Layer stacks claimed or described, ordered top of device to substrate.
array substrate (generic)
array substrate (bottom-gate configuration)
Materials described outside the worked examples.
active layer material
carbon nanotube
graphene
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,600,816Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 SVG 16002220.06-07-2018.JI₄SUOYNRXEAPX3.SPEC.2.svg 1.25 4.7 Black and white
FIG. 2 SVG 16002220.06-07-2018.JI₄SUOYNRXEAPX3.SPEC.3.svg 1.54 5.03 Black and white
FIG. 3 SVG 16002220.06-07-2018.JI₄SUOYNRXEAPX3.SPEC.4.svg 1.38 5.39 Black and white
FIG. 4 SVG 16002220.06-07-2018.JI₄SUOYNRXEAPX3.SPEC.5.svg 2.27 5.64 Black and white
FIG. 5 SVG 16002220.06-07-2018.JI₄SUOYNRXEAPX3.SPEC.6.svg 9.96 7.51 Black and white SVG 16002220.06-07-2018.JI₄SUOYNRXEAPX3.SPEC.7.svg 2.59 7.51 Black and …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An array substrate, comprising a substrate, an active layer disposed on the substrate, a conductive layer, a source and a drain, wherein the conductive layer is disposed on two opposite sides of the active layer and is in contact with the active layer, the conductive layer forms a gap on the active layer to expose a partial surface of the active layer, the source and the drain are respectively disposed on the conductive layer on two opposite sides of the active layer.
The array substrate according to claim 1, wherein a material of the conductive layer is graphene.
A display panel, comprising the array substrate according to claim 1, a color filter substrate, and a liquid crystal molecule layer sealed between the array substrate and the color filter substrate.
A manufacturing method of an array substrate, comprising: providing a substrate and disposing an active layer thereon; forming a conductive layer in contact with the active layer on two opposite sides of the active layer, wherein the conductive layer forms a gap on the active layer to expose a partial surface of the active layer; and forming a source and a drain respectively on the conductive layer on the two opposite sides of the active layer.
The manufacturing method of an array substrate according to claim 11, wherein the step of forming a conductive layer in contact with the active layer on two opposite sides of the active layer comprises depositing a bottom gate on the substrate, and depositing a gate insulating layer covering the bottom gate.
The manufacturing method of an array substrate according to claim 11, wherein the step of forming a source and a drain respectively on the conductive layer on the two opposite sides of the active layer further comprises depositing an insulating protective layer between the source, the drain and the gap on the active layer, depositing a top gate on the insulating protective layer and depositing a passivation protective layer covering the top gate on the top gate.
The manufacturing method of an array substrate according to claim 11, wherein a photoresist is used to protect the gap on the active layer, the substrate is immersed into the conductive layer solution to deposit the conductive layer, after the deposition was completed, the substrate was baked at 150 0C for 30 minutes to remove excess conductive layer solution for drying the substrate. What is claimed is:
6 14 16. Canceled
Layer stacks claimed or described, ordered top of device to substrate.
array substrate (generic)
array substrate (bottom-gate configuration)
Materials described outside the worked examples.
active layer material
carbon nanotube
graphene
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
array substrate (top-gate configuration)
display panel
silicon dioxide
SiO₂
METHOD OF FABRICATING GRAPHENE NANO-MESH
array substrate (top-gate configuration)
display panel
silicon dioxide
SiO₂
METHOD OF FABRICATING GRAPHENE NANO-MESH
array substrate (top-gate configuration)
display panel
silicon dioxide
SiO₂
METHOD OF FABRICATING GRAPHENE NANO-MESH
array substrate (top-gate configuration)
display panel
silicon dioxide
SiO₂
METHOD OF FABRICATING GRAPHENE NANO-MESH