BILAYER GATE DIELECTRIC WITH LOW EQUIVALENT OXIDE THICKNESS FOR GRAPHENE DEVICES

Christos D. Dimitrakopoulos

Patent

Atlas literature

Patent

US 8,680,511

BILAYER GATE DIELECTRIC WITH LOW EQUIVALENT OXIDE THICKNESS FOR GRAPHENE DEVICES

Christos D. Dimitrakopoulos

Drawings

Patent drawings and their descriptions. Click a drawing to enlarge it.

FIG. 1

FIG. 1 1 B and 1 1 C respectively, are cross section AFM images at diﬀerent magniﬁcations illustrating the roughness of the HfO₂ layer that was formed atop the …

FIG. 2

FIG. 2 is a pictorial representation (through a cross sectional view) illustrating the base substrate of

FIG. 3

FIG. 3 is a pictorial representation (through a cross sectional view) illustrating the structure of

FIG. 4

FIG. 4 is a pictorial representation (through a cross sectional view) illustrating the structure of

FIG. 5

FIG. 5 is a pictorial representation (through a cross sectional view) illustrating a graphene- containing semiconductor device that can be formed using the …

FIG. 6

FIG. 6 is a pictorial representation (through a cross sectional view) illustrating another graphene-containing semiconductor device that can be formed using …

FIG. 7

FIG. 7 is a pictorial representation (through a cross sectional view) illustrating a further graphene-containing semiconductor device that can be formed using …

FIG. 8

FIG. 8 is a pictorial representation (through a cross sectional view) illustrating an even further graphene-containing semiconductor device that can be formed …

FIG. 9

FIG. 9A is an actual AFM height image of a structure after forming a SiN layer atop a graphene layer as in accordance with Example 1 of the present disclosure. …

FIG. 10

FIG. 10 is a cross section AFM image illustrating the roughness of the SiN layer depicted in

FIG. 11

FIG. 11 B and 1 I C respectively, are YO R₉₂₀₁₁₀₆₇₃U S 1 Page 17 of 24 representative cross section AFM images at diﬀerent magniﬁcations illustrating the …

FIG. 12

FIGS. 12A and 12B which correspond to

FIG. 13

FIG. 13 is an actual AFM height image of a structure after forming a HfO₂ layer directly atop a graphene layer in accordance with Example 2 of the present …

FIG. 14

FIG. 14 is a cross section AFM image illustrating the roughness of the HfO₂ layer that was formed directly atop the graphene layer as in accordance with …

FIG. 15

FIG. 15 is a side-by-side SEM comparison of the structures provided in Examples 1 and 2 of the present disclosure. The uniform area on the right has a SiN X …

Claims

Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.

6 independent · 22 dependent

1
IndependentCSi₃N₄HfO₂semiconductor structure with bilayer gate dielectric on graphene
A semiconductor structure comprising: a graphene layer located on an uppermost surface of a base substrate; and a bilayer gate dielectric located on an uppermost surface of [[the]] said graphene layer, wherein said bilayer gate dielectric includes, from bottom to top, a tensile silicon nitride layer and a HfO₂ layer, wherein said tensile silicon nitride layer and said HfO₂ l ayer are continuously present atop [[the]] said uppermost surface of said graphene layer.
1. 2
  Dependent← claim 1base substrate (semiconductor, dielectric, or conductive material)semiconductor structure with bilayer gate dielectric on graphene
  The semiconductor structure of Claim 1, wherein said base substrate is a semiconductor material, a dielectric material, a conductive material or combinations thereof.
2. 3
  Dependent← claim 1SiCsemiconductor structure with bilayer gate dielectric on graphene
  The semiconductor structure of Claim 1, wherein said base substrate is comprised of SiC.
3. 4
  Dependent← claim 1Si₃N₄semiconductor structure with bilayer gate dielectric on graphene
  The semiconductor structure of Claim 1, wherein said tensile silicon nitride layer has a thickness from 1 nm to 15 nm.
4. 5
  Dependent← claim 1HfO₂semiconductor structure with bilayer gate dielectric on graphene
  The semiconductor structure of Claim 1, wherein said Hf O₂ layer has a thickness from 2 nm to 500 nm. 2 I \ IBM\1 05\28151 \ AMEND\28151 am l doc
5. 6
  Dependent← claim 1Csemiconductor structure with bilayer gate dielectric on graphene
  The semiconductor structure of Claim 1, wherein said graphene layer has an epitaxial relationship with [[the]] said underlying base substrate. currently amended
7
Independent
canceled
8
IndependentCSi₃N₄HfO₂graphene-containing semiconductor device with bilayer gate dielectric
A semiconductor device comprising: a base substrate having an uppermost surface; and a graphene-containing semiconductor device located on [[the]] said uppermost surface of [[the]] said base substrate, wherein said graphene-containing semiconductor device includes a graphene layer located on said uppermost surface of said base substrate, and a bilayer gate dielectric located on an uppermost surface of [[the]] sa id graphene layer, wherein said bilayer gate dielectric includes, from bottom to top, a tensile silicon nitride layer and a Hf₀ 2 layer, and wherein said tensile silicon nitride layer and said Hf O₂ l ayer are continuously present atop [[the]] sa id uppermost surface of said graphene layer.
1. 9
  Dependent← claim 8Cgraphene-containing semiconductor device with bilayer gate dielectric
  The semiconductor device of Claim 8, wherein said graphene-containing semiconductor device is a ﬁeld eﬀect transistor, and wherein at least a portion of said graphene layer serves as a channel of said ﬁeld eﬀect transistor.
2. 15
  Dependent← claim 8base substrate (semiconductor, dielectric, or conductive material)graphene-containing semiconductor device with bilayer gate dielectric
  The sem i conductor device of Claim 8, wherein said base substrate is a semiconductor material, a dielectric material, a conductive material or combinations thereof. 4 I \IBM \10 5\28151\A M END\28 1 51 am l doc
3. 16
  Dependent← claim 8SiCgraphene-containing semiconductor device with bilayer gate dielectric
  The semiconductor device of Claim 8, wherein said base substrate is comprised of SiC.
17
IndependentCSi₃N₄HfO₂
A method comprising: providing a graphene layer on an uppermost surface of a base substrate; forming a tensile silicon nitride layer on an uppermost surface of said graphene layer; and forming a Hf O 2 layer on an uppermost surface of said tensile silicon nitride layer, wherein said tensile silicon nitride layer and said HfO₂ layer are continuously present atop [[the]] sa id uppermost surface of said graphene layer.
1. 18
  Dependent← claim 17C
  (Currently Amended and Withdrawn) The method of Claim 17, wherein said providing [[the]] said graphene layer comprises epitaxial growth.
2. 23
  Dependent← claim 17Si₃N₄
  (Currently Amended and Withdrawn) The method of Claim 17, wherein said tensile silicon nitride layer is a tnieilc nitride ﬁlm formed by plasma chemical vapor deposition at a temperature between 350 ° C and 450 °C.
3. 24
  Dependent← claim 17CHfO₂
  The method of Claim 17, further comprising forming a source region in contact with one portion of said graphene layer and a drain region in contact with another portion of [[the]] sai d graphene layer, and forming a gate conductor on an uppermost surface of said Hf O 2 layer and located between [[the]] said source region and [[the]] said drain region.
4. 25
  Dependent← claim 17C
  (Currently Amended and Withdrawn) The method of Claim 17, wherein said graphene layer is patterned prior to forming [[the]] said tensile silicon nitride layer and [[the]] said Hf O 2 layer. 6 I \IBM\ 1 05\28151\A M END\28151 am l doc
27
IndependentCSi₃N₄HfO₂graphene field effect transistor with bilayer gate dielectric (top-contact source/drain on graphene)
A semiconductor device comprising: a base substrate having an uppermost surface; and a graphene-containing semiconductor device located on said uppermost surface of said base substrate, wherein said graphene-containing semiconductor device is a ﬁeld eﬀect transistor and comprises: a graphene layer located on said uppermost surface of said base substrate, wherein at least a portion of said graphene layer serves as a channel of said ﬁeld eﬀect transistor; a bilayer gate dielectric located on an uppermost surface of said graphene layer, wherein said bilayer gate dielectric includes, from bottom to top, a silicon nitride layer and a HfO 2 layer, and wherein said silicon nitride layer and said Hf O 2 layer are continuously present atop said uppermost surface of said graphene layer; and a source region in contact with one portion of said graphene layer and a drain region in contact with another portion of said graphene layer, wherein a portion of said source 7 I \IBM\105\ 28151 \AM END\28151 am l doc region is located on a portion of said uppermost surface of said graphene layer and a portion of said drain region is located on another portion of said uppermost surface of said graphene layer.
28
IndependentCSi₃N₄HfO₂graphene field effect transistor with bilayer gate dielectric and self-aligned gate conductor
A semiconductor device comprising: a base substrate having an uppermost surface; and a graphene-containing semiconductor device located on said uppermost surface of said base substrate, wherein said graphene-containing semiconductor device is a ﬁeld eﬀect transistor and comprises: a graphene layer located on said uppermost surface of said base substrate, wherein at least a portion of said graphene layer serves as a channel of said ﬁeld eﬀect transistor; a bilayer gate dielectric located on an uppermost surface of said graphene layer, wherein said bilayer gate dielectric includes, from bottom to top, a silicon nitride layer and a HfO 2 layer, and wherein said silicon nitride layer and said Hf O 2 layer are continuously present atop said uppermost surface of said graphene layer; a source region in contact with one portion of said graphene layer and a drain region in contact with another portion of atop an uppermost surface of said Hf O 2 layer and drain region, wherein a portion of said bilayer gate upper surface of said source region and another a sidewall and an upper surface of said drain region. doc said graphene layer; and a gate conductor located located between said source region and said dielectric is located on a sidewall and an portion of said bilayer gate dielectric is located on 8 I \ BM\ 1 05\28151\AMEND\28151 am l

Device structures

Layer stacks claimed or described, ordered top of device to substrate.

semiconductor structure with bilayer gate dielectric on graphene

HfO₂gate dielectric top

Si₃N₄gate dielectric bottom

Cchannel

base substrate (semiconductor, dielectric, or conductive material)substrate

graphene-containing semiconductor device with bilayer gate dielectric

HfO₂gate dielectric top

Materials

Materials described outside the worked examples.

graphene

Channel Material

tensile silicon nitride

Si₃N₄

Gate Dielectric Wetting Layer

Process steps

Additional fabrication and treatment steps described in the patent.

Epitaxial Growth

Step 1

Temperature

1400, 2000°C

Ambient

inert ambient (second anneal); dilute silicon-containing ambient (first anneal)

Characterization

Measurements and analyses referenced in the patent, with their drawing references.

afm

AFM

FIG. 1 1 B and 1 1 C respectively, are cross section AFM images at diﬀerent magniﬁcations illustrating the roughness of the HfO₂ layer that was formed atop the …

Figure references

FIG. 1

graphenegraphene

Reported properties

Performance values and ranges asserted in the specification or claims.

Property	Value	Material
low EOT definition: EOT less than half the real total dielectric stack thickness; specifically EOT < 20 nm	≤ 20 nm	—
Temperature	810–1250 °C

Why these are connected

Related documents with shared materials, methods, properties, or citations.

BILAYER GATE DIELECTRIC WITH LOW EQUIVALENT OXIDE THICKNESS FOR GRAPHENE DEVICES | Matter42 Literature