Patent
US 8,587,065LOCAL BOTTOM GATES FOR GRAPHENE AND CARBON NANOTUBE DEVICES
Zhihong Chen
US
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Patent
Atlas literature
Patent
US 8,587,065Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-5 are diagrams illustrating an exemplary methodology for fabricating a transistor device having a channel formed from a nanoscale material, such as …
FIG. 2 is a three-dimensional diagram illustrating a gate material having been deposited into the trench to form a gate according to an embodiment of the …
FIG. 3 is a three-dimensional diagram illustrating a dielectric layer having been deposited over the insulator and gate according to an embodiment of the …
FIG. 4 is a three-dimensional diagram illustrating a carbon nanotube channel having been formed on the dielectric layer over the gate and source and drain …
FIG. 5 is a three-dimensional diagram illustrating a graphene channel having been formed on the dielectric layer over the gate and source and drain contacts …
FIG. 6 is a cross-sectional diagram illustrating a dry etch through a patterned poly (methyl methacrylate) (PMMA) resist mask having been used to define …
FIG. 7 is a cross-sectional diagram illustrating a wet etch having been used to undercut the PMMA and to increase the overall depth of the trenches according …
FIG. 8 is a cross-sectional diagram illustrating metal layers having been deposited in the trenches followed by a lift-off process which results in metal gates …
FIG. 9 is an atomic force microscope (AFM) image 900 of a local bottom gate 902 formed using the above-described process. Local bottom gate 902 was formed from …
FIG. 10 is a scanning electron microscope (SEM) image 1000 of a local bottom gate 1002 formed using the above- described process. Local bottom gate 1002 was …
FIG. 11 is a SEM image of a palladium (Pd) metal gate and an aluminum (Al) metal gate, both covered with a hafnium oxide (Hf O 2) dielectric layer, on which …
FIG. 12 is a SEM image of a Pd metal gate and an Al metal gate, both covered with a Hf O 2 dielectric layer, on which carbon nanotubes were transferred from a …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor device, comprising: a substrate; an insulator on the substrate; a gate embedded in the insulator with a top surface of the gate being substantially coplanar with a surface of the insulator; a dielectric layer over the gate and insulator; a channel comprising a carbon nanostructure material formed on the dielectric layer over the gate, wherein the dielectric layer over the gate and the insulator provides a flat surface on which the channel is formed; and source and drain contacts connected by the channel.
The device of claim 1, wherein the carbon nanostructure material comprises carbon nanotubes.
The device of claim 1, wherein the carbon nanostructure material comprises graphene.
The device of claim 1, wherein the insulator comprises silicon dioxide.
The device of claim 1, wherein the gate comprises one or more metals.
The device of claim 1, wherein the gate comprises poly-silicon.
The device of claim 1, wherein the dielectric layer comprises one or more of aluminum oxide and hafnium oxide.
YO R₉₂₀₀₉₀₃₈₇US₂ 12 8. The device of claim 1, wherein the dielectric layer has a thickness of less than about 10 nm.
The device of claim 1, wherein the substrate is undoped.
The device of claim 1, wherein the substrate comprises a silicon substrate.
The device of claim 1, wherein each of the than or equal to 4 nm.
The device of claim 1, wherein the dielectric about 10 nm. source and drain contacts overlaps the gate by less layer has a thickness of from about 3 nm to
Layer stacks claimed or described, ordered top of device to substrate.
transistor device with embedded local bottom gate and carbon nanostructure channel
Materials described outside the worked examples.
carbon nanostructure material
substrate
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1-5 are diagrams illustrating an exemplary methodology for fabricating a transistor device having a channel formed from a nanoscale material, such as …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≤ 10 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,587,065Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-5 are diagrams illustrating an exemplary methodology for fabricating a transistor device having a channel formed from a nanoscale material, such as …
FIG. 2 is a three-dimensional diagram illustrating a gate material having been deposited into the trench to form a gate according to an embodiment of the …
FIG. 3 is a three-dimensional diagram illustrating a dielectric layer having been deposited over the insulator and gate according to an embodiment of the …
FIG. 4 is a three-dimensional diagram illustrating a carbon nanotube channel having been formed on the dielectric layer over the gate and source and drain …
FIG. 5 is a three-dimensional diagram illustrating a graphene channel having been formed on the dielectric layer over the gate and source and drain contacts …
FIG. 6 is a cross-sectional diagram illustrating a dry etch through a patterned poly (methyl methacrylate) (PMMA) resist mask having been used to define …
FIG. 7 is a cross-sectional diagram illustrating a wet etch having been used to undercut the PMMA and to increase the overall depth of the trenches according …
FIG. 8 is a cross-sectional diagram illustrating metal layers having been deposited in the trenches followed by a lift-off process which results in metal gates …
FIG. 9 is an atomic force microscope (AFM) image 900 of a local bottom gate 902 formed using the above-described process. Local bottom gate 902 was formed from …
FIG. 10 is a scanning electron microscope (SEM) image 1000 of a local bottom gate 1002 formed using the above- described process. Local bottom gate 1002 was …
FIG. 11 is a SEM image of a palladium (Pd) metal gate and an aluminum (Al) metal gate, both covered with a hafnium oxide (Hf O 2) dielectric layer, on which …
FIG. 12 is a SEM image of a Pd metal gate and an Al metal gate, both covered with a Hf O 2 dielectric layer, on which carbon nanotubes were transferred from a …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor device, comprising: a substrate; an insulator on the substrate; a gate embedded in the insulator with a top surface of the gate being substantially coplanar with a surface of the insulator; a dielectric layer over the gate and insulator; a channel comprising a carbon nanostructure material formed on the dielectric layer over the gate, wherein the dielectric layer over the gate and the insulator provides a flat surface on which the channel is formed; and source and drain contacts connected by the channel.
The device of claim 1, wherein the carbon nanostructure material comprises carbon nanotubes.
The device of claim 1, wherein the carbon nanostructure material comprises graphene.
The device of claim 1, wherein the insulator comprises silicon dioxide.
The device of claim 1, wherein the gate comprises one or more metals.
The device of claim 1, wherein the gate comprises poly-silicon.
The device of claim 1, wherein the dielectric layer comprises one or more of aluminum oxide and hafnium oxide.
YO R₉₂₀₀₉₀₃₈₇US₂ 12 8. The device of claim 1, wherein the dielectric layer has a thickness of less than about 10 nm.
The device of claim 1, wherein the substrate is undoped.
The device of claim 1, wherein the substrate comprises a silicon substrate.
The device of claim 1, wherein each of the than or equal to 4 nm.
The device of claim 1, wherein the dielectric about 10 nm. source and drain contacts overlaps the gate by less layer has a thickness of from about 3 nm to
Layer stacks claimed or described, ordered top of device to substrate.
transistor device with embedded local bottom gate and carbon nanostructure channel
Materials described outside the worked examples.
carbon nanostructure material
substrate
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1-5 are diagrams illustrating an exemplary methodology for fabricating a transistor device having a channel formed from a nanoscale material, such as …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≤ 10 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,587,065Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-5 are diagrams illustrating an exemplary methodology for fabricating a transistor device having a channel formed from a nanoscale material, such as …
FIG. 2 is a three-dimensional diagram illustrating a gate material having been deposited into the trench to form a gate according to an embodiment of the …
FIG. 3 is a three-dimensional diagram illustrating a dielectric layer having been deposited over the insulator and gate according to an embodiment of the …
FIG. 4 is a three-dimensional diagram illustrating a carbon nanotube channel having been formed on the dielectric layer over the gate and source and drain …
FIG. 5 is a three-dimensional diagram illustrating a graphene channel having been formed on the dielectric layer over the gate and source and drain contacts …
FIG. 6 is a cross-sectional diagram illustrating a dry etch through a patterned poly (methyl methacrylate) (PMMA) resist mask having been used to define …
FIG. 7 is a cross-sectional diagram illustrating a wet etch having been used to undercut the PMMA and to increase the overall depth of the trenches according …
FIG. 8 is a cross-sectional diagram illustrating metal layers having been deposited in the trenches followed by a lift-off process which results in metal gates …
FIG. 9 is an atomic force microscope (AFM) image 900 of a local bottom gate 902 formed using the above-described process. Local bottom gate 902 was formed from …
FIG. 10 is a scanning electron microscope (SEM) image 1000 of a local bottom gate 1002 formed using the above- described process. Local bottom gate 1002 was …
FIG. 11 is a SEM image of a palladium (Pd) metal gate and an aluminum (Al) metal gate, both covered with a hafnium oxide (Hf O 2) dielectric layer, on which …
FIG. 12 is a SEM image of a Pd metal gate and an Al metal gate, both covered with a Hf O 2 dielectric layer, on which carbon nanotubes were transferred from a …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor device, comprising: a substrate; an insulator on the substrate; a gate embedded in the insulator with a top surface of the gate being substantially coplanar with a surface of the insulator; a dielectric layer over the gate and insulator; a channel comprising a carbon nanostructure material formed on the dielectric layer over the gate, wherein the dielectric layer over the gate and the insulator provides a flat surface on which the channel is formed; and source and drain contacts connected by the channel.
The device of claim 1, wherein the carbon nanostructure material comprises carbon nanotubes.
The device of claim 1, wherein the carbon nanostructure material comprises graphene.
The device of claim 1, wherein the insulator comprises silicon dioxide.
The device of claim 1, wherein the gate comprises one or more metals.
The device of claim 1, wherein the gate comprises poly-silicon.
The device of claim 1, wherein the dielectric layer comprises one or more of aluminum oxide and hafnium oxide.
YO R₉₂₀₀₉₀₃₈₇US₂ 12 8. The device of claim 1, wherein the dielectric layer has a thickness of less than about 10 nm.
The device of claim 1, wherein the substrate is undoped.
The device of claim 1, wherein the substrate comprises a silicon substrate.
The device of claim 1, wherein each of the than or equal to 4 nm.
The device of claim 1, wherein the dielectric about 10 nm. source and drain contacts overlaps the gate by less layer has a thickness of from about 3 nm to
Layer stacks claimed or described, ordered top of device to substrate.
transistor device with embedded local bottom gate and carbon nanostructure channel
Materials described outside the worked examples.
carbon nanostructure material
substrate
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1-5 are diagrams illustrating an exemplary methodology for fabricating a transistor device having a channel formed from a nanoscale material, such as …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≤ 10 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,587,065Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-5 are diagrams illustrating an exemplary methodology for fabricating a transistor device having a channel formed from a nanoscale material, such as …
FIG. 2 is a three-dimensional diagram illustrating a gate material having been deposited into the trench to form a gate according to an embodiment of the …
FIG. 3 is a three-dimensional diagram illustrating a dielectric layer having been deposited over the insulator and gate according to an embodiment of the …
FIG. 4 is a three-dimensional diagram illustrating a carbon nanotube channel having been formed on the dielectric layer over the gate and source and drain …
FIG. 5 is a three-dimensional diagram illustrating a graphene channel having been formed on the dielectric layer over the gate and source and drain contacts …
FIG. 6 is a cross-sectional diagram illustrating a dry etch through a patterned poly (methyl methacrylate) (PMMA) resist mask having been used to define …
FIG. 7 is a cross-sectional diagram illustrating a wet etch having been used to undercut the PMMA and to increase the overall depth of the trenches according …
FIG. 8 is a cross-sectional diagram illustrating metal layers having been deposited in the trenches followed by a lift-off process which results in metal gates …
FIG. 9 is an atomic force microscope (AFM) image 900 of a local bottom gate 902 formed using the above-described process. Local bottom gate 902 was formed from …
FIG. 10 is a scanning electron microscope (SEM) image 1000 of a local bottom gate 1002 formed using the above- described process. Local bottom gate 1002 was …
FIG. 11 is a SEM image of a palladium (Pd) metal gate and an aluminum (Al) metal gate, both covered with a hafnium oxide (Hf O 2) dielectric layer, on which …
FIG. 12 is a SEM image of a Pd metal gate and an Al metal gate, both covered with a Hf O 2 dielectric layer, on which carbon nanotubes were transferred from a …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor device, comprising: a substrate; an insulator on the substrate; a gate embedded in the insulator with a top surface of the gate being substantially coplanar with a surface of the insulator; a dielectric layer over the gate and insulator; a channel comprising a carbon nanostructure material formed on the dielectric layer over the gate, wherein the dielectric layer over the gate and the insulator provides a flat surface on which the channel is formed; and source and drain contacts connected by the channel.
The device of claim 1, wherein the carbon nanostructure material comprises carbon nanotubes.
The device of claim 1, wherein the carbon nanostructure material comprises graphene.
The device of claim 1, wherein the insulator comprises silicon dioxide.
The device of claim 1, wherein the gate comprises one or more metals.
The device of claim 1, wherein the gate comprises poly-silicon.
The device of claim 1, wherein the dielectric layer comprises one or more of aluminum oxide and hafnium oxide.
YO R₉₂₀₀₉₀₃₈₇US₂ 12 8. The device of claim 1, wherein the dielectric layer has a thickness of less than about 10 nm.
The device of claim 1, wherein the substrate is undoped.
The device of claim 1, wherein the substrate comprises a silicon substrate.
The device of claim 1, wherein each of the than or equal to 4 nm.
The device of claim 1, wherein the dielectric about 10 nm. source and drain contacts overlaps the gate by less layer has a thickness of from about 3 nm to
Layer stacks claimed or described, ordered top of device to substrate.
transistor device with embedded local bottom gate and carbon nanostructure channel
Materials described outside the worked examples.
carbon nanostructure material
substrate
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 1-5 are diagrams illustrating an exemplary methodology for fabricating a transistor device having a channel formed from a nanoscale material, such as …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | ≤ 10 nm | — |
Related documents with shared materials, methods, properties, or citations.
dielectric layer
carbon nanotubes
graphene
silicon dioxide
SiO₂
one or more metals
poly-silicon
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
silicon
Si
aluminum
Al
titanium
Ti
palladium
Pd
FIG. 5 is a three-dimensional diagram illustrating a graphene channel having been formed on the dielectric layer over the gate and source and drain contacts …
FIG. 8 is a cross-sectional diagram illustrating metal layers having been deposited in the trenches followed by a lift-off process which results in metal gates …
FIG. 9 is an atomic force microscope (AFM) image 900 of a local bottom gate 902 formed using the above-described process. Local bottom gate 902 was formed from …
FIG. 10 is a scanning electron microscope (SEM) image 1000 of a local bottom gate 1002 formed using the above- described process. Local bottom gate 1002 was …
FIG. 11 is a SEM image of a palladium (Pd) metal gate and an aluminum (Al) metal gate, both covered with a hafnium oxide (Hf O 2) dielectric layer, on which …
FIG. 12 is a SEM image of a Pd metal gate and an Al metal gate, both covered with a Hf O 2 dielectric layer, on which carbon nanotubes were transferred from a …
dielectric layer
carbon nanotubes
graphene
silicon dioxide
SiO₂
one or more metals
poly-silicon
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
silicon
Si
aluminum
Al
titanium
Ti
palladium
Pd
FIG. 5 is a three-dimensional diagram illustrating a graphene channel having been formed on the dielectric layer over the gate and source and drain contacts …
FIG. 8 is a cross-sectional diagram illustrating metal layers having been deposited in the trenches followed by a lift-off process which results in metal gates …
FIG. 9 is an atomic force microscope (AFM) image 900 of a local bottom gate 902 formed using the above-described process. Local bottom gate 902 was formed from …
FIG. 10 is a scanning electron microscope (SEM) image 1000 of a local bottom gate 1002 formed using the above- described process. Local bottom gate 1002 was …
FIG. 11 is a SEM image of a palladium (Pd) metal gate and an aluminum (Al) metal gate, both covered with a hafnium oxide (Hf O 2) dielectric layer, on which …
FIG. 12 is a SEM image of a Pd metal gate and an Al metal gate, both covered with a Hf O 2 dielectric layer, on which carbon nanotubes were transferred from a …
dielectric layer
carbon nanotubes
graphene
silicon dioxide
SiO₂
one or more metals
poly-silicon
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
silicon
Si
aluminum
Al
titanium
Ti
palladium
Pd
FIG. 5 is a three-dimensional diagram illustrating a graphene channel having been formed on the dielectric layer over the gate and source and drain contacts …
FIG. 8 is a cross-sectional diagram illustrating metal layers having been deposited in the trenches followed by a lift-off process which results in metal gates …
FIG. 9 is an atomic force microscope (AFM) image 900 of a local bottom gate 902 formed using the above-described process. Local bottom gate 902 was formed from …
FIG. 10 is a scanning electron microscope (SEM) image 1000 of a local bottom gate 1002 formed using the above- described process. Local bottom gate 1002 was …
FIG. 11 is a SEM image of a palladium (Pd) metal gate and an aluminum (Al) metal gate, both covered with a hafnium oxide (Hf O 2) dielectric layer, on which …
FIG. 12 is a SEM image of a Pd metal gate and an Al metal gate, both covered with a Hf O 2 dielectric layer, on which carbon nanotubes were transferred from a …
dielectric layer
carbon nanotubes
graphene
silicon dioxide
SiO₂
one or more metals
poly-silicon
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
silicon
Si
aluminum
Al
titanium
Ti
palladium
Pd
FIG. 5 is a three-dimensional diagram illustrating a graphene channel having been formed on the dielectric layer over the gate and source and drain contacts …
FIG. 8 is a cross-sectional diagram illustrating metal layers having been deposited in the trenches followed by a lift-off process which results in metal gates …
FIG. 9 is an atomic force microscope (AFM) image 900 of a local bottom gate 902 formed using the above-described process. Local bottom gate 902 was formed from …
FIG. 10 is a scanning electron microscope (SEM) image 1000 of a local bottom gate 1002 formed using the above- described process. Local bottom gate 1002 was …
FIG. 11 is a SEM image of a palladium (Pd) metal gate and an aluminum (Al) metal gate, both covered with a hafnium oxide (Hf O 2) dielectric layer, on which …
FIG. 12 is a SEM image of a Pd metal gate and an Al metal gate, both covered with a Hf O 2 dielectric layer, on which carbon nanotubes were transferred from a …