Patent
US 9,293,536BILAYER GRAPHENE TUNNELING FIELD EFFECT TRANSISTOR
Amirhasan Nourbakhsh
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,293,536Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows schematically a BLG TFET according to a first aspect.
FIG. 2 shows schematically a biased BLG TFET according to embodiments of the first aspect (top) and the corresponding band diagram 15 scheme of the BLG …
FIG. 3 shows schematically a biased BLG TFET according to embodiments of the first aspect (top) and the corresponding band diagram scheme of the BLG TFET …
FIG. 4 shows the transfer characteristics for a BLG TFET according 20 embodiments of the first aspect in the ON-state.
FIG. 5 shows schematically a BLG TFET according to a third aspect.
FIG. 6 shows schematically a biased BLG TFET according to embodiments of the third aspect (top) and the corresponding band 25 diagram scheme of the BLG TFET …
FIG. 7 shows schematically a biased BLG TFET according to embodiments of the third aspect (top) and the corresponding band diagram scheme of the BLG TFET …
FIG. 8 shows the transfer characteristics for a BLG TFET according 30 embodiments of the third aspect in the ON-state. -18-
FIGS. 9-15 show schematically different steps of a method for manufacturing a BLG TFET of the first aspect according to a fifth aspect. Although the specific …
FIG. 10) a trench 1 100 a is provided in the bottom dielectric layer 100 b. This trench is preferably formed using standard patterning and etching techniques …
FIG. 11) the trench 1100 a is filled with conducting gate material as such providing the bottom gate electrodes 121. The 5 conducting bottom gate material …
FIG. 12) the first gate dielectric layer 111 is provided on the bottom gate electrode and on the bottom dielectric layer 10 1 00 b. The f irst gate dielectric …
FIG. 13) a bilayer graphene 103 is formed on the first 15 gate dielectric layer 111 and a second gate dielectric layer 112 is formed on the bilayer graphene …
FIG. 14) the top gate electrode 133 is formed by depositing conducting top gate material and patterning the metal material. Furthermore gate contacts 233, 221 …
FIG. 15). Depending on the positioning of the different bottom gate electrodes and/or top gate electrodes different configurations for the BLG device are …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
The bilayer graphene tunnelling field effect transistor of
The bilayer graphene tunneling field effect transistor of Claim 2, wherein a p-i-n junction or n-i-p junction is electrostatically induced in the bilayer graphene.
The bila y er graphene tunnelling field effect transistor of Claim [[1]] 2, further comprising a first gate dielectric layer on a substrate, wherein the bila yer graphene comprises a first graphene layer and a second graphene layer, wherein the first graphene layer and the second graphene layer are adjoining, the bila y er graphene being sandwiched in between with the first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer contacting the first graphene layer and the second gate dielectric layer contacting the second graphene layer, and the top gate electrode contacting the second gate dielectric layer opposite to the second graphene layer.
The bila y er graphene tunnelling field effect transistor of Claim 3, wherein the first and second gate dielectric layers have a same equivalent oxide thickness.
The bila y er graphene tunneling field effect transistor of Claim 3, further comprising a second top gate electrode capacitively coupled to the top surface of the bila y er graphene and spaced apart along the top surface from the first top gate electrode, wherein the bottom gate electrode fully overlaps the first top gate electrode and the second top gate electrode, thereby defining a channel region capacitively coupled to the bottom gate electrode and the first top gate electrode, a source region capacitively coupled to the second top gate electrode and the bottom gate electrode, a ba rri er region only capacitively coupled to the bottom gate electrode, and a drain region only capacitively coupled to the bottom gate electrode, wherein the transistor comprises a first top gate electrode and a second top gate electrode and wherein -3- Application No.: 14/572364 Filing Date: both the first top gate electrode and the second top gate electrode contact the second gate dielectric layer opposite to the second graphene layer.
The bila y er graphene tunnelling field effect transistor of Claim [[1]] 2, wherein the bottom gate electrode is embedded in a substrate, wherein the substrate comprises a semiconductor layer with a bottom dielectric layer on top, wherein the bottom gate electrode is embedded in the bottom dielectric layer, wherein the bottom gate electrode has a top surface and the bottom dielectric layer has a top dielectric surface, and -2- Application No.: 14/572364 Filing Date: wherein the top surface of the bottom gate electrode is coplanar with the top dielectric surface of the bottom dielectric layer.
The bilayer graphene tunnelling field effect transistor of
The bilayer graphene tunnelling field effect transistor of Claim 5, further comprising a first gate dielectric layer on a substrate, wherein the bilayer graphene comprises a -4- Application No.: 14/572364 Filing Date: first graphene layer and a second graphene layer, wherein the first graphene layer and the second graphene layer are adjoining, the bilayer graphene being sandwiched in between with the first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer contacting the first graphene layer and the second gate dielectric layer contacting the second graphene layer, and the top gate electrode contacting the second gate dielectric layer opposite to the second graphene layer.
The bilayer graphene tunnelling field effect transistor of Claim 5, wherein the bottom gate electrode is embedded in a substrate, wherein the substrate comprises a semiconductor layer with a bottom dielectric layer on top, wherein the bottom gate electrode is embedded in the bottom dielectric layer, wherein the bottom gate electrode has a top surface and the bottom dielectric layer has a top dielectric surface, and wherein the top surface of the bottom gate electrode is coplanar with the top dielectric surface of the bottom dielectric layer.
The bilayer graphene tunnelling field effect transistor of Claim 5, further comprising a different contact for each of the at least a top and a bottom gate electrode configured to separately bias each of the at least a top and a bottom gate electrode.
The bilayer graphene tunnelling field effect transistor of Claim 5, wherein the bilayer graphene layer is chemically undoped.
The bila y er graphene tunnelling field effect transistor of Claim [[1]] SVG 14572364.12-07-2015.IHWNFCKEPXXIFW3.CLM.2.20.549.1911.585.1953.svg 0.14 0.12 Chemistry Black and white further comprising a different contact for each of the at least a top and a bottom gate electrode configured to separately bias each of the at least a top and a bottom gate electrode.
The bilayer graphene tunnelling field effect transistor of Claim [[1]] SVG 14572364.12-07-2015.IHWNFCKEPXXIFW3.CLM.3.6.540.672.576.714.svg 0.14 0.12 Chemistry Black and white wherein the bilayer graphene layer is chemically undoped.
The bilayer graphene tunnelling field effect transistor of
The bilayer graphene tunneling field effect transistor of Claim 10, wherein the p-i-n junction or an n-i-p junction is electrostatically induced by applying a voltage to a top gate electrode and a voltage of opposite sign to the bottom gate electrode.
The bilayer graphene tunnelling field effect transistor of Claim 10, further comprising a first gate dielectric layer on a substrate, wherein the bilayer graphene comprises a first graphene layer and a second graphene layer, wherein the first graphene layer and the second graphene layer are adjoining, the bilayer graphene being sandwiched in between with the first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer contacting the first graphene layer and the second gate dielectric layer contacting the second graphene layer, and the top gate electrode contacting the second gate dielectric layer opposite to the second graphene layer.
The bilayer graphene tunnelling field effect transistor of Claim 10, wherein the bottom gate electrode is embedded in a substrate, wherein the substrate comprises a semiconductor layer with a bottom dielectric layer on top, wherein the bottom gate electrode is embedded in the bottom dielectric layer, wherein the bottom gate electrode has a top surface and -5- Application No.: 14/572364 Filing Date: the bottom dielectric layer has a top dielectric surface, and wherein the top surface of the bottom dielectric surface of the bottom dielectric layer.
The bilayer graphene tunnelling field effect graphene layer is chemically undoped. -6-gate electrode is coplanar with the top transistor of Claim 10, further comprising a bottom gate electrode configured to separately electrode. transistor of Claim 10, wherein the bilayer
The bilayer graphene tunnelling field effect different contact for each of the at least a top and bias each of the at least a top and a bottom gate
Layer stacks claimed or described, ordered top of device to substrate.
bilayer graphene tunnelling field effect transistor (single top gate)
bilayer graphene tunnelling field effect transistor (dual top gate with barrier region)
Materials described outside the worked examples.
bilayer graphene
first gate dielectric layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Optical Band Gap | 0–300 meV | bilayer graphene |
Fet On Off Ratio | 100 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,293,536Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows schematically a BLG TFET according to a first aspect.
FIG. 2 shows schematically a biased BLG TFET according to embodiments of the first aspect (top) and the corresponding band diagram 15 scheme of the BLG …
FIG. 3 shows schematically a biased BLG TFET according to embodiments of the first aspect (top) and the corresponding band diagram scheme of the BLG TFET …
FIG. 4 shows the transfer characteristics for a BLG TFET according 20 embodiments of the first aspect in the ON-state.
FIG. 5 shows schematically a BLG TFET according to a third aspect.
FIG. 6 shows schematically a biased BLG TFET according to embodiments of the third aspect (top) and the corresponding band 25 diagram scheme of the BLG TFET …
FIG. 7 shows schematically a biased BLG TFET according to embodiments of the third aspect (top) and the corresponding band diagram scheme of the BLG TFET …
FIG. 8 shows the transfer characteristics for a BLG TFET according 30 embodiments of the third aspect in the ON-state. -18-
FIGS. 9-15 show schematically different steps of a method for manufacturing a BLG TFET of the first aspect according to a fifth aspect. Although the specific …
FIG. 10) a trench 1 100 a is provided in the bottom dielectric layer 100 b. This trench is preferably formed using standard patterning and etching techniques …
FIG. 11) the trench 1100 a is filled with conducting gate material as such providing the bottom gate electrodes 121. The 5 conducting bottom gate material …
FIG. 12) the first gate dielectric layer 111 is provided on the bottom gate electrode and on the bottom dielectric layer 10 1 00 b. The f irst gate dielectric …
FIG. 13) a bilayer graphene 103 is formed on the first 15 gate dielectric layer 111 and a second gate dielectric layer 112 is formed on the bilayer graphene …
FIG. 14) the top gate electrode 133 is formed by depositing conducting top gate material and patterning the metal material. Furthermore gate contacts 233, 221 …
FIG. 15). Depending on the positioning of the different bottom gate electrodes and/or top gate electrodes different configurations for the BLG device are …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
The bilayer graphene tunnelling field effect transistor of
The bilayer graphene tunneling field effect transistor of Claim 2, wherein a p-i-n junction or n-i-p junction is electrostatically induced in the bilayer graphene.
The bila y er graphene tunnelling field effect transistor of Claim [[1]] 2, further comprising a first gate dielectric layer on a substrate, wherein the bila yer graphene comprises a first graphene layer and a second graphene layer, wherein the first graphene layer and the second graphene layer are adjoining, the bila y er graphene being sandwiched in between with the first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer contacting the first graphene layer and the second gate dielectric layer contacting the second graphene layer, and the top gate electrode contacting the second gate dielectric layer opposite to the second graphene layer.
The bila y er graphene tunnelling field effect transistor of Claim 3, wherein the first and second gate dielectric layers have a same equivalent oxide thickness.
The bila y er graphene tunneling field effect transistor of Claim 3, further comprising a second top gate electrode capacitively coupled to the top surface of the bila y er graphene and spaced apart along the top surface from the first top gate electrode, wherein the bottom gate electrode fully overlaps the first top gate electrode and the second top gate electrode, thereby defining a channel region capacitively coupled to the bottom gate electrode and the first top gate electrode, a source region capacitively coupled to the second top gate electrode and the bottom gate electrode, a ba rri er region only capacitively coupled to the bottom gate electrode, and a drain region only capacitively coupled to the bottom gate electrode, wherein the transistor comprises a first top gate electrode and a second top gate electrode and wherein -3- Application No.: 14/572364 Filing Date: both the first top gate electrode and the second top gate electrode contact the second gate dielectric layer opposite to the second graphene layer.
The bila y er graphene tunnelling field effect transistor of Claim [[1]] 2, wherein the bottom gate electrode is embedded in a substrate, wherein the substrate comprises a semiconductor layer with a bottom dielectric layer on top, wherein the bottom gate electrode is embedded in the bottom dielectric layer, wherein the bottom gate electrode has a top surface and the bottom dielectric layer has a top dielectric surface, and -2- Application No.: 14/572364 Filing Date: wherein the top surface of the bottom gate electrode is coplanar with the top dielectric surface of the bottom dielectric layer.
The bilayer graphene tunnelling field effect transistor of
The bilayer graphene tunnelling field effect transistor of Claim 5, further comprising a first gate dielectric layer on a substrate, wherein the bilayer graphene comprises a -4- Application No.: 14/572364 Filing Date: first graphene layer and a second graphene layer, wherein the first graphene layer and the second graphene layer are adjoining, the bilayer graphene being sandwiched in between with the first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer contacting the first graphene layer and the second gate dielectric layer contacting the second graphene layer, and the top gate electrode contacting the second gate dielectric layer opposite to the second graphene layer.
The bilayer graphene tunnelling field effect transistor of Claim 5, wherein the bottom gate electrode is embedded in a substrate, wherein the substrate comprises a semiconductor layer with a bottom dielectric layer on top, wherein the bottom gate electrode is embedded in the bottom dielectric layer, wherein the bottom gate electrode has a top surface and the bottom dielectric layer has a top dielectric surface, and wherein the top surface of the bottom gate electrode is coplanar with the top dielectric surface of the bottom dielectric layer.
The bilayer graphene tunnelling field effect transistor of Claim 5, further comprising a different contact for each of the at least a top and a bottom gate electrode configured to separately bias each of the at least a top and a bottom gate electrode.
The bilayer graphene tunnelling field effect transistor of Claim 5, wherein the bilayer graphene layer is chemically undoped.
The bila y er graphene tunnelling field effect transistor of Claim [[1]] SVG 14572364.12-07-2015.IHWNFCKEPXXIFW3.CLM.2.20.549.1911.585.1953.svg 0.14 0.12 Chemistry Black and white further comprising a different contact for each of the at least a top and a bottom gate electrode configured to separately bias each of the at least a top and a bottom gate electrode.
The bilayer graphene tunnelling field effect transistor of Claim [[1]] SVG 14572364.12-07-2015.IHWNFCKEPXXIFW3.CLM.3.6.540.672.576.714.svg 0.14 0.12 Chemistry Black and white wherein the bilayer graphene layer is chemically undoped.
The bilayer graphene tunnelling field effect transistor of
The bilayer graphene tunneling field effect transistor of Claim 10, wherein the p-i-n junction or an n-i-p junction is electrostatically induced by applying a voltage to a top gate electrode and a voltage of opposite sign to the bottom gate electrode.
The bilayer graphene tunnelling field effect transistor of Claim 10, further comprising a first gate dielectric layer on a substrate, wherein the bilayer graphene comprises a first graphene layer and a second graphene layer, wherein the first graphene layer and the second graphene layer are adjoining, the bilayer graphene being sandwiched in between with the first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer contacting the first graphene layer and the second gate dielectric layer contacting the second graphene layer, and the top gate electrode contacting the second gate dielectric layer opposite to the second graphene layer.
The bilayer graphene tunnelling field effect transistor of Claim 10, wherein the bottom gate electrode is embedded in a substrate, wherein the substrate comprises a semiconductor layer with a bottom dielectric layer on top, wherein the bottom gate electrode is embedded in the bottom dielectric layer, wherein the bottom gate electrode has a top surface and -5- Application No.: 14/572364 Filing Date: the bottom dielectric layer has a top dielectric surface, and wherein the top surface of the bottom dielectric surface of the bottom dielectric layer.
The bilayer graphene tunnelling field effect graphene layer is chemically undoped. -6-gate electrode is coplanar with the top transistor of Claim 10, further comprising a bottom gate electrode configured to separately electrode. transistor of Claim 10, wherein the bilayer
The bilayer graphene tunnelling field effect different contact for each of the at least a top and bias each of the at least a top and a bottom gate
Layer stacks claimed or described, ordered top of device to substrate.
bilayer graphene tunnelling field effect transistor (single top gate)
bilayer graphene tunnelling field effect transistor (dual top gate with barrier region)
Materials described outside the worked examples.
bilayer graphene
first gate dielectric layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Optical Band Gap | 0–300 meV | bilayer graphene |
Fet On Off Ratio | 100 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,293,536Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows schematically a BLG TFET according to a first aspect.
FIG. 2 shows schematically a biased BLG TFET according to embodiments of the first aspect (top) and the corresponding band diagram 15 scheme of the BLG …
FIG. 3 shows schematically a biased BLG TFET according to embodiments of the first aspect (top) and the corresponding band diagram scheme of the BLG TFET …
FIG. 4 shows the transfer characteristics for a BLG TFET according 20 embodiments of the first aspect in the ON-state.
FIG. 5 shows schematically a BLG TFET according to a third aspect.
FIG. 6 shows schematically a biased BLG TFET according to embodiments of the third aspect (top) and the corresponding band 25 diagram scheme of the BLG TFET …
FIG. 7 shows schematically a biased BLG TFET according to embodiments of the third aspect (top) and the corresponding band diagram scheme of the BLG TFET …
FIG. 8 shows the transfer characteristics for a BLG TFET according 30 embodiments of the third aspect in the ON-state. -18-
FIGS. 9-15 show schematically different steps of a method for manufacturing a BLG TFET of the first aspect according to a fifth aspect. Although the specific …
FIG. 10) a trench 1 100 a is provided in the bottom dielectric layer 100 b. This trench is preferably formed using standard patterning and etching techniques …
FIG. 11) the trench 1100 a is filled with conducting gate material as such providing the bottom gate electrodes 121. The 5 conducting bottom gate material …
FIG. 12) the first gate dielectric layer 111 is provided on the bottom gate electrode and on the bottom dielectric layer 10 1 00 b. The f irst gate dielectric …
FIG. 13) a bilayer graphene 103 is formed on the first 15 gate dielectric layer 111 and a second gate dielectric layer 112 is formed on the bilayer graphene …
FIG. 14) the top gate electrode 133 is formed by depositing conducting top gate material and patterning the metal material. Furthermore gate contacts 233, 221 …
FIG. 15). Depending on the positioning of the different bottom gate electrodes and/or top gate electrodes different configurations for the BLG device are …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
The bilayer graphene tunnelling field effect transistor of
The bilayer graphene tunneling field effect transistor of Claim 2, wherein a p-i-n junction or n-i-p junction is electrostatically induced in the bilayer graphene.
The bila y er graphene tunnelling field effect transistor of Claim [[1]] 2, further comprising a first gate dielectric layer on a substrate, wherein the bila yer graphene comprises a first graphene layer and a second graphene layer, wherein the first graphene layer and the second graphene layer are adjoining, the bila y er graphene being sandwiched in between with the first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer contacting the first graphene layer and the second gate dielectric layer contacting the second graphene layer, and the top gate electrode contacting the second gate dielectric layer opposite to the second graphene layer.
The bila y er graphene tunnelling field effect transistor of Claim 3, wherein the first and second gate dielectric layers have a same equivalent oxide thickness.
The bila y er graphene tunneling field effect transistor of Claim 3, further comprising a second top gate electrode capacitively coupled to the top surface of the bila y er graphene and spaced apart along the top surface from the first top gate electrode, wherein the bottom gate electrode fully overlaps the first top gate electrode and the second top gate electrode, thereby defining a channel region capacitively coupled to the bottom gate electrode and the first top gate electrode, a source region capacitively coupled to the second top gate electrode and the bottom gate electrode, a ba rri er region only capacitively coupled to the bottom gate electrode, and a drain region only capacitively coupled to the bottom gate electrode, wherein the transistor comprises a first top gate electrode and a second top gate electrode and wherein -3- Application No.: 14/572364 Filing Date: both the first top gate electrode and the second top gate electrode contact the second gate dielectric layer opposite to the second graphene layer.
The bila y er graphene tunnelling field effect transistor of Claim [[1]] 2, wherein the bottom gate electrode is embedded in a substrate, wherein the substrate comprises a semiconductor layer with a bottom dielectric layer on top, wherein the bottom gate electrode is embedded in the bottom dielectric layer, wherein the bottom gate electrode has a top surface and the bottom dielectric layer has a top dielectric surface, and -2- Application No.: 14/572364 Filing Date: wherein the top surface of the bottom gate electrode is coplanar with the top dielectric surface of the bottom dielectric layer.
The bilayer graphene tunnelling field effect transistor of
The bilayer graphene tunnelling field effect transistor of Claim 5, further comprising a first gate dielectric layer on a substrate, wherein the bilayer graphene comprises a -4- Application No.: 14/572364 Filing Date: first graphene layer and a second graphene layer, wherein the first graphene layer and the second graphene layer are adjoining, the bilayer graphene being sandwiched in between with the first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer contacting the first graphene layer and the second gate dielectric layer contacting the second graphene layer, and the top gate electrode contacting the second gate dielectric layer opposite to the second graphene layer.
The bilayer graphene tunnelling field effect transistor of Claim 5, wherein the bottom gate electrode is embedded in a substrate, wherein the substrate comprises a semiconductor layer with a bottom dielectric layer on top, wherein the bottom gate electrode is embedded in the bottom dielectric layer, wherein the bottom gate electrode has a top surface and the bottom dielectric layer has a top dielectric surface, and wherein the top surface of the bottom gate electrode is coplanar with the top dielectric surface of the bottom dielectric layer.
The bilayer graphene tunnelling field effect transistor of Claim 5, further comprising a different contact for each of the at least a top and a bottom gate electrode configured to separately bias each of the at least a top and a bottom gate electrode.
The bilayer graphene tunnelling field effect transistor of Claim 5, wherein the bilayer graphene layer is chemically undoped.
The bila y er graphene tunnelling field effect transistor of Claim [[1]] SVG 14572364.12-07-2015.IHWNFCKEPXXIFW3.CLM.2.20.549.1911.585.1953.svg 0.14 0.12 Chemistry Black and white further comprising a different contact for each of the at least a top and a bottom gate electrode configured to separately bias each of the at least a top and a bottom gate electrode.
The bilayer graphene tunnelling field effect transistor of Claim [[1]] SVG 14572364.12-07-2015.IHWNFCKEPXXIFW3.CLM.3.6.540.672.576.714.svg 0.14 0.12 Chemistry Black and white wherein the bilayer graphene layer is chemically undoped.
The bilayer graphene tunnelling field effect transistor of
The bilayer graphene tunneling field effect transistor of Claim 10, wherein the p-i-n junction or an n-i-p junction is electrostatically induced by applying a voltage to a top gate electrode and a voltage of opposite sign to the bottom gate electrode.
The bilayer graphene tunnelling field effect transistor of Claim 10, further comprising a first gate dielectric layer on a substrate, wherein the bilayer graphene comprises a first graphene layer and a second graphene layer, wherein the first graphene layer and the second graphene layer are adjoining, the bilayer graphene being sandwiched in between with the first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer contacting the first graphene layer and the second gate dielectric layer contacting the second graphene layer, and the top gate electrode contacting the second gate dielectric layer opposite to the second graphene layer.
The bilayer graphene tunnelling field effect transistor of Claim 10, wherein the bottom gate electrode is embedded in a substrate, wherein the substrate comprises a semiconductor layer with a bottom dielectric layer on top, wherein the bottom gate electrode is embedded in the bottom dielectric layer, wherein the bottom gate electrode has a top surface and -5- Application No.: 14/572364 Filing Date: the bottom dielectric layer has a top dielectric surface, and wherein the top surface of the bottom dielectric surface of the bottom dielectric layer.
The bilayer graphene tunnelling field effect graphene layer is chemically undoped. -6-gate electrode is coplanar with the top transistor of Claim 10, further comprising a bottom gate electrode configured to separately electrode. transistor of Claim 10, wherein the bilayer
The bilayer graphene tunnelling field effect different contact for each of the at least a top and bias each of the at least a top and a bottom gate
Layer stacks claimed or described, ordered top of device to substrate.
bilayer graphene tunnelling field effect transistor (single top gate)
bilayer graphene tunnelling field effect transistor (dual top gate with barrier region)
Materials described outside the worked examples.
bilayer graphene
first gate dielectric layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Optical Band Gap | 0–300 meV | bilayer graphene |
Fet On Off Ratio | 100 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,293,536Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows schematically a BLG TFET according to a first aspect.
FIG. 2 shows schematically a biased BLG TFET according to embodiments of the first aspect (top) and the corresponding band diagram 15 scheme of the BLG …
FIG. 3 shows schematically a biased BLG TFET according to embodiments of the first aspect (top) and the corresponding band diagram scheme of the BLG TFET …
FIG. 4 shows the transfer characteristics for a BLG TFET according 20 embodiments of the first aspect in the ON-state.
FIG. 5 shows schematically a BLG TFET according to a third aspect.
FIG. 6 shows schematically a biased BLG TFET according to embodiments of the third aspect (top) and the corresponding band 25 diagram scheme of the BLG TFET …
FIG. 7 shows schematically a biased BLG TFET according to embodiments of the third aspect (top) and the corresponding band diagram scheme of the BLG TFET …
FIG. 8 shows the transfer characteristics for a BLG TFET according 30 embodiments of the third aspect in the ON-state. -18-
FIGS. 9-15 show schematically different steps of a method for manufacturing a BLG TFET of the first aspect according to a fifth aspect. Although the specific …
FIG. 10) a trench 1 100 a is provided in the bottom dielectric layer 100 b. This trench is preferably formed using standard patterning and etching techniques …
FIG. 11) the trench 1100 a is filled with conducting gate material as such providing the bottom gate electrodes 121. The 5 conducting bottom gate material …
FIG. 12) the first gate dielectric layer 111 is provided on the bottom gate electrode and on the bottom dielectric layer 10 1 00 b. The f irst gate dielectric …
FIG. 13) a bilayer graphene 103 is formed on the first 15 gate dielectric layer 111 and a second gate dielectric layer 112 is formed on the bilayer graphene …
FIG. 14) the top gate electrode 133 is formed by depositing conducting top gate material and patterning the metal material. Furthermore gate contacts 233, 221 …
FIG. 15). Depending on the positioning of the different bottom gate electrodes and/or top gate electrodes different configurations for the BLG device are …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
The bilayer graphene tunnelling field effect transistor of
The bilayer graphene tunneling field effect transistor of Claim 2, wherein a p-i-n junction or n-i-p junction is electrostatically induced in the bilayer graphene.
The bila y er graphene tunnelling field effect transistor of Claim [[1]] 2, further comprising a first gate dielectric layer on a substrate, wherein the bila yer graphene comprises a first graphene layer and a second graphene layer, wherein the first graphene layer and the second graphene layer are adjoining, the bila y er graphene being sandwiched in between with the first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer contacting the first graphene layer and the second gate dielectric layer contacting the second graphene layer, and the top gate electrode contacting the second gate dielectric layer opposite to the second graphene layer.
The bila y er graphene tunnelling field effect transistor of Claim 3, wherein the first and second gate dielectric layers have a same equivalent oxide thickness.
The bila y er graphene tunneling field effect transistor of Claim 3, further comprising a second top gate electrode capacitively coupled to the top surface of the bila y er graphene and spaced apart along the top surface from the first top gate electrode, wherein the bottom gate electrode fully overlaps the first top gate electrode and the second top gate electrode, thereby defining a channel region capacitively coupled to the bottom gate electrode and the first top gate electrode, a source region capacitively coupled to the second top gate electrode and the bottom gate electrode, a ba rri er region only capacitively coupled to the bottom gate electrode, and a drain region only capacitively coupled to the bottom gate electrode, wherein the transistor comprises a first top gate electrode and a second top gate electrode and wherein -3- Application No.: 14/572364 Filing Date: both the first top gate electrode and the second top gate electrode contact the second gate dielectric layer opposite to the second graphene layer.
The bila y er graphene tunnelling field effect transistor of Claim [[1]] 2, wherein the bottom gate electrode is embedded in a substrate, wherein the substrate comprises a semiconductor layer with a bottom dielectric layer on top, wherein the bottom gate electrode is embedded in the bottom dielectric layer, wherein the bottom gate electrode has a top surface and the bottom dielectric layer has a top dielectric surface, and -2- Application No.: 14/572364 Filing Date: wherein the top surface of the bottom gate electrode is coplanar with the top dielectric surface of the bottom dielectric layer.
The bilayer graphene tunnelling field effect transistor of
The bilayer graphene tunnelling field effect transistor of Claim 5, further comprising a first gate dielectric layer on a substrate, wherein the bilayer graphene comprises a -4- Application No.: 14/572364 Filing Date: first graphene layer and a second graphene layer, wherein the first graphene layer and the second graphene layer are adjoining, the bilayer graphene being sandwiched in between with the first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer contacting the first graphene layer and the second gate dielectric layer contacting the second graphene layer, and the top gate electrode contacting the second gate dielectric layer opposite to the second graphene layer.
The bilayer graphene tunnelling field effect transistor of Claim 5, wherein the bottom gate electrode is embedded in a substrate, wherein the substrate comprises a semiconductor layer with a bottom dielectric layer on top, wherein the bottom gate electrode is embedded in the bottom dielectric layer, wherein the bottom gate electrode has a top surface and the bottom dielectric layer has a top dielectric surface, and wherein the top surface of the bottom gate electrode is coplanar with the top dielectric surface of the bottom dielectric layer.
The bilayer graphene tunnelling field effect transistor of Claim 5, further comprising a different contact for each of the at least a top and a bottom gate electrode configured to separately bias each of the at least a top and a bottom gate electrode.
The bilayer graphene tunnelling field effect transistor of Claim 5, wherein the bilayer graphene layer is chemically undoped.
The bila y er graphene tunnelling field effect transistor of Claim [[1]] SVG 14572364.12-07-2015.IHWNFCKEPXXIFW3.CLM.2.20.549.1911.585.1953.svg 0.14 0.12 Chemistry Black and white further comprising a different contact for each of the at least a top and a bottom gate electrode configured to separately bias each of the at least a top and a bottom gate electrode.
The bilayer graphene tunnelling field effect transistor of Claim [[1]] SVG 14572364.12-07-2015.IHWNFCKEPXXIFW3.CLM.3.6.540.672.576.714.svg 0.14 0.12 Chemistry Black and white wherein the bilayer graphene layer is chemically undoped.
The bilayer graphene tunnelling field effect transistor of
The bilayer graphene tunneling field effect transistor of Claim 10, wherein the p-i-n junction or an n-i-p junction is electrostatically induced by applying a voltage to a top gate electrode and a voltage of opposite sign to the bottom gate electrode.
The bilayer graphene tunnelling field effect transistor of Claim 10, further comprising a first gate dielectric layer on a substrate, wherein the bilayer graphene comprises a first graphene layer and a second graphene layer, wherein the first graphene layer and the second graphene layer are adjoining, the bilayer graphene being sandwiched in between with the first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer contacting the first graphene layer and the second gate dielectric layer contacting the second graphene layer, and the top gate electrode contacting the second gate dielectric layer opposite to the second graphene layer.
The bilayer graphene tunnelling field effect transistor of Claim 10, wherein the bottom gate electrode is embedded in a substrate, wherein the substrate comprises a semiconductor layer with a bottom dielectric layer on top, wherein the bottom gate electrode is embedded in the bottom dielectric layer, wherein the bottom gate electrode has a top surface and -5- Application No.: 14/572364 Filing Date: the bottom dielectric layer has a top dielectric surface, and wherein the top surface of the bottom dielectric surface of the bottom dielectric layer.
The bilayer graphene tunnelling field effect graphene layer is chemically undoped. -6-gate electrode is coplanar with the top transistor of Claim 10, further comprising a bottom gate electrode configured to separately electrode. transistor of Claim 10, wherein the bilayer
The bilayer graphene tunnelling field effect different contact for each of the at least a top and bias each of the at least a top and a bottom gate
Layer stacks claimed or described, ordered top of device to substrate.
bilayer graphene tunnelling field effect transistor (single top gate)
bilayer graphene tunnelling field effect transistor (dual top gate with barrier region)
Materials described outside the worked examples.
bilayer graphene
first gate dielectric layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Optical Band Gap | 0–300 meV | bilayer graphene |
Fet On Off Ratio | 100 |
Related documents with shared materials, methods, properties, or citations.
bilayer graphene |
Voltage | ≤ 0 V | — |
Voltage | ≥ 0 V | — |
bilayer graphene |
Voltage | ≤ 0 V | — |
Voltage | ≥ 0 V | — |
bilayer graphene |
Voltage | ≤ 0 V | — |
Voltage | ≥ 0 V | — |
bilayer graphene |
Voltage | ≤ 0 V | — |
Voltage | ≥ 0 V | — |