Patent
Atlas literature
Patent
US 12,652,038 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a circuit block diagram of a system-in-package, as has been described in the foregoing; 45
FIG. 2 is a circuit block diagram exemplary of a mono- lithic half-bridge power stage in GaN technology according to one or more embodiments of the present …
FIG. 3 is a circuit block diagram exemplary of a driver stage in GaN technology according to one or more embodi- 50 ments of the present description;
FIG. 4 is a circuit block diagram exemplary of a low-side pre-buffer stage in GaN technology according to one or more embodiments of the present description
FIG. 5 is a circuit block diagram exemplary of a high-side 55 pre-buffer stage in GaN technology according to one or more embodiments of the present …
FIG. 6 is a circuit block diagram exemplary of a com- parator circuit in GaN technology according to one or more embodiments of the present description. 60
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A driver circuit, comprising: an input supply pad configured to receive a supply volt-age, an input ground pad configured to receive a ground voltage, an input high-side control pad configured to receive a high-side control signal, an input low-side control pad configured to receive a low-side control signal, and an output pad configured to produce an output driving signal; a high-side output buffer circuit; a low-side output buffer circuit; a level shifter configured to shift and pass the high-side control signal to the high-side output buffer circuit; a low-side intermediate buffer circuit configured to pass the low-side control signal to the low-side output buffer circuit; a high-side GaN power transistor arranged between a high-voltage supply pad and the output pad and driven by the high-side output buffer circuit; a low-side GaN power transistor arranged between the output pad and a protected ground pad and driven by the low-side output buffer circuit; a first voltage regulator configured to produce a first regulated voltage as a function of the supply voltage; bootstrap circuitry configured to produce a bootstrap voltage as a function of the supply voltage; and a second voltage regulator configured to produce a second regulated voltage as a function of the bootstrap voltage, wherein the low-side output buffer circuit is supplied by the first regulated voltage and the high-side output buffer circuit is supplied by the second regulated volt-age.
The driver circuit of claim 1, wherein the level shifter, the high-side output buffer circuit, the low-side intermediate buffer circuit, the low-side output buffer circuit, the high-side GaN power transistor and the low-side GaN power transistor are implemented in a single GaN semiconductor substrate.
The driver circuit of claim 1, wherein: the level shifter, the low-side intermediate buffer circuit, the low-side output buffer circuit and the low-side GaN power transistor are implemented in a first GaN semiconductor substrate; and the high-side output buffer circuit and the high-side GaN power transistor are implemented in a second GaN semiconductor substrate.
A driver circuit, comprising: an input supply pad configured to receive a supply volt-age, an input ground pad configured to receive a ground voltage, an input high-side control pad configured to receive a high-side control signal, an input low-side control pad configured to receive a low-side control signal, and an output pad configured to produce an output driving signal; a high-side output buffer circuit; a low-side output buffer circuit; a level shifter configured to shift and pass the high-side control signal to the high-side output buffer circuit; 50 a low-side intermediate buffer circuit configured to pass the low-side control signal to the low-side output buffer circuit; a high-side GaN power transistor arranged between a high-voltage supply pad and the output pad and driven by the high-side output buffer circuit; a low-side GaN power transistor arranged between the output pad and a protected ground pad and driven by the low-side output buffer circuit, wherein the low-side intermediate buffer circuit includes an input stage, a B₂ differential-to-single-ended stage, and an output stage, wherein the input stage includes: an input differential pair of transistors, a first transistor of the pair being configured to receive an input signal at a control terminal thereof, and a second transistor of the pair being configured to receive a reference signal at a control terminal thereof; a first current generator load coupled between the first transistor and a supply node of the low-side intermediate buffer circuit; a second current generator load coupled between the second transistor and the supply node of the low-side intermediate buffer circuit; and a tail current generator coupled between a tail node of the input differential pair of transistors and a ground node of the low-side intermediate buffer circuit; and wherein the differential-to-single-ended stage includes a current mirror arrangement coupled to first and second output nodes of the input differential pair of transistors; and wherein the output stage includes a pair of cas-caded inverter circuits, the first inverter circuit being configured to receive a single-ended signal from an output node of the differential-to-single-ended stage, and the second inverter circuit being configured to receive a complemented signal from an output node of the first inverter circuit to produce an output signal of the low-side intermediate buffer circuit.
The driver circuit of claim 6, wherein the level shifter, the high-side output buffer circuit, the low-side intermediate buffer circuit, the low-side output buffer circuit, the high-side GaN power transistor and the low-side GaN power transistor are implemented in a single GaN semiconductor substrate.
The driver circuit of claim 6, wherein: the level shifter, the low-side intermediate buffer circuit, the low-side output buffer circuit and the low-side GaN power transistor are implemented in a first GaN semiconductor substrate; and the high-side output buffer circuit and the high-side GaN power transistor are implemented in a second GaN semiconductor substrate.
The driver circuit of claim 6, further comprising: a first voltage regulator configured to produce a first regulated voltage as a function of the supply voltage; bootstrap circuitry configured to produce a bootstrap voltage as a function of the supply voltage; and a second voltage regulator configured to produce a second regulated voltage as a function of the bootstrap voltage, wherein the low-side output buffer circuit is supplied by the first regulated voltage and the high-side output buffer circuit is supplied by the second regulated volt-age. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN half-bridge driver circuit
GaN output buffer circuit (push-pull stage)
Materials described outside the worked examples.
GaN semiconductor substrate
GaN
GaN-on-Si semiconductor substrate
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 3
Cited non-patent literature · 15
Related documents with shared materials, methods, properties, or citations.
SUBSTRATE HAVING THIN FILM OF GAN JOINED THEREON AND METHOD OF FABRICATING THE SAME, AND A GAN-BASED SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
METHOD FOR FABRICATING P-TYPE GALLIUM NITRIDE SEMICONDUCTOR AND METHOD OF HEAT TREATMENT
Patent
Atlas literature
Patent
US 12,652,038 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a circuit block diagram of a system-in-package, as has been described in the foregoing; 45
FIG. 2 is a circuit block diagram exemplary of a mono- lithic half-bridge power stage in GaN technology according to one or more embodiments of the present …
FIG. 3 is a circuit block diagram exemplary of a driver stage in GaN technology according to one or more embodi- 50 ments of the present description;
FIG. 4 is a circuit block diagram exemplary of a low-side pre-buffer stage in GaN technology according to one or more embodiments of the present description
FIG. 5 is a circuit block diagram exemplary of a high-side 55 pre-buffer stage in GaN technology according to one or more embodiments of the present …
FIG. 6 is a circuit block diagram exemplary of a com- parator circuit in GaN technology according to one or more embodiments of the present description. 60
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A driver circuit, comprising: an input supply pad configured to receive a supply volt-age, an input ground pad configured to receive a ground voltage, an input high-side control pad configured to receive a high-side control signal, an input low-side control pad configured to receive a low-side control signal, and an output pad configured to produce an output driving signal; a high-side output buffer circuit; a low-side output buffer circuit; a level shifter configured to shift and pass the high-side control signal to the high-side output buffer circuit; a low-side intermediate buffer circuit configured to pass the low-side control signal to the low-side output buffer circuit; a high-side GaN power transistor arranged between a high-voltage supply pad and the output pad and driven by the high-side output buffer circuit; a low-side GaN power transistor arranged between the output pad and a protected ground pad and driven by the low-side output buffer circuit; a first voltage regulator configured to produce a first regulated voltage as a function of the supply voltage; bootstrap circuitry configured to produce a bootstrap voltage as a function of the supply voltage; and a second voltage regulator configured to produce a second regulated voltage as a function of the bootstrap voltage, wherein the low-side output buffer circuit is supplied by the first regulated voltage and the high-side output buffer circuit is supplied by the second regulated volt-age.
The driver circuit of claim 1, wherein the level shifter, the high-side output buffer circuit, the low-side intermediate buffer circuit, the low-side output buffer circuit, the high-side GaN power transistor and the low-side GaN power transistor are implemented in a single GaN semiconductor substrate.
The driver circuit of claim 1, wherein: the level shifter, the low-side intermediate buffer circuit, the low-side output buffer circuit and the low-side GaN power transistor are implemented in a first GaN semiconductor substrate; and the high-side output buffer circuit and the high-side GaN power transistor are implemented in a second GaN semiconductor substrate.
A driver circuit, comprising: an input supply pad configured to receive a supply volt-age, an input ground pad configured to receive a ground voltage, an input high-side control pad configured to receive a high-side control signal, an input low-side control pad configured to receive a low-side control signal, and an output pad configured to produce an output driving signal; a high-side output buffer circuit; a low-side output buffer circuit; a level shifter configured to shift and pass the high-side control signal to the high-side output buffer circuit; 50 a low-side intermediate buffer circuit configured to pass the low-side control signal to the low-side output buffer circuit; a high-side GaN power transistor arranged between a high-voltage supply pad and the output pad and driven by the high-side output buffer circuit; a low-side GaN power transistor arranged between the output pad and a protected ground pad and driven by the low-side output buffer circuit, wherein the low-side intermediate buffer circuit includes an input stage, a B₂ differential-to-single-ended stage, and an output stage, wherein the input stage includes: an input differential pair of transistors, a first transistor of the pair being configured to receive an input signal at a control terminal thereof, and a second transistor of the pair being configured to receive a reference signal at a control terminal thereof; a first current generator load coupled between the first transistor and a supply node of the low-side intermediate buffer circuit; a second current generator load coupled between the second transistor and the supply node of the low-side intermediate buffer circuit; and a tail current generator coupled between a tail node of the input differential pair of transistors and a ground node of the low-side intermediate buffer circuit; and wherein the differential-to-single-ended stage includes a current mirror arrangement coupled to first and second output nodes of the input differential pair of transistors; and wherein the output stage includes a pair of cas-caded inverter circuits, the first inverter circuit being configured to receive a single-ended signal from an output node of the differential-to-single-ended stage, and the second inverter circuit being configured to receive a complemented signal from an output node of the first inverter circuit to produce an output signal of the low-side intermediate buffer circuit.
The driver circuit of claim 6, wherein the level shifter, the high-side output buffer circuit, the low-side intermediate buffer circuit, the low-side output buffer circuit, the high-side GaN power transistor and the low-side GaN power transistor are implemented in a single GaN semiconductor substrate.
The driver circuit of claim 6, wherein: the level shifter, the low-side intermediate buffer circuit, the low-side output buffer circuit and the low-side GaN power transistor are implemented in a first GaN semiconductor substrate; and the high-side output buffer circuit and the high-side GaN power transistor are implemented in a second GaN semiconductor substrate.
The driver circuit of claim 6, further comprising: a first voltage regulator configured to produce a first regulated voltage as a function of the supply voltage; bootstrap circuitry configured to produce a bootstrap voltage as a function of the supply voltage; and a second voltage regulator configured to produce a second regulated voltage as a function of the bootstrap voltage, wherein the low-side output buffer circuit is supplied by the first regulated voltage and the high-side output buffer circuit is supplied by the second regulated volt-age. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN half-bridge driver circuit
GaN output buffer circuit (push-pull stage)
Materials described outside the worked examples.
GaN semiconductor substrate
GaN
GaN-on-Si semiconductor substrate
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 3
Cited non-patent literature · 15
Related documents with shared materials, methods, properties, or citations.
SUBSTRATE HAVING THIN FILM OF GAN JOINED THEREON AND METHOD OF FABRICATING THE SAME, AND A GAN-BASED SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
METHOD FOR FABRICATING P-TYPE GALLIUM NITRIDE SEMICONDUCTOR AND METHOD OF HEAT TREATMENT
Patent
Atlas literature
Patent
US 12,652,038 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a circuit block diagram of a system-in-package, as has been described in the foregoing; 45
FIG. 2 is a circuit block diagram exemplary of a mono- lithic half-bridge power stage in GaN technology according to one or more embodiments of the present …
FIG. 3 is a circuit block diagram exemplary of a driver stage in GaN technology according to one or more embodi- 50 ments of the present description;
FIG. 4 is a circuit block diagram exemplary of a low-side pre-buffer stage in GaN technology according to one or more embodiments of the present description
FIG. 5 is a circuit block diagram exemplary of a high-side 55 pre-buffer stage in GaN technology according to one or more embodiments of the present …
FIG. 6 is a circuit block diagram exemplary of a com- parator circuit in GaN technology according to one or more embodiments of the present description. 60
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A driver circuit, comprising: an input supply pad configured to receive a supply volt-age, an input ground pad configured to receive a ground voltage, an input high-side control pad configured to receive a high-side control signal, an input low-side control pad configured to receive a low-side control signal, and an output pad configured to produce an output driving signal; a high-side output buffer circuit; a low-side output buffer circuit; a level shifter configured to shift and pass the high-side control signal to the high-side output buffer circuit; a low-side intermediate buffer circuit configured to pass the low-side control signal to the low-side output buffer circuit; a high-side GaN power transistor arranged between a high-voltage supply pad and the output pad and driven by the high-side output buffer circuit; a low-side GaN power transistor arranged between the output pad and a protected ground pad and driven by the low-side output buffer circuit; a first voltage regulator configured to produce a first regulated voltage as a function of the supply voltage; bootstrap circuitry configured to produce a bootstrap voltage as a function of the supply voltage; and a second voltage regulator configured to produce a second regulated voltage as a function of the bootstrap voltage, wherein the low-side output buffer circuit is supplied by the first regulated voltage and the high-side output buffer circuit is supplied by the second regulated volt-age.
The driver circuit of claim 1, wherein the level shifter, the high-side output buffer circuit, the low-side intermediate buffer circuit, the low-side output buffer circuit, the high-side GaN power transistor and the low-side GaN power transistor are implemented in a single GaN semiconductor substrate.
The driver circuit of claim 1, wherein: the level shifter, the low-side intermediate buffer circuit, the low-side output buffer circuit and the low-side GaN power transistor are implemented in a first GaN semiconductor substrate; and the high-side output buffer circuit and the high-side GaN power transistor are implemented in a second GaN semiconductor substrate.
A driver circuit, comprising: an input supply pad configured to receive a supply volt-age, an input ground pad configured to receive a ground voltage, an input high-side control pad configured to receive a high-side control signal, an input low-side control pad configured to receive a low-side control signal, and an output pad configured to produce an output driving signal; a high-side output buffer circuit; a low-side output buffer circuit; a level shifter configured to shift and pass the high-side control signal to the high-side output buffer circuit; 50 a low-side intermediate buffer circuit configured to pass the low-side control signal to the low-side output buffer circuit; a high-side GaN power transistor arranged between a high-voltage supply pad and the output pad and driven by the high-side output buffer circuit; a low-side GaN power transistor arranged between the output pad and a protected ground pad and driven by the low-side output buffer circuit, wherein the low-side intermediate buffer circuit includes an input stage, a B₂ differential-to-single-ended stage, and an output stage, wherein the input stage includes: an input differential pair of transistors, a first transistor of the pair being configured to receive an input signal at a control terminal thereof, and a second transistor of the pair being configured to receive a reference signal at a control terminal thereof; a first current generator load coupled between the first transistor and a supply node of the low-side intermediate buffer circuit; a second current generator load coupled between the second transistor and the supply node of the low-side intermediate buffer circuit; and a tail current generator coupled between a tail node of the input differential pair of transistors and a ground node of the low-side intermediate buffer circuit; and wherein the differential-to-single-ended stage includes a current mirror arrangement coupled to first and second output nodes of the input differential pair of transistors; and wherein the output stage includes a pair of cas-caded inverter circuits, the first inverter circuit being configured to receive a single-ended signal from an output node of the differential-to-single-ended stage, and the second inverter circuit being configured to receive a complemented signal from an output node of the first inverter circuit to produce an output signal of the low-side intermediate buffer circuit.
The driver circuit of claim 6, wherein the level shifter, the high-side output buffer circuit, the low-side intermediate buffer circuit, the low-side output buffer circuit, the high-side GaN power transistor and the low-side GaN power transistor are implemented in a single GaN semiconductor substrate.
The driver circuit of claim 6, wherein: the level shifter, the low-side intermediate buffer circuit, the low-side output buffer circuit and the low-side GaN power transistor are implemented in a first GaN semiconductor substrate; and the high-side output buffer circuit and the high-side GaN power transistor are implemented in a second GaN semiconductor substrate.
The driver circuit of claim 6, further comprising: a first voltage regulator configured to produce a first regulated voltage as a function of the supply voltage; bootstrap circuitry configured to produce a bootstrap voltage as a function of the supply voltage; and a second voltage regulator configured to produce a second regulated voltage as a function of the bootstrap voltage, wherein the low-side output buffer circuit is supplied by the first regulated voltage and the high-side output buffer circuit is supplied by the second regulated volt-age. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN half-bridge driver circuit
GaN output buffer circuit (push-pull stage)
Materials described outside the worked examples.
GaN semiconductor substrate
GaN
GaN-on-Si semiconductor substrate
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 3
Cited non-patent literature · 15
Related documents with shared materials, methods, properties, or citations.
SUBSTRATE HAVING THIN FILM OF GAN JOINED THEREON AND METHOD OF FABRICATING THE SAME, AND A GAN-BASED SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
METHOD FOR FABRICATING P-TYPE GALLIUM NITRIDE SEMICONDUCTOR AND METHOD OF HEAT TREATMENT
Patent
Atlas literature
Patent
US 12,652,038 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a circuit block diagram of a system-in-package, as has been described in the foregoing; 45
FIG. 2 is a circuit block diagram exemplary of a mono- lithic half-bridge power stage in GaN technology according to one or more embodiments of the present …
FIG. 3 is a circuit block diagram exemplary of a driver stage in GaN technology according to one or more embodi- 50 ments of the present description;
FIG. 4 is a circuit block diagram exemplary of a low-side pre-buffer stage in GaN technology according to one or more embodiments of the present description
FIG. 5 is a circuit block diagram exemplary of a high-side 55 pre-buffer stage in GaN technology according to one or more embodiments of the present …
FIG. 6 is a circuit block diagram exemplary of a com- parator circuit in GaN technology according to one or more embodiments of the present description. 60
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A driver circuit, comprising: an input supply pad configured to receive a supply volt-age, an input ground pad configured to receive a ground voltage, an input high-side control pad configured to receive a high-side control signal, an input low-side control pad configured to receive a low-side control signal, and an output pad configured to produce an output driving signal; a high-side output buffer circuit; a low-side output buffer circuit; a level shifter configured to shift and pass the high-side control signal to the high-side output buffer circuit; a low-side intermediate buffer circuit configured to pass the low-side control signal to the low-side output buffer circuit; a high-side GaN power transistor arranged between a high-voltage supply pad and the output pad and driven by the high-side output buffer circuit; a low-side GaN power transistor arranged between the output pad and a protected ground pad and driven by the low-side output buffer circuit; a first voltage regulator configured to produce a first regulated voltage as a function of the supply voltage; bootstrap circuitry configured to produce a bootstrap voltage as a function of the supply voltage; and a second voltage regulator configured to produce a second regulated voltage as a function of the bootstrap voltage, wherein the low-side output buffer circuit is supplied by the first regulated voltage and the high-side output buffer circuit is supplied by the second regulated volt-age.
The driver circuit of claim 1, wherein the level shifter, the high-side output buffer circuit, the low-side intermediate buffer circuit, the low-side output buffer circuit, the high-side GaN power transistor and the low-side GaN power transistor are implemented in a single GaN semiconductor substrate.
The driver circuit of claim 1, wherein: the level shifter, the low-side intermediate buffer circuit, the low-side output buffer circuit and the low-side GaN power transistor are implemented in a first GaN semiconductor substrate; and the high-side output buffer circuit and the high-side GaN power transistor are implemented in a second GaN semiconductor substrate.
A driver circuit, comprising: an input supply pad configured to receive a supply volt-age, an input ground pad configured to receive a ground voltage, an input high-side control pad configured to receive a high-side control signal, an input low-side control pad configured to receive a low-side control signal, and an output pad configured to produce an output driving signal; a high-side output buffer circuit; a low-side output buffer circuit; a level shifter configured to shift and pass the high-side control signal to the high-side output buffer circuit; 50 a low-side intermediate buffer circuit configured to pass the low-side control signal to the low-side output buffer circuit; a high-side GaN power transistor arranged between a high-voltage supply pad and the output pad and driven by the high-side output buffer circuit; a low-side GaN power transistor arranged between the output pad and a protected ground pad and driven by the low-side output buffer circuit, wherein the low-side intermediate buffer circuit includes an input stage, a B₂ differential-to-single-ended stage, and an output stage, wherein the input stage includes: an input differential pair of transistors, a first transistor of the pair being configured to receive an input signal at a control terminal thereof, and a second transistor of the pair being configured to receive a reference signal at a control terminal thereof; a first current generator load coupled between the first transistor and a supply node of the low-side intermediate buffer circuit; a second current generator load coupled between the second transistor and the supply node of the low-side intermediate buffer circuit; and a tail current generator coupled between a tail node of the input differential pair of transistors and a ground node of the low-side intermediate buffer circuit; and wherein the differential-to-single-ended stage includes a current mirror arrangement coupled to first and second output nodes of the input differential pair of transistors; and wherein the output stage includes a pair of cas-caded inverter circuits, the first inverter circuit being configured to receive a single-ended signal from an output node of the differential-to-single-ended stage, and the second inverter circuit being configured to receive a complemented signal from an output node of the first inverter circuit to produce an output signal of the low-side intermediate buffer circuit.
The driver circuit of claim 6, wherein the level shifter, the high-side output buffer circuit, the low-side intermediate buffer circuit, the low-side output buffer circuit, the high-side GaN power transistor and the low-side GaN power transistor are implemented in a single GaN semiconductor substrate.
The driver circuit of claim 6, wherein: the level shifter, the low-side intermediate buffer circuit, the low-side output buffer circuit and the low-side GaN power transistor are implemented in a first GaN semiconductor substrate; and the high-side output buffer circuit and the high-side GaN power transistor are implemented in a second GaN semiconductor substrate.
The driver circuit of claim 6, further comprising: a first voltage regulator configured to produce a first regulated voltage as a function of the supply voltage; bootstrap circuitry configured to produce a bootstrap voltage as a function of the supply voltage; and a second voltage regulator configured to produce a second regulated voltage as a function of the bootstrap voltage, wherein the low-side output buffer circuit is supplied by the first regulated voltage and the high-side output buffer circuit is supplied by the second regulated volt-age. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN half-bridge driver circuit
GaN output buffer circuit (push-pull stage)
Materials described outside the worked examples.
GaN semiconductor substrate
GaN
GaN-on-Si semiconductor substrate
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 3
Cited non-patent literature · 15
Related documents with shared materials, methods, properties, or citations.
SUBSTRATE HAVING THIN FILM OF GAN JOINED THEREON AND METHOD OF FABRICATING THE SAME, AND A GAN-BASED SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
METHOD FOR FABRICATING P-TYPE GALLIUM NITRIDE SEMICONDUCTOR AND METHOD OF HEAT TREATMENT
