Patent
US 11,476,338d "ALUMINUM INDIUM PHOSPHIDE SUBFIN GERMANIUM CHANNEL
Matthew V. Metz
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
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US 11,476,338Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A is a side view of an example integrated circuit including example transistors;
FIG. 2 is an example band diagram of an example hetero-junction between germanium and aluminum indium phosphide;
FIG. 3 is a flow diagram illustrating an example process for forming transistors having enhanced channel mobility and reduced leakage;
FIGS. 4A, 4B, 4C, 4 D, 4E, 4F, and 4G are side views of example transistor structures as particular fabrication operations are performed;
FIG. 5 is a view of an example SRAM cell implementing one or more transistors having enhanced channel mobility and reduced leakage;
FIG. 6 is an illustrative diagram of a mobile computing platform employing an integrated circuit with transistor(s) having germanium fin channels and aluminum …
FIG. 7 is a functional block diagram of a computing device, all arranged in accordance with at least some implementations of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit comprising a transistor comprising: a fin channel comprising germanium; and a subfin having a first layer adjacent to the fin channel and a second layer adjacent to the first layer, wherein the first layer comprises aluminum, indium, and phosphorus. Original
The integrated circuit of claim 1, further comprising a second transistor comprising: a second fin channel; and a second subfin having a third layer adjacent to the second fin channel and a fourth layer adjacent to the third layer, wherein the transistor is a PMOS transistor and the second transistor is an NMOS transistor. Previously presented
The integrated circuit of claim 1, wherein the second layer comprises gallium and arsenic. Original
The integrated circuit of claim 1 further comprising: a dielectric layer adjacent to the second layer and a first portion of the first layer, wherein a second portion of the first layer extends beyond a top surface of the dielectric layer; and a substrate, wherein the first layer and the dielectric layer are on the substrate. Original
The integrated circuit of claim 1, wherein the transistor is a PMOS transistor and the first layer comprises aluminum, indium, and phosphorus having an aluminum concentration in the range of 99% to 50%. Original
The integrated circuit of claim 1, wherein the transistor is an NMOS transistor and the first layer comprises aluminum, indium, and phosphorus having an aluminum concentration in the range of 35% to 50%. Original
A transistor structure comprising: a fin channel comprising germanium; and a subfin having a layer adjacent to the fin channel, the layer comprising aluminum, indium, and phosphorus. Original
The transistor structure of claim 10, wherein the transistor is a PMOS transistor and the layer comprises an aluminum concentration in the range of 99% to 50%. Original
The transistor structure of claim 10, wherein the transistor is an NMOS transistor and the layer comprises an aluminum concentration in the range of 35% to 50%. Original
The transistor structure of claim 10, further comprising: a dielectric layer adjacent to a first portion of the layer, wherein a second portion of the layer extends beyond a top surface of the dielectric layer. Original
The transistor structure of claim 10, wherein the subfin further comprises a second layer adjacent the layer. Original
An SRAM cell comprising: an NMOS transistor including: a first fin channel comprising germanium; and a first subfin having a first layer adjacent to the fin channel, wherein the first layer comprises aluminum, indium, and phosphorus; and a PMOS transistor including: a second fin channel; and a second subfin having a second layer adjacent to the fin channel. Previously presented
The SRAM cell of claim 16, wherein the second fin channel comprises germanium, the first layer comprises a first aluminum to indium ratio, and the second layer comprises aluminum, indium, and phosphorus having a second aluminum to indium ratio greater than the first aluminum to indium ratio. Original
The SRAM cell of claim 16, wherein the second fin channel comprises at least one of germanium, silicon, or a III -V material. Original
The SRAM cell of claim 16, wherein the second layer comprises gallium and arsenic. Original
The SRAM cell of claim 16, further comprising: an insulator layer adjacent to the second layer and a first portion of the first layer, wherein a second portion of the first layer extends beyond the insulator layer; and a substrate, wherein the first layer and the insulator are on the substrate. Original
Layer stacks claimed or described, ordered top of device to substrate.
integrated circuit with PMOS FinFET having germanium fin channel and AlInP subfin
NMOS FinFET (second transistor in CMOS pair)
No layer stack recorded.
transistor structure with germanium fin channel and AlInP subfin layer
Materials described outside the worked examples.
germanium
Ge
aluminum indium phosphide
AlInP
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 A is a side view of an example integrated circuit including example transistors;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 8–20 nm | — |
Thickness | 200–350 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,476,338Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A is a side view of an example integrated circuit including example transistors;
FIG. 2 is an example band diagram of an example hetero-junction between germanium and aluminum indium phosphide;
FIG. 3 is a flow diagram illustrating an example process for forming transistors having enhanced channel mobility and reduced leakage;
FIGS. 4A, 4B, 4C, 4 D, 4E, 4F, and 4G are side views of example transistor structures as particular fabrication operations are performed;
FIG. 5 is a view of an example SRAM cell implementing one or more transistors having enhanced channel mobility and reduced leakage;
FIG. 6 is an illustrative diagram of a mobile computing platform employing an integrated circuit with transistor(s) having germanium fin channels and aluminum …
FIG. 7 is a functional block diagram of a computing device, all arranged in accordance with at least some implementations of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit comprising a transistor comprising: a fin channel comprising germanium; and a subfin having a first layer adjacent to the fin channel and a second layer adjacent to the first layer, wherein the first layer comprises aluminum, indium, and phosphorus. Original
The integrated circuit of claim 1, further comprising a second transistor comprising: a second fin channel; and a second subfin having a third layer adjacent to the second fin channel and a fourth layer adjacent to the third layer, wherein the transistor is a PMOS transistor and the second transistor is an NMOS transistor. Previously presented
The integrated circuit of claim 1, wherein the second layer comprises gallium and arsenic. Original
The integrated circuit of claim 1 further comprising: a dielectric layer adjacent to the second layer and a first portion of the first layer, wherein a second portion of the first layer extends beyond a top surface of the dielectric layer; and a substrate, wherein the first layer and the dielectric layer are on the substrate. Original
The integrated circuit of claim 1, wherein the transistor is a PMOS transistor and the first layer comprises aluminum, indium, and phosphorus having an aluminum concentration in the range of 99% to 50%. Original
The integrated circuit of claim 1, wherein the transistor is an NMOS transistor and the first layer comprises aluminum, indium, and phosphorus having an aluminum concentration in the range of 35% to 50%. Original
A transistor structure comprising: a fin channel comprising germanium; and a subfin having a layer adjacent to the fin channel, the layer comprising aluminum, indium, and phosphorus. Original
The transistor structure of claim 10, wherein the transistor is a PMOS transistor and the layer comprises an aluminum concentration in the range of 99% to 50%. Original
The transistor structure of claim 10, wherein the transistor is an NMOS transistor and the layer comprises an aluminum concentration in the range of 35% to 50%. Original
The transistor structure of claim 10, further comprising: a dielectric layer adjacent to a first portion of the layer, wherein a second portion of the layer extends beyond a top surface of the dielectric layer. Original
The transistor structure of claim 10, wherein the subfin further comprises a second layer adjacent the layer. Original
An SRAM cell comprising: an NMOS transistor including: a first fin channel comprising germanium; and a first subfin having a first layer adjacent to the fin channel, wherein the first layer comprises aluminum, indium, and phosphorus; and a PMOS transistor including: a second fin channel; and a second subfin having a second layer adjacent to the fin channel. Previously presented
The SRAM cell of claim 16, wherein the second fin channel comprises germanium, the first layer comprises a first aluminum to indium ratio, and the second layer comprises aluminum, indium, and phosphorus having a second aluminum to indium ratio greater than the first aluminum to indium ratio. Original
The SRAM cell of claim 16, wherein the second fin channel comprises at least one of germanium, silicon, or a III -V material. Original
The SRAM cell of claim 16, wherein the second layer comprises gallium and arsenic. Original
The SRAM cell of claim 16, further comprising: an insulator layer adjacent to the second layer and a first portion of the first layer, wherein a second portion of the first layer extends beyond the insulator layer; and a substrate, wherein the first layer and the insulator are on the substrate. Original
Layer stacks claimed or described, ordered top of device to substrate.
integrated circuit with PMOS FinFET having germanium fin channel and AlInP subfin
NMOS FinFET (second transistor in CMOS pair)
No layer stack recorded.
transistor structure with germanium fin channel and AlInP subfin layer
Materials described outside the worked examples.
germanium
Ge
aluminum indium phosphide
AlInP
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 A is a side view of an example integrated circuit including example transistors;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 8–20 nm | — |
Thickness | 200–350 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,476,338Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A is a side view of an example integrated circuit including example transistors;
FIG. 2 is an example band diagram of an example hetero-junction between germanium and aluminum indium phosphide;
FIG. 3 is a flow diagram illustrating an example process for forming transistors having enhanced channel mobility and reduced leakage;
FIGS. 4A, 4B, 4C, 4 D, 4E, 4F, and 4G are side views of example transistor structures as particular fabrication operations are performed;
FIG. 5 is a view of an example SRAM cell implementing one or more transistors having enhanced channel mobility and reduced leakage;
FIG. 6 is an illustrative diagram of a mobile computing platform employing an integrated circuit with transistor(s) having germanium fin channels and aluminum …
FIG. 7 is a functional block diagram of a computing device, all arranged in accordance with at least some implementations of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit comprising a transistor comprising: a fin channel comprising germanium; and a subfin having a first layer adjacent to the fin channel and a second layer adjacent to the first layer, wherein the first layer comprises aluminum, indium, and phosphorus. Original
The integrated circuit of claim 1, further comprising a second transistor comprising: a second fin channel; and a second subfin having a third layer adjacent to the second fin channel and a fourth layer adjacent to the third layer, wherein the transistor is a PMOS transistor and the second transistor is an NMOS transistor. Previously presented
The integrated circuit of claim 1, wherein the second layer comprises gallium and arsenic. Original
The integrated circuit of claim 1 further comprising: a dielectric layer adjacent to the second layer and a first portion of the first layer, wherein a second portion of the first layer extends beyond a top surface of the dielectric layer; and a substrate, wherein the first layer and the dielectric layer are on the substrate. Original
The integrated circuit of claim 1, wherein the transistor is a PMOS transistor and the first layer comprises aluminum, indium, and phosphorus having an aluminum concentration in the range of 99% to 50%. Original
The integrated circuit of claim 1, wherein the transistor is an NMOS transistor and the first layer comprises aluminum, indium, and phosphorus having an aluminum concentration in the range of 35% to 50%. Original
A transistor structure comprising: a fin channel comprising germanium; and a subfin having a layer adjacent to the fin channel, the layer comprising aluminum, indium, and phosphorus. Original
The transistor structure of claim 10, wherein the transistor is a PMOS transistor and the layer comprises an aluminum concentration in the range of 99% to 50%. Original
The transistor structure of claim 10, wherein the transistor is an NMOS transistor and the layer comprises an aluminum concentration in the range of 35% to 50%. Original
The transistor structure of claim 10, further comprising: a dielectric layer adjacent to a first portion of the layer, wherein a second portion of the layer extends beyond a top surface of the dielectric layer. Original
The transistor structure of claim 10, wherein the subfin further comprises a second layer adjacent the layer. Original
An SRAM cell comprising: an NMOS transistor including: a first fin channel comprising germanium; and a first subfin having a first layer adjacent to the fin channel, wherein the first layer comprises aluminum, indium, and phosphorus; and a PMOS transistor including: a second fin channel; and a second subfin having a second layer adjacent to the fin channel. Previously presented
The SRAM cell of claim 16, wherein the second fin channel comprises germanium, the first layer comprises a first aluminum to indium ratio, and the second layer comprises aluminum, indium, and phosphorus having a second aluminum to indium ratio greater than the first aluminum to indium ratio. Original
The SRAM cell of claim 16, wherein the second fin channel comprises at least one of germanium, silicon, or a III -V material. Original
The SRAM cell of claim 16, wherein the second layer comprises gallium and arsenic. Original
The SRAM cell of claim 16, further comprising: an insulator layer adjacent to the second layer and a first portion of the first layer, wherein a second portion of the first layer extends beyond the insulator layer; and a substrate, wherein the first layer and the insulator are on the substrate. Original
Layer stacks claimed or described, ordered top of device to substrate.
integrated circuit with PMOS FinFET having germanium fin channel and AlInP subfin
NMOS FinFET (second transistor in CMOS pair)
No layer stack recorded.
transistor structure with germanium fin channel and AlInP subfin layer
Materials described outside the worked examples.
germanium
Ge
aluminum indium phosphide
AlInP
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 A is a side view of an example integrated circuit including example transistors;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 8–20 nm | — |
Thickness | 200–350 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,476,338Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A is a side view of an example integrated circuit including example transistors;
FIG. 2 is an example band diagram of an example hetero-junction between germanium and aluminum indium phosphide;
FIG. 3 is a flow diagram illustrating an example process for forming transistors having enhanced channel mobility and reduced leakage;
FIGS. 4A, 4B, 4C, 4 D, 4E, 4F, and 4G are side views of example transistor structures as particular fabrication operations are performed;
FIG. 5 is a view of an example SRAM cell implementing one or more transistors having enhanced channel mobility and reduced leakage;
FIG. 6 is an illustrative diagram of a mobile computing platform employing an integrated circuit with transistor(s) having germanium fin channels and aluminum …
FIG. 7 is a functional block diagram of a computing device, all arranged in accordance with at least some implementations of the present disclosure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An integrated circuit comprising a transistor comprising: a fin channel comprising germanium; and a subfin having a first layer adjacent to the fin channel and a second layer adjacent to the first layer, wherein the first layer comprises aluminum, indium, and phosphorus. Original
The integrated circuit of claim 1, further comprising a second transistor comprising: a second fin channel; and a second subfin having a third layer adjacent to the second fin channel and a fourth layer adjacent to the third layer, wherein the transistor is a PMOS transistor and the second transistor is an NMOS transistor. Previously presented
The integrated circuit of claim 1, wherein the second layer comprises gallium and arsenic. Original
The integrated circuit of claim 1 further comprising: a dielectric layer adjacent to the second layer and a first portion of the first layer, wherein a second portion of the first layer extends beyond a top surface of the dielectric layer; and a substrate, wherein the first layer and the dielectric layer are on the substrate. Original
The integrated circuit of claim 1, wherein the transistor is a PMOS transistor and the first layer comprises aluminum, indium, and phosphorus having an aluminum concentration in the range of 99% to 50%. Original
The integrated circuit of claim 1, wherein the transistor is an NMOS transistor and the first layer comprises aluminum, indium, and phosphorus having an aluminum concentration in the range of 35% to 50%. Original
A transistor structure comprising: a fin channel comprising germanium; and a subfin having a layer adjacent to the fin channel, the layer comprising aluminum, indium, and phosphorus. Original
The transistor structure of claim 10, wherein the transistor is a PMOS transistor and the layer comprises an aluminum concentration in the range of 99% to 50%. Original
The transistor structure of claim 10, wherein the transistor is an NMOS transistor and the layer comprises an aluminum concentration in the range of 35% to 50%. Original
The transistor structure of claim 10, further comprising: a dielectric layer adjacent to a first portion of the layer, wherein a second portion of the layer extends beyond a top surface of the dielectric layer. Original
The transistor structure of claim 10, wherein the subfin further comprises a second layer adjacent the layer. Original
An SRAM cell comprising: an NMOS transistor including: a first fin channel comprising germanium; and a first subfin having a first layer adjacent to the fin channel, wherein the first layer comprises aluminum, indium, and phosphorus; and a PMOS transistor including: a second fin channel; and a second subfin having a second layer adjacent to the fin channel. Previously presented
The SRAM cell of claim 16, wherein the second fin channel comprises germanium, the first layer comprises a first aluminum to indium ratio, and the second layer comprises aluminum, indium, and phosphorus having a second aluminum to indium ratio greater than the first aluminum to indium ratio. Original
The SRAM cell of claim 16, wherein the second fin channel comprises at least one of germanium, silicon, or a III -V material. Original
The SRAM cell of claim 16, wherein the second layer comprises gallium and arsenic. Original
The SRAM cell of claim 16, further comprising: an insulator layer adjacent to the second layer and a first portion of the first layer, wherein a second portion of the first layer extends beyond the insulator layer; and a substrate, wherein the first layer and the insulator are on the substrate. Original
Layer stacks claimed or described, ordered top of device to substrate.
integrated circuit with PMOS FinFET having germanium fin channel and AlInP subfin
NMOS FinFET (second transistor in CMOS pair)
No layer stack recorded.
transistor structure with germanium fin channel and AlInP subfin layer
Materials described outside the worked examples.
germanium
Ge
aluminum indium phosphide
AlInP
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 A is a side view of an example integrated circuit including example transistors;
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 8–20 nm | — |
Thickness | 200–350 nm |
Related documents with shared materials, methods, properties, or citations.
SRAM cell with NMOS (Ge channel, AlInP subfin) and PMOS transistors
silicon
Si
indium gallium arsenide
InGaAs
gallium arsenide
GaAs
dielectric layer
III-V material
silicon oxide
SiO₂
FIG. 3 is a flow diagram illustrating an example process for forming transistors having enhanced channel mobility and reduced leakage;
FIGS. 4A, 4B, 4C, 4 D, 4E, 4F, and 4G are side views of example transistor structures as particular fabrication operations are performed;
FIG. 5 is a view of an example SRAM cell implementing one or more transistors having enhanced channel mobility and reduced leakage;
FIG. 6 is an illustrative diagram of a mobile computing platform employing an integrated circuit with transistor(s) having germanium fin channels and aluminum …
| — |
Thickness | 50–120 nm | — |
SRAM cell with NMOS (Ge channel, AlInP subfin) and PMOS transistors
silicon
Si
indium gallium arsenide
InGaAs
gallium arsenide
GaAs
dielectric layer
III-V material
silicon oxide
SiO₂
FIG. 3 is a flow diagram illustrating an example process for forming transistors having enhanced channel mobility and reduced leakage;
FIGS. 4A, 4B, 4C, 4 D, 4E, 4F, and 4G are side views of example transistor structures as particular fabrication operations are performed;
FIG. 5 is a view of an example SRAM cell implementing one or more transistors having enhanced channel mobility and reduced leakage;
FIG. 6 is an illustrative diagram of a mobile computing platform employing an integrated circuit with transistor(s) having germanium fin channels and aluminum …
| — |
Thickness | 50–120 nm | — |
SRAM cell with NMOS (Ge channel, AlInP subfin) and PMOS transistors
silicon
Si
indium gallium arsenide
InGaAs
gallium arsenide
GaAs
dielectric layer
III-V material
silicon oxide
SiO₂
FIG. 3 is a flow diagram illustrating an example process for forming transistors having enhanced channel mobility and reduced leakage;
FIGS. 4A, 4B, 4C, 4 D, 4E, 4F, and 4G are side views of example transistor structures as particular fabrication operations are performed;
FIG. 5 is a view of an example SRAM cell implementing one or more transistors having enhanced channel mobility and reduced leakage;
FIG. 6 is an illustrative diagram of a mobile computing platform employing an integrated circuit with transistor(s) having germanium fin channels and aluminum …
| — |
Thickness | 50–120 nm | — |
SRAM cell with NMOS (Ge channel, AlInP subfin) and PMOS transistors
silicon
Si
indium gallium arsenide
InGaAs
gallium arsenide
GaAs
dielectric layer
III-V material
silicon oxide
SiO₂
FIG. 3 is a flow diagram illustrating an example process for forming transistors having enhanced channel mobility and reduced leakage;
FIGS. 4A, 4B, 4C, 4 D, 4E, 4F, and 4G are side views of example transistor structures as particular fabrication operations are performed;
FIG. 5 is a view of an example SRAM cell implementing one or more transistors having enhanced channel mobility and reduced leakage;
FIG. 6 is an illustrative diagram of a mobile computing platform employing an integrated circuit with transistor(s) having germanium fin channels and aluminum …
| — |
Thickness | 50–120 nm | — |