Patent
US 10,541,315INP-BASED TRANSISTOR FABRICATION
Peide Ye
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,541,315Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A, a semiconductor substrate 100 has an InP-b ased t op layer 110 dis po sed t h ere o ver. In v ari o us e m bodi m ents, a portion of th is InP layer …
FIG. 2B. Prio r t o the form ati on o f the high-k g ate dielect r ic 210, surface cleani ng and preparation of the substrate i 00 incl u des I-F-or HCl -based …
FIGS. 3A and 3B show how ART techniques may be used to grow a high- quality InP layer above a buffer layer on a lattice-mismatched underlying material, such as …
FIG. 4C. In an embodiment, InP may be grown epitaxially within the source and drain recesses 400, 400' by CVD with doping performed in situ. With a p-type …
FIGS. 5A-5 G illustrate a method of creating a MOSFET with source and drain regions that are self-aligned to the gate, i.e., the edges of the source and drain …
FIGS. 6A and 6B, to mitigate interfacial instability difficulties between InP and dielectric materials as well as to prevent incongruent sublimation of the I II …
FIG. 7B the gate 710 is defined and the source and drain regions 720, 730 of a transistor are implanted using techniques similar to those discussed above for …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method comprising: forming a mask layer over a substrate, the substrate comprising a first crystalline semiconductor material having a first lattice constant, the mask layer comprising a non- crystalline dielectric material; patterning the mask layer to form an opening in the mask layer, the opening exposing a portion of the substrate; forming a buffer layer in the opening, the buffer layer comprising a second crystalline semiconductor material having a second lattice constant, the second lattice constant being different from the first lattice constant, a topmost surface of the buffer layer being below a topmost surface of the mask layer, dislocation defects within the buffer layer extending laterally and terminating at a sidewall of the opening; forming a semiconductor layer over the buffer layer in the opening, the semiconductor layer fully filling the opening, the semiconductor layer being made of a single third crystalline semiconductor material having a third lattice constant, the third lattice constant being substantially same as the second lattice constant; and forming a gate stack over the semiconductor layer, wherein the topmost surface of the mask layer is level with a topmost surface of the semiconductor layer after forming the gate stack. Previously presented
The method of claim 1, wherein the mask layer has a thickness between about 20 nm and about 5000 0 nm. Original
The method of claim 1, wherein a height of the opening is greater than or equal to a first height, and wherein the first height is between one half of a width of the opening and two times the width of the opening. Previously presented
The method of claim 1, wherein a ratio of a height of the opening to a width of the opening is between about 1 and about 50. Original
The method of claim 1, wherein forming the buffer layer in the opening comprises selectively epitaxially growing the buffer layer in the opening. Original
The method of claim 1, wherein a density of the dislocation defects within the buffer layer decreases with increasing a distance from a bottom of the opening. Original
The method of claim 1, wherein the semiconductor layer is made of InP. Previously presented
The method of claim 1 5, further comprising: etching the semiconductor layer to form a recess in the semiconductor layer; and epitaxially growing a fourth crystalline semiconductor material in the recess. Original
1 8. The method of claim 1 5, wherein a ratio of the first height to the first width is between about 1 and about 50. Original
The method of claim 1 5, wherein the first width is between about 20 nm and about 1000 nm. Original
The method of claim 1 5, wherein the semiconductor layer is made of InP. Previously presented
-14. Canceled
Canceled
A method comprising: forming a non-crystalline dielectric layer over a substrate, the substrate comprising a first crystalline semiconductor material having a first lattice constant; etching the non-crystalline dielectric layer to form an opening in the non-crystalline dielectric layer, the opening exposing a portion of the substrate, the opening having a first width and a first height; epitaxially growing a buffer layer in the opening, the buffer layer comprising a second crystalline semiconductor material having a second lattice constant, the second lattice constant being different from the first lattice constant, the buffer layer having a second height less than the first height, dislocation defects within the buffer layer extending laterally and terminating at a sidewall of the opening below a third height, the third height being less than the second height, the third height being between one half of the first width and two times the first width; epitaxially growing a semiconductor layer over the buffer layer in the opening, a topmost surface of the semiconductor layer being level with a topmost surface of the non-crystalline dielectric layer, the semiconductor layer being made of a single third crystalline semiconductor material having a third lattice constant, the third lattice constant being substantially same as the second lattice constant; forming a gate dielectric over the semiconductor layer; and forming a gate electrode over the gate dielectric, wherein a topmost surface of the buffer layer is below with the topmost surface of the non-crystalline dielectric layer after forming the gate electrode. Previously presented
The method of claim 15, wherein the second crystalline semiconductor material is different from the third crystalline semiconductor material. Original
A method comprising: forming a non-crystalline dielectric layer over a crystalline Si layer; etching the non-crystalline dielectric layer to form an opening in the non-crystalline dielectric layer, the opening exposing a topmost surface of the crystalline Si layer, the opening having a first width and a first height; epitaxially growing a buffer layer in the opening, the buffer layer comprising a crystalline semiconductor material having a lattice constant different from a lattice constant of crystalline Si, the buffer layer having a second height less than the first height, dislocation defects within the buffer layer extending laterally and terminating at a sidewall of the opening below a third height, the third height being less than the second height, the third height being between one half of the first width and two times the first width; epitaxially growing a crystalline InP layer over and in physical contact with the buffer layer in the opening, a topmost surface of the crystalline InP layer being level with a topmost surface of the non-crystalline dielectric layer, the lattice constant of the buffer layer being substantially same as a lattice constant of crystalline InP; and forming a gate stack over and in physical contact with the topmost surface of the crystalline InP layer, wherein the topmost surface of the crystalline InP layer remains level with the topmost surface of the non-crystalline dielectric layer after forming a gate stack. Previously presented
The method of claim 21, wherein the topmost surface of the crystalline Si layer is a (loo) surface. Previously presented
The method of claim 21, wherein a length of the opening is greater than the first width of the opening. Previously presented
The method of claim 21, wherein a length of the opening is greater than the third height. Previously presented
The method of claim 21, wherein the first height is greater than the first width. Previously presented
The method of claim 21, wherein a density of the dislocation defects within the buffer layer decreases with increasing a distance from a bottom of the opening. Previously presented
The method of claim 21, wherein the non-crystalline dielectric layer comprises silicon nitride or silicon dioxide. Previously presented
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
InP-based MOSFET (inversion-type, enhancement-mode)
Materials described outside the worked examples.
crystalline Si (substrate)
Si
non-crystalline dielectric (mask layer)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1A, a semiconductor substrate 100 has an InP-b ased t op layer 110 dis po sed t h ere o ver. In v ari o us e m bodi m ents, a portion of th is InP layer …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet On Off Ratio | >1000x improvement over enhancement-mode GaAs MOSFETs relative | InP |
Electron Saturation Velocity | 20000000 cm/s |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,541,315Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A, a semiconductor substrate 100 has an InP-b ased t op layer 110 dis po sed t h ere o ver. In v ari o us e m bodi m ents, a portion of th is InP layer …
FIG. 2B. Prio r t o the form ati on o f the high-k g ate dielect r ic 210, surface cleani ng and preparation of the substrate i 00 incl u des I-F-or HCl -based …
FIGS. 3A and 3B show how ART techniques may be used to grow a high- quality InP layer above a buffer layer on a lattice-mismatched underlying material, such as …
FIG. 4C. In an embodiment, InP may be grown epitaxially within the source and drain recesses 400, 400' by CVD with doping performed in situ. With a p-type …
FIGS. 5A-5 G illustrate a method of creating a MOSFET with source and drain regions that are self-aligned to the gate, i.e., the edges of the source and drain …
FIGS. 6A and 6B, to mitigate interfacial instability difficulties between InP and dielectric materials as well as to prevent incongruent sublimation of the I II …
FIG. 7B the gate 710 is defined and the source and drain regions 720, 730 of a transistor are implanted using techniques similar to those discussed above for …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method comprising: forming a mask layer over a substrate, the substrate comprising a first crystalline semiconductor material having a first lattice constant, the mask layer comprising a non- crystalline dielectric material; patterning the mask layer to form an opening in the mask layer, the opening exposing a portion of the substrate; forming a buffer layer in the opening, the buffer layer comprising a second crystalline semiconductor material having a second lattice constant, the second lattice constant being different from the first lattice constant, a topmost surface of the buffer layer being below a topmost surface of the mask layer, dislocation defects within the buffer layer extending laterally and terminating at a sidewall of the opening; forming a semiconductor layer over the buffer layer in the opening, the semiconductor layer fully filling the opening, the semiconductor layer being made of a single third crystalline semiconductor material having a third lattice constant, the third lattice constant being substantially same as the second lattice constant; and forming a gate stack over the semiconductor layer, wherein the topmost surface of the mask layer is level with a topmost surface of the semiconductor layer after forming the gate stack. Previously presented
The method of claim 1, wherein the mask layer has a thickness between about 20 nm and about 5000 0 nm. Original
The method of claim 1, wherein a height of the opening is greater than or equal to a first height, and wherein the first height is between one half of a width of the opening and two times the width of the opening. Previously presented
The method of claim 1, wherein a ratio of a height of the opening to a width of the opening is between about 1 and about 50. Original
The method of claim 1, wherein forming the buffer layer in the opening comprises selectively epitaxially growing the buffer layer in the opening. Original
The method of claim 1, wherein a density of the dislocation defects within the buffer layer decreases with increasing a distance from a bottom of the opening. Original
The method of claim 1, wherein the semiconductor layer is made of InP. Previously presented
The method of claim 1 5, further comprising: etching the semiconductor layer to form a recess in the semiconductor layer; and epitaxially growing a fourth crystalline semiconductor material in the recess. Original
1 8. The method of claim 1 5, wherein a ratio of the first height to the first width is between about 1 and about 50. Original
The method of claim 1 5, wherein the first width is between about 20 nm and about 1000 nm. Original
The method of claim 1 5, wherein the semiconductor layer is made of InP. Previously presented
-14. Canceled
Canceled
A method comprising: forming a non-crystalline dielectric layer over a substrate, the substrate comprising a first crystalline semiconductor material having a first lattice constant; etching the non-crystalline dielectric layer to form an opening in the non-crystalline dielectric layer, the opening exposing a portion of the substrate, the opening having a first width and a first height; epitaxially growing a buffer layer in the opening, the buffer layer comprising a second crystalline semiconductor material having a second lattice constant, the second lattice constant being different from the first lattice constant, the buffer layer having a second height less than the first height, dislocation defects within the buffer layer extending laterally and terminating at a sidewall of the opening below a third height, the third height being less than the second height, the third height being between one half of the first width and two times the first width; epitaxially growing a semiconductor layer over the buffer layer in the opening, a topmost surface of the semiconductor layer being level with a topmost surface of the non-crystalline dielectric layer, the semiconductor layer being made of a single third crystalline semiconductor material having a third lattice constant, the third lattice constant being substantially same as the second lattice constant; forming a gate dielectric over the semiconductor layer; and forming a gate electrode over the gate dielectric, wherein a topmost surface of the buffer layer is below with the topmost surface of the non-crystalline dielectric layer after forming the gate electrode. Previously presented
The method of claim 15, wherein the second crystalline semiconductor material is different from the third crystalline semiconductor material. Original
A method comprising: forming a non-crystalline dielectric layer over a crystalline Si layer; etching the non-crystalline dielectric layer to form an opening in the non-crystalline dielectric layer, the opening exposing a topmost surface of the crystalline Si layer, the opening having a first width and a first height; epitaxially growing a buffer layer in the opening, the buffer layer comprising a crystalline semiconductor material having a lattice constant different from a lattice constant of crystalline Si, the buffer layer having a second height less than the first height, dislocation defects within the buffer layer extending laterally and terminating at a sidewall of the opening below a third height, the third height being less than the second height, the third height being between one half of the first width and two times the first width; epitaxially growing a crystalline InP layer over and in physical contact with the buffer layer in the opening, a topmost surface of the crystalline InP layer being level with a topmost surface of the non-crystalline dielectric layer, the lattice constant of the buffer layer being substantially same as a lattice constant of crystalline InP; and forming a gate stack over and in physical contact with the topmost surface of the crystalline InP layer, wherein the topmost surface of the crystalline InP layer remains level with the topmost surface of the non-crystalline dielectric layer after forming a gate stack. Previously presented
The method of claim 21, wherein the topmost surface of the crystalline Si layer is a (loo) surface. Previously presented
The method of claim 21, wherein a length of the opening is greater than the first width of the opening. Previously presented
The method of claim 21, wherein a length of the opening is greater than the third height. Previously presented
The method of claim 21, wherein the first height is greater than the first width. Previously presented
The method of claim 21, wherein a density of the dislocation defects within the buffer layer decreases with increasing a distance from a bottom of the opening. Previously presented
The method of claim 21, wherein the non-crystalline dielectric layer comprises silicon nitride or silicon dioxide. Previously presented
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
InP-based MOSFET (inversion-type, enhancement-mode)
Materials described outside the worked examples.
crystalline Si (substrate)
Si
non-crystalline dielectric (mask layer)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1A, a semiconductor substrate 100 has an InP-b ased t op layer 110 dis po sed t h ere o ver. In v ari o us e m bodi m ents, a portion of th is InP layer …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet On Off Ratio | >1000x improvement over enhancement-mode GaAs MOSFETs relative | InP |
Electron Saturation Velocity | 20000000 cm/s |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,541,315Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A, a semiconductor substrate 100 has an InP-b ased t op layer 110 dis po sed t h ere o ver. In v ari o us e m bodi m ents, a portion of th is InP layer …
FIG. 2B. Prio r t o the form ati on o f the high-k g ate dielect r ic 210, surface cleani ng and preparation of the substrate i 00 incl u des I-F-or HCl -based …
FIGS. 3A and 3B show how ART techniques may be used to grow a high- quality InP layer above a buffer layer on a lattice-mismatched underlying material, such as …
FIG. 4C. In an embodiment, InP may be grown epitaxially within the source and drain recesses 400, 400' by CVD with doping performed in situ. With a p-type …
FIGS. 5A-5 G illustrate a method of creating a MOSFET with source and drain regions that are self-aligned to the gate, i.e., the edges of the source and drain …
FIGS. 6A and 6B, to mitigate interfacial instability difficulties between InP and dielectric materials as well as to prevent incongruent sublimation of the I II …
FIG. 7B the gate 710 is defined and the source and drain regions 720, 730 of a transistor are implanted using techniques similar to those discussed above for …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method comprising: forming a mask layer over a substrate, the substrate comprising a first crystalline semiconductor material having a first lattice constant, the mask layer comprising a non- crystalline dielectric material; patterning the mask layer to form an opening in the mask layer, the opening exposing a portion of the substrate; forming a buffer layer in the opening, the buffer layer comprising a second crystalline semiconductor material having a second lattice constant, the second lattice constant being different from the first lattice constant, a topmost surface of the buffer layer being below a topmost surface of the mask layer, dislocation defects within the buffer layer extending laterally and terminating at a sidewall of the opening; forming a semiconductor layer over the buffer layer in the opening, the semiconductor layer fully filling the opening, the semiconductor layer being made of a single third crystalline semiconductor material having a third lattice constant, the third lattice constant being substantially same as the second lattice constant; and forming a gate stack over the semiconductor layer, wherein the topmost surface of the mask layer is level with a topmost surface of the semiconductor layer after forming the gate stack. Previously presented
The method of claim 1, wherein the mask layer has a thickness between about 20 nm and about 5000 0 nm. Original
The method of claim 1, wherein a height of the opening is greater than or equal to a first height, and wherein the first height is between one half of a width of the opening and two times the width of the opening. Previously presented
The method of claim 1, wherein a ratio of a height of the opening to a width of the opening is between about 1 and about 50. Original
The method of claim 1, wherein forming the buffer layer in the opening comprises selectively epitaxially growing the buffer layer in the opening. Original
The method of claim 1, wherein a density of the dislocation defects within the buffer layer decreases with increasing a distance from a bottom of the opening. Original
The method of claim 1, wherein the semiconductor layer is made of InP. Previously presented
The method of claim 1 5, further comprising: etching the semiconductor layer to form a recess in the semiconductor layer; and epitaxially growing a fourth crystalline semiconductor material in the recess. Original
1 8. The method of claim 1 5, wherein a ratio of the first height to the first width is between about 1 and about 50. Original
The method of claim 1 5, wherein the first width is between about 20 nm and about 1000 nm. Original
The method of claim 1 5, wherein the semiconductor layer is made of InP. Previously presented
-14. Canceled
Canceled
A method comprising: forming a non-crystalline dielectric layer over a substrate, the substrate comprising a first crystalline semiconductor material having a first lattice constant; etching the non-crystalline dielectric layer to form an opening in the non-crystalline dielectric layer, the opening exposing a portion of the substrate, the opening having a first width and a first height; epitaxially growing a buffer layer in the opening, the buffer layer comprising a second crystalline semiconductor material having a second lattice constant, the second lattice constant being different from the first lattice constant, the buffer layer having a second height less than the first height, dislocation defects within the buffer layer extending laterally and terminating at a sidewall of the opening below a third height, the third height being less than the second height, the third height being between one half of the first width and two times the first width; epitaxially growing a semiconductor layer over the buffer layer in the opening, a topmost surface of the semiconductor layer being level with a topmost surface of the non-crystalline dielectric layer, the semiconductor layer being made of a single third crystalline semiconductor material having a third lattice constant, the third lattice constant being substantially same as the second lattice constant; forming a gate dielectric over the semiconductor layer; and forming a gate electrode over the gate dielectric, wherein a topmost surface of the buffer layer is below with the topmost surface of the non-crystalline dielectric layer after forming the gate electrode. Previously presented
The method of claim 15, wherein the second crystalline semiconductor material is different from the third crystalline semiconductor material. Original
A method comprising: forming a non-crystalline dielectric layer over a crystalline Si layer; etching the non-crystalline dielectric layer to form an opening in the non-crystalline dielectric layer, the opening exposing a topmost surface of the crystalline Si layer, the opening having a first width and a first height; epitaxially growing a buffer layer in the opening, the buffer layer comprising a crystalline semiconductor material having a lattice constant different from a lattice constant of crystalline Si, the buffer layer having a second height less than the first height, dislocation defects within the buffer layer extending laterally and terminating at a sidewall of the opening below a third height, the third height being less than the second height, the third height being between one half of the first width and two times the first width; epitaxially growing a crystalline InP layer over and in physical contact with the buffer layer in the opening, a topmost surface of the crystalline InP layer being level with a topmost surface of the non-crystalline dielectric layer, the lattice constant of the buffer layer being substantially same as a lattice constant of crystalline InP; and forming a gate stack over and in physical contact with the topmost surface of the crystalline InP layer, wherein the topmost surface of the crystalline InP layer remains level with the topmost surface of the non-crystalline dielectric layer after forming a gate stack. Previously presented
The method of claim 21, wherein the topmost surface of the crystalline Si layer is a (loo) surface. Previously presented
The method of claim 21, wherein a length of the opening is greater than the first width of the opening. Previously presented
The method of claim 21, wherein a length of the opening is greater than the third height. Previously presented
The method of claim 21, wherein the first height is greater than the first width. Previously presented
The method of claim 21, wherein a density of the dislocation defects within the buffer layer decreases with increasing a distance from a bottom of the opening. Previously presented
The method of claim 21, wherein the non-crystalline dielectric layer comprises silicon nitride or silicon dioxide. Previously presented
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
InP-based MOSFET (inversion-type, enhancement-mode)
Materials described outside the worked examples.
crystalline Si (substrate)
Si
non-crystalline dielectric (mask layer)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1A, a semiconductor substrate 100 has an InP-b ased t op layer 110 dis po sed t h ere o ver. In v ari o us e m bodi m ents, a portion of th is InP layer …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet On Off Ratio | >1000x improvement over enhancement-mode GaAs MOSFETs relative | InP |
Electron Saturation Velocity | 20000000 cm/s |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,541,315Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1A, a semiconductor substrate 100 has an InP-b ased t op layer 110 dis po sed t h ere o ver. In v ari o us e m bodi m ents, a portion of th is InP layer …
FIG. 2B. Prio r t o the form ati on o f the high-k g ate dielect r ic 210, surface cleani ng and preparation of the substrate i 00 incl u des I-F-or HCl -based …
FIGS. 3A and 3B show how ART techniques may be used to grow a high- quality InP layer above a buffer layer on a lattice-mismatched underlying material, such as …
FIG. 4C. In an embodiment, InP may be grown epitaxially within the source and drain recesses 400, 400' by CVD with doping performed in situ. With a p-type …
FIGS. 5A-5 G illustrate a method of creating a MOSFET with source and drain regions that are self-aligned to the gate, i.e., the edges of the source and drain …
FIGS. 6A and 6B, to mitigate interfacial instability difficulties between InP and dielectric materials as well as to prevent incongruent sublimation of the I II …
FIG. 7B the gate 710 is defined and the source and drain regions 720, 730 of a transistor are implanted using techniques similar to those discussed above for …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method comprising: forming a mask layer over a substrate, the substrate comprising a first crystalline semiconductor material having a first lattice constant, the mask layer comprising a non- crystalline dielectric material; patterning the mask layer to form an opening in the mask layer, the opening exposing a portion of the substrate; forming a buffer layer in the opening, the buffer layer comprising a second crystalline semiconductor material having a second lattice constant, the second lattice constant being different from the first lattice constant, a topmost surface of the buffer layer being below a topmost surface of the mask layer, dislocation defects within the buffer layer extending laterally and terminating at a sidewall of the opening; forming a semiconductor layer over the buffer layer in the opening, the semiconductor layer fully filling the opening, the semiconductor layer being made of a single third crystalline semiconductor material having a third lattice constant, the third lattice constant being substantially same as the second lattice constant; and forming a gate stack over the semiconductor layer, wherein the topmost surface of the mask layer is level with a topmost surface of the semiconductor layer after forming the gate stack. Previously presented
The method of claim 1, wherein the mask layer has a thickness between about 20 nm and about 5000 0 nm. Original
The method of claim 1, wherein a height of the opening is greater than or equal to a first height, and wherein the first height is between one half of a width of the opening and two times the width of the opening. Previously presented
The method of claim 1, wherein a ratio of a height of the opening to a width of the opening is between about 1 and about 50. Original
The method of claim 1, wherein forming the buffer layer in the opening comprises selectively epitaxially growing the buffer layer in the opening. Original
The method of claim 1, wherein a density of the dislocation defects within the buffer layer decreases with increasing a distance from a bottom of the opening. Original
The method of claim 1, wherein the semiconductor layer is made of InP. Previously presented
The method of claim 1 5, further comprising: etching the semiconductor layer to form a recess in the semiconductor layer; and epitaxially growing a fourth crystalline semiconductor material in the recess. Original
1 8. The method of claim 1 5, wherein a ratio of the first height to the first width is between about 1 and about 50. Original
The method of claim 1 5, wherein the first width is between about 20 nm and about 1000 nm. Original
The method of claim 1 5, wherein the semiconductor layer is made of InP. Previously presented
-14. Canceled
Canceled
A method comprising: forming a non-crystalline dielectric layer over a substrate, the substrate comprising a first crystalline semiconductor material having a first lattice constant; etching the non-crystalline dielectric layer to form an opening in the non-crystalline dielectric layer, the opening exposing a portion of the substrate, the opening having a first width and a first height; epitaxially growing a buffer layer in the opening, the buffer layer comprising a second crystalline semiconductor material having a second lattice constant, the second lattice constant being different from the first lattice constant, the buffer layer having a second height less than the first height, dislocation defects within the buffer layer extending laterally and terminating at a sidewall of the opening below a third height, the third height being less than the second height, the third height being between one half of the first width and two times the first width; epitaxially growing a semiconductor layer over the buffer layer in the opening, a topmost surface of the semiconductor layer being level with a topmost surface of the non-crystalline dielectric layer, the semiconductor layer being made of a single third crystalline semiconductor material having a third lattice constant, the third lattice constant being substantially same as the second lattice constant; forming a gate dielectric over the semiconductor layer; and forming a gate electrode over the gate dielectric, wherein a topmost surface of the buffer layer is below with the topmost surface of the non-crystalline dielectric layer after forming the gate electrode. Previously presented
The method of claim 15, wherein the second crystalline semiconductor material is different from the third crystalline semiconductor material. Original
A method comprising: forming a non-crystalline dielectric layer over a crystalline Si layer; etching the non-crystalline dielectric layer to form an opening in the non-crystalline dielectric layer, the opening exposing a topmost surface of the crystalline Si layer, the opening having a first width and a first height; epitaxially growing a buffer layer in the opening, the buffer layer comprising a crystalline semiconductor material having a lattice constant different from a lattice constant of crystalline Si, the buffer layer having a second height less than the first height, dislocation defects within the buffer layer extending laterally and terminating at a sidewall of the opening below a third height, the third height being less than the second height, the third height being between one half of the first width and two times the first width; epitaxially growing a crystalline InP layer over and in physical contact with the buffer layer in the opening, a topmost surface of the crystalline InP layer being level with a topmost surface of the non-crystalline dielectric layer, the lattice constant of the buffer layer being substantially same as a lattice constant of crystalline InP; and forming a gate stack over and in physical contact with the topmost surface of the crystalline InP layer, wherein the topmost surface of the crystalline InP layer remains level with the topmost surface of the non-crystalline dielectric layer after forming a gate stack. Previously presented
The method of claim 21, wherein the topmost surface of the crystalline Si layer is a (loo) surface. Previously presented
The method of claim 21, wherein a length of the opening is greater than the first width of the opening. Previously presented
The method of claim 21, wherein a length of the opening is greater than the third height. Previously presented
The method of claim 21, wherein the first height is greater than the first width. Previously presented
The method of claim 21, wherein a density of the dislocation defects within the buffer layer decreases with increasing a distance from a bottom of the opening. Previously presented
The method of claim 21, wherein the non-crystalline dielectric layer comprises silicon nitride or silicon dioxide. Previously presented
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
InP-based MOSFET (inversion-type, enhancement-mode)
Materials described outside the worked examples.
crystalline Si (substrate)
Si
non-crystalline dielectric (mask layer)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1A, a semiconductor substrate 100 has an InP-b ased t op layer 110 dis po sed t h ere o ver. In v ari o us e m bodi m ents, a portion of th is InP layer …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet On Off Ratio | >1000x improvement over enhancement-mode GaAs MOSFETs relative | InP |
Electron Saturation Velocity | 20000000 cm/s |
Related documents with shared materials, methods, properties, or citations.
Si₃N₄
silicon dioxide
SiO₂
buffer layer crystalline semiconductor
InP
gate dielectric
fourth crystalline semiconductor material (recess fill)
Al₂O₃
HfO
InGaAs
InAs
InSb
FIG. 2B. Prio r t o the form ati on o f the high-k g ate dielect r ic 210, surface cleani ng and preparation of the substrate i 00 incl u des I-F-or HCl -based …
FIG. 7B the gate 710 is defined and the source and drain regions 720, 730 of a transistor are implanted using techniques similar to those discussed above for …
Temperature | 400–1000 °C | — |
Temperature | 300–900 °C | — |
Voltage | 0–8 V | — |
Thickness | 5–10 nm | — |
Voltage | 2–4 V | — |
Temperature | 200–350 °C | — |
Thickness | 20–1000 nm | — |
Thickness | ≤ 15 nm | — |
Thickness | ≤ 5000 nm | — |
Si₃N₄
silicon dioxide
SiO₂
buffer layer crystalline semiconductor
InP
gate dielectric
fourth crystalline semiconductor material (recess fill)
Al₂O₃
HfO
InGaAs
InAs
InSb
FIG. 2B. Prio r t o the form ati on o f the high-k g ate dielect r ic 210, surface cleani ng and preparation of the substrate i 00 incl u des I-F-or HCl -based …
FIG. 7B the gate 710 is defined and the source and drain regions 720, 730 of a transistor are implanted using techniques similar to those discussed above for …
Temperature | 400–1000 °C | — |
Temperature | 300–900 °C | — |
Voltage | 0–8 V | — |
Thickness | 5–10 nm | — |
Voltage | 2–4 V | — |
Temperature | 200–350 °C | — |
Thickness | 20–1000 nm | — |
Thickness | ≤ 15 nm | — |
Thickness | ≤ 5000 nm | — |
Si₃N₄
silicon dioxide
SiO₂
buffer layer crystalline semiconductor
InP
gate dielectric
fourth crystalline semiconductor material (recess fill)
Al₂O₃
HfO
InGaAs
InAs
InSb
FIG. 2B. Prio r t o the form ati on o f the high-k g ate dielect r ic 210, surface cleani ng and preparation of the substrate i 00 incl u des I-F-or HCl -based …
FIG. 7B the gate 710 is defined and the source and drain regions 720, 730 of a transistor are implanted using techniques similar to those discussed above for …
Temperature | 400–1000 °C | — |
Temperature | 300–900 °C | — |
Voltage | 0–8 V | — |
Thickness | 5–10 nm | — |
Voltage | 2–4 V | — |
Temperature | 200–350 °C | — |
Thickness | 20–1000 nm | — |
Thickness | ≤ 15 nm | — |
Thickness | ≤ 5000 nm | — |
Si₃N₄
silicon dioxide
SiO₂
buffer layer crystalline semiconductor
InP
gate dielectric
fourth crystalline semiconductor material (recess fill)
Al₂O₃
HfO
InGaAs
InAs
InSb
FIG. 2B. Prio r t o the form ati on o f the high-k g ate dielect r ic 210, surface cleani ng and preparation of the substrate i 00 incl u des I-F-or HCl -based …
FIG. 7B the gate 710 is defined and the source and drain regions 720, 730 of a transistor are implanted using techniques similar to those discussed above for …
Temperature | 400–1000 °C | — |
Temperature | 300–900 °C | — |
Voltage | 0–8 V | — |
Thickness | 5–10 nm | — |
Voltage | 2–4 V | — |
Temperature | 200–350 °C | — |
Thickness | 20–1000 nm | — |
Thickness | ≤ 15 nm | — |
Thickness | ≤ 5000 nm | — |