Patent
US 10,748,990STACKED INDIUM GALLIUM ARSENIDE NANOSHEETS ON SILICON WITH BOTTOM TRAPEZOID ISOLATION
Takashi Ando
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,748,990Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A is a side cross-sectional view of an initial structure for forming a nanosheet semiconductor device including an epitaxially formed stack of at least …
FIG. 2B to form undercut regions underlying the second nanosheet layer, in accordance with one embodiment of the present disclosure. [00 13]
FIG. 3 is a side cross-sectional view depicting isotopically etching the first nanosheet layer of the structure depicted in
FIG. 4 is a side cross- sectional view depicting one embodiment of forming an inner spacer on etched surfaces of the first nanosheet layer that provide the …
FIG. 5A is a side cross-sectional view of removing the sacrificial gate structure to provide a gate opening exposing channel region portions of the at least two …
FIG. 6A is a side cross-sectional view depicting depositing a dielectric layer filling the inverted apex region, in accordance with one embodiment of the …
FIG. 7A is a side cross-sectional view depicting recessing the dielectric layer that is filling the inverted apex region of the structure depicted in
FIG. 8A is a side cross-sectional view depicting forming a functional gate structure on the channel region portions of the second nanosheet layer that is …
FIG. 9 is a side cross-sectional view depicting forming contacts to the structure depicted in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a nanosheet semiconductor device comprising: epitaxially forming a stack of at least two repeating nanosheets, the at least two repeating nanosheets including a first nanosheet layer of a first I II -V semiconductor material and a second nanosheet layer of a second I II -V semiconductor material; forming source and drain regions on the second nanosheet layer; removing a portion of the first nanosheet layer in the stack of the at least two repeating nanosheets selectively to the second nanosheet layer, wherein the etch process for removing the portion of the first nanosheet layer is selective to facets of the material for the first nanosheet layer to provide an inverted apex at the base of the stack; and depositing a dielectric layer filling the inverted apex region. Original
The method of claim 1, wherein the first I II -V semiconductor material is indium phosphide (InP). Original
The method of claim 1, wherein the second I II -V semiconductor material is comprised of indium gallium arsenide (InGaAs). Original
The method of claim 1, wherein the stack of the at least two repeating nanosheets comprises epitaxial growth on a silicon substrate having a (100) orientation. Original
The method of claim 1, wherein said forming the source and drain regions on the second nanosheet layer comprises: etching exposed portions of the stack of the at least two repeating nanosheets with an anisotropic etch process; isotopically etching the first nanosheet layer to form undercut regions underlying the second nanosheet layer; forming an inner spacer on etched surfaces of the first nanosheet layer that provide the undercut regions; and epitaxially growing the source and drain regions on exposed surfaces of the second nanosheet layer. Original
The method of claim 1, wherein said removing the portion of the first nanosheet layer of indium phosphide (I nP) in the stack of the at least two repeating nanosheets selectively to the second nanosheet layer of indium gallium arsenide (I nGaAs) comprise a wet chemical etch of hydrochloric acid (HCl). Original
The method of claim 1, wherein said depositing the dielectric layer filling the inverted apex region includes spin on deposition following by an etch to recess the deposited material. Original
A method of forming a nanosheet semiconductor device comprising: forming a stack of at least two repeating nanosheets, the at least two repeating nanosheets including a first nanosheet layer of a first I ll -V semiconductor material and a second nanosheet layer of a second III -V semiconductor material; forming source and drain regions on the second nanosheet layer; removing a portion of the first nanosheet layer in the stack of the at least two repeating nanosheets selectively to the second nanosheet layer, wherein the etch process for removing the portion of the first nanosheet layer is selective to facets of the material for the first nanosheet to provide an inverted apex at the base of the stack; and depositing a dielectric layer filling the inverted apex region. Original
The method of claim 11, wherein the first III -V semiconductor material is indium phosphide (InP). Original
The method of claim 11, wherein the source and drain regions are composed of epitaxial merged material between at least two nanosheets of the III -V semiconductor material. Original
The method of claim 11, wherein the stack of at least two repeating nanosheets is present atop a substrate of a type IV semiconductor material. Original
The method of claim 11, wherein the type IV semiconductor material is silicon (Si) having a (100) orientation. Original
Layer stacks claimed or described, ordered top of device to substrate.
nanosheet gate-all-around MOSFET
Materials described outside the worked examples.
indium phosphide
InP
indium gallium arsenide
InGaAs
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 300–900 °C | — |
Thickness | 1–30 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,748,990Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A is a side cross-sectional view of an initial structure for forming a nanosheet semiconductor device including an epitaxially formed stack of at least …
FIG. 2B to form undercut regions underlying the second nanosheet layer, in accordance with one embodiment of the present disclosure. [00 13]
FIG. 3 is a side cross-sectional view depicting isotopically etching the first nanosheet layer of the structure depicted in
FIG. 4 is a side cross- sectional view depicting one embodiment of forming an inner spacer on etched surfaces of the first nanosheet layer that provide the …
FIG. 5A is a side cross-sectional view of removing the sacrificial gate structure to provide a gate opening exposing channel region portions of the at least two …
FIG. 6A is a side cross-sectional view depicting depositing a dielectric layer filling the inverted apex region, in accordance with one embodiment of the …
FIG. 7A is a side cross-sectional view depicting recessing the dielectric layer that is filling the inverted apex region of the structure depicted in
FIG. 8A is a side cross-sectional view depicting forming a functional gate structure on the channel region portions of the second nanosheet layer that is …
FIG. 9 is a side cross-sectional view depicting forming contacts to the structure depicted in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a nanosheet semiconductor device comprising: epitaxially forming a stack of at least two repeating nanosheets, the at least two repeating nanosheets including a first nanosheet layer of a first I II -V semiconductor material and a second nanosheet layer of a second I II -V semiconductor material; forming source and drain regions on the second nanosheet layer; removing a portion of the first nanosheet layer in the stack of the at least two repeating nanosheets selectively to the second nanosheet layer, wherein the etch process for removing the portion of the first nanosheet layer is selective to facets of the material for the first nanosheet layer to provide an inverted apex at the base of the stack; and depositing a dielectric layer filling the inverted apex region. Original
The method of claim 1, wherein the first I II -V semiconductor material is indium phosphide (InP). Original
The method of claim 1, wherein the second I II -V semiconductor material is comprised of indium gallium arsenide (InGaAs). Original
The method of claim 1, wherein the stack of the at least two repeating nanosheets comprises epitaxial growth on a silicon substrate having a (100) orientation. Original
The method of claim 1, wherein said forming the source and drain regions on the second nanosheet layer comprises: etching exposed portions of the stack of the at least two repeating nanosheets with an anisotropic etch process; isotopically etching the first nanosheet layer to form undercut regions underlying the second nanosheet layer; forming an inner spacer on etched surfaces of the first nanosheet layer that provide the undercut regions; and epitaxially growing the source and drain regions on exposed surfaces of the second nanosheet layer. Original
The method of claim 1, wherein said removing the portion of the first nanosheet layer of indium phosphide (I nP) in the stack of the at least two repeating nanosheets selectively to the second nanosheet layer of indium gallium arsenide (I nGaAs) comprise a wet chemical etch of hydrochloric acid (HCl). Original
The method of claim 1, wherein said depositing the dielectric layer filling the inverted apex region includes spin on deposition following by an etch to recess the deposited material. Original
A method of forming a nanosheet semiconductor device comprising: forming a stack of at least two repeating nanosheets, the at least two repeating nanosheets including a first nanosheet layer of a first I ll -V semiconductor material and a second nanosheet layer of a second III -V semiconductor material; forming source and drain regions on the second nanosheet layer; removing a portion of the first nanosheet layer in the stack of the at least two repeating nanosheets selectively to the second nanosheet layer, wherein the etch process for removing the portion of the first nanosheet layer is selective to facets of the material for the first nanosheet to provide an inverted apex at the base of the stack; and depositing a dielectric layer filling the inverted apex region. Original
The method of claim 11, wherein the first III -V semiconductor material is indium phosphide (InP). Original
The method of claim 11, wherein the source and drain regions are composed of epitaxial merged material between at least two nanosheets of the III -V semiconductor material. Original
The method of claim 11, wherein the stack of at least two repeating nanosheets is present atop a substrate of a type IV semiconductor material. Original
The method of claim 11, wherein the type IV semiconductor material is silicon (Si) having a (100) orientation. Original
Layer stacks claimed or described, ordered top of device to substrate.
nanosheet gate-all-around MOSFET
Materials described outside the worked examples.
indium phosphide
InP
indium gallium arsenide
InGaAs
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 300–900 °C | — |
Thickness | 1–30 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,748,990Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A is a side cross-sectional view of an initial structure for forming a nanosheet semiconductor device including an epitaxially formed stack of at least …
FIG. 2B to form undercut regions underlying the second nanosheet layer, in accordance with one embodiment of the present disclosure. [00 13]
FIG. 3 is a side cross-sectional view depicting isotopically etching the first nanosheet layer of the structure depicted in
FIG. 4 is a side cross- sectional view depicting one embodiment of forming an inner spacer on etched surfaces of the first nanosheet layer that provide the …
FIG. 5A is a side cross-sectional view of removing the sacrificial gate structure to provide a gate opening exposing channel region portions of the at least two …
FIG. 6A is a side cross-sectional view depicting depositing a dielectric layer filling the inverted apex region, in accordance with one embodiment of the …
FIG. 7A is a side cross-sectional view depicting recessing the dielectric layer that is filling the inverted apex region of the structure depicted in
FIG. 8A is a side cross-sectional view depicting forming a functional gate structure on the channel region portions of the second nanosheet layer that is …
FIG. 9 is a side cross-sectional view depicting forming contacts to the structure depicted in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a nanosheet semiconductor device comprising: epitaxially forming a stack of at least two repeating nanosheets, the at least two repeating nanosheets including a first nanosheet layer of a first I II -V semiconductor material and a second nanosheet layer of a second I II -V semiconductor material; forming source and drain regions on the second nanosheet layer; removing a portion of the first nanosheet layer in the stack of the at least two repeating nanosheets selectively to the second nanosheet layer, wherein the etch process for removing the portion of the first nanosheet layer is selective to facets of the material for the first nanosheet layer to provide an inverted apex at the base of the stack; and depositing a dielectric layer filling the inverted apex region. Original
The method of claim 1, wherein the first I II -V semiconductor material is indium phosphide (InP). Original
The method of claim 1, wherein the second I II -V semiconductor material is comprised of indium gallium arsenide (InGaAs). Original
The method of claim 1, wherein the stack of the at least two repeating nanosheets comprises epitaxial growth on a silicon substrate having a (100) orientation. Original
The method of claim 1, wherein said forming the source and drain regions on the second nanosheet layer comprises: etching exposed portions of the stack of the at least two repeating nanosheets with an anisotropic etch process; isotopically etching the first nanosheet layer to form undercut regions underlying the second nanosheet layer; forming an inner spacer on etched surfaces of the first nanosheet layer that provide the undercut regions; and epitaxially growing the source and drain regions on exposed surfaces of the second nanosheet layer. Original
The method of claim 1, wherein said removing the portion of the first nanosheet layer of indium phosphide (I nP) in the stack of the at least two repeating nanosheets selectively to the second nanosheet layer of indium gallium arsenide (I nGaAs) comprise a wet chemical etch of hydrochloric acid (HCl). Original
The method of claim 1, wherein said depositing the dielectric layer filling the inverted apex region includes spin on deposition following by an etch to recess the deposited material. Original
A method of forming a nanosheet semiconductor device comprising: forming a stack of at least two repeating nanosheets, the at least two repeating nanosheets including a first nanosheet layer of a first I ll -V semiconductor material and a second nanosheet layer of a second III -V semiconductor material; forming source and drain regions on the second nanosheet layer; removing a portion of the first nanosheet layer in the stack of the at least two repeating nanosheets selectively to the second nanosheet layer, wherein the etch process for removing the portion of the first nanosheet layer is selective to facets of the material for the first nanosheet to provide an inverted apex at the base of the stack; and depositing a dielectric layer filling the inverted apex region. Original
The method of claim 11, wherein the first III -V semiconductor material is indium phosphide (InP). Original
The method of claim 11, wherein the source and drain regions are composed of epitaxial merged material between at least two nanosheets of the III -V semiconductor material. Original
The method of claim 11, wherein the stack of at least two repeating nanosheets is present atop a substrate of a type IV semiconductor material. Original
The method of claim 11, wherein the type IV semiconductor material is silicon (Si) having a (100) orientation. Original
Layer stacks claimed or described, ordered top of device to substrate.
nanosheet gate-all-around MOSFET
Materials described outside the worked examples.
indium phosphide
InP
indium gallium arsenide
InGaAs
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 300–900 °C | — |
Thickness | 1–30 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,748,990Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 A is a side cross-sectional view of an initial structure for forming a nanosheet semiconductor device including an epitaxially formed stack of at least …
FIG. 2B to form undercut regions underlying the second nanosheet layer, in accordance with one embodiment of the present disclosure. [00 13]
FIG. 3 is a side cross-sectional view depicting isotopically etching the first nanosheet layer of the structure depicted in
FIG. 4 is a side cross- sectional view depicting one embodiment of forming an inner spacer on etched surfaces of the first nanosheet layer that provide the …
FIG. 5A is a side cross-sectional view of removing the sacrificial gate structure to provide a gate opening exposing channel region portions of the at least two …
FIG. 6A is a side cross-sectional view depicting depositing a dielectric layer filling the inverted apex region, in accordance with one embodiment of the …
FIG. 7A is a side cross-sectional view depicting recessing the dielectric layer that is filling the inverted apex region of the structure depicted in
FIG. 8A is a side cross-sectional view depicting forming a functional gate structure on the channel region portions of the second nanosheet layer that is …
FIG. 9 is a side cross-sectional view depicting forming contacts to the structure depicted in
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a nanosheet semiconductor device comprising: epitaxially forming a stack of at least two repeating nanosheets, the at least two repeating nanosheets including a first nanosheet layer of a first I II -V semiconductor material and a second nanosheet layer of a second I II -V semiconductor material; forming source and drain regions on the second nanosheet layer; removing a portion of the first nanosheet layer in the stack of the at least two repeating nanosheets selectively to the second nanosheet layer, wherein the etch process for removing the portion of the first nanosheet layer is selective to facets of the material for the first nanosheet layer to provide an inverted apex at the base of the stack; and depositing a dielectric layer filling the inverted apex region. Original
The method of claim 1, wherein the first I II -V semiconductor material is indium phosphide (InP). Original
The method of claim 1, wherein the second I II -V semiconductor material is comprised of indium gallium arsenide (InGaAs). Original
The method of claim 1, wherein the stack of the at least two repeating nanosheets comprises epitaxial growth on a silicon substrate having a (100) orientation. Original
The method of claim 1, wherein said forming the source and drain regions on the second nanosheet layer comprises: etching exposed portions of the stack of the at least two repeating nanosheets with an anisotropic etch process; isotopically etching the first nanosheet layer to form undercut regions underlying the second nanosheet layer; forming an inner spacer on etched surfaces of the first nanosheet layer that provide the undercut regions; and epitaxially growing the source and drain regions on exposed surfaces of the second nanosheet layer. Original
The method of claim 1, wherein said removing the portion of the first nanosheet layer of indium phosphide (I nP) in the stack of the at least two repeating nanosheets selectively to the second nanosheet layer of indium gallium arsenide (I nGaAs) comprise a wet chemical etch of hydrochloric acid (HCl). Original
The method of claim 1, wherein said depositing the dielectric layer filling the inverted apex region includes spin on deposition following by an etch to recess the deposited material. Original
A method of forming a nanosheet semiconductor device comprising: forming a stack of at least two repeating nanosheets, the at least two repeating nanosheets including a first nanosheet layer of a first I ll -V semiconductor material and a second nanosheet layer of a second III -V semiconductor material; forming source and drain regions on the second nanosheet layer; removing a portion of the first nanosheet layer in the stack of the at least two repeating nanosheets selectively to the second nanosheet layer, wherein the etch process for removing the portion of the first nanosheet layer is selective to facets of the material for the first nanosheet to provide an inverted apex at the base of the stack; and depositing a dielectric layer filling the inverted apex region. Original
The method of claim 11, wherein the first III -V semiconductor material is indium phosphide (InP). Original
The method of claim 11, wherein the source and drain regions are composed of epitaxial merged material between at least two nanosheets of the III -V semiconductor material. Original
The method of claim 11, wherein the stack of at least two repeating nanosheets is present atop a substrate of a type IV semiconductor material. Original
The method of claim 11, wherein the type IV semiconductor material is silicon (Si) having a (100) orientation. Original
Layer stacks claimed or described, ordered top of device to substrate.
nanosheet gate-all-around MOSFET
Materials described outside the worked examples.
indium phosphide
InP
indium gallium arsenide
InGaAs
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 300–900 °C | — |
Thickness | 1–30 nm |
Related documents with shared materials, methods, properties, or citations.
silicon
Si
hydrochloric acid
HCl
spin-on dielectric
type IV semiconductor
| — |
Thickness | 5–20 nm | — |
Thickness | 1–15 nm | — |
Thickness | 1–100 nm | — |
Temperature | ≤ 200 °C | — |
silicon
Si
hydrochloric acid
HCl
spin-on dielectric
type IV semiconductor
| — |
Thickness | 5–20 nm | — |
Thickness | 1–15 nm | — |
Thickness | 1–100 nm | — |
Temperature | ≤ 200 °C | — |
silicon
Si
hydrochloric acid
HCl
spin-on dielectric
type IV semiconductor
| — |
Thickness | 5–20 nm | — |
Thickness | 1–15 nm | — |
Thickness | 1–100 nm | — |
Temperature | ≤ 200 °C | — |
silicon
Si
hydrochloric acid
HCl
spin-on dielectric
type IV semiconductor
| — |
Thickness | 5–20 nm | — |
Thickness | 1–15 nm | — |
Thickness | 1–100 nm | — |
Temperature | ≤ 200 °C | — |