Patent
Atlas literature
Patent
US 10,651,288Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a perspective view of the device that includes a plurality of fins formed on a substrate, according to an embodiment.
Figure 2 illustrates a perspective view of the device after a shallow trench isolation (STI) layer is formed on top of the substrate and the fins, according to an embodiment.
Figure 3 illustrates a perspective view of the device after the fins are recessed to form a plurality of trenches, according to an embodiment.
Figure 4A illustrates a perspective view of the device after multi-layer stacks are formed in the trenches, according to an embodiment.
Figure 4B illustrates a perspective view of the device after multi-layer stacks including multiple channel layers are formed in the trenches, according to an embodiment.
Figure 4C illustrates a perspective view of the device having a chevron shaped channel layer, according to an embodiment.
Figure 5 illustrates a perspective view of the device after a cap layer is polished to the same height as the STI layer, according to an embodiment.
Figure 6 illustrates a perspective view of the device after the STI layer is recessed to expose the cap layer within the multi-layer stacks, according to an embodiment.
Figure 7 illustrates a perspective view of the device after a sacrificial gate electrode and sidewall spacers are formed over the cap layer and the STI layer, according to an embodiment.
Figure 8 illustrates a perspective view of the device after portions of the multi-layer stack are recessed to form replacement source/drain (S/D) trenches, according to an embodiment.
Figure 9 illustrates a perspective view of the device after a replacement S/D region is formed in the S/D trenches.
Figure 1O A illustrates a perspective view of the device after an interlayer dielectric (ILD) is formed over the exposed surfaces, according to an embodiment. [0017] Figure lO B illustrates a cross-sectional view of the device illustrated in Figure IO A along the line A, according to an embodiment.
Figure 1 B illustrates a cross-sectional view of the device illustrated in
Figure 1 A along the line A, according to an embodiment.
Figure 12A illustrates a perspective view of the device af t er the STI layer within the sidewall spacers is recessed and the cap layer and the buffer layer are etched to expose channel layer, according to an embodiment.
Figure 12B illustrates a cross-sectional view of the device illustrated in
Figure 13 illustrates a cross-sectional view of the device illustrated in figure 12A along the line A after formation of internal spacers, according to an embodiment.
Figure 14A illustrates a cross-sectional view of the device illustrated in
Figure 14B illustrates a cross-sectional view of the device illustrated in
Figure 15 perspective view of the device after formation of the S/D regions, according to an embodiment.
Figure 16 is a cross-sectional illustration of an interposer implementing one or more embodiments of the invention.
Figure 17 is a schematic of a computing device built in accordance with an embodiment of the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
- 19. Canceled
Canceled
A semiconductor device comprising: a shallow trench isolation (STI) layer; a gate structure completely surrounding a bottommost nanowire channel in a gate region, the gate structure in a gate trench in the S TI layer, the gate trench having a bottom, wherein the bottom of the gate trench in the ST I layer is below a bottom surface of the bottommost nanowire channel; and a source region and a drain region on opposite ends of the bottommost nanowire channel at least partially formed within trenches in the STI layer on opposite sides of the gate region, wherein a top surface of the STI layer is above a top surface of the bottommost nanowire channel, [[and]] wherein a top surface of the source region is above the top surface of the STI layer, and a top surface of the drain region is above the top surface of the STI layer, and wherein a portion of the source region and a portion of the drain region are on a buffer layer, the buffer layer having a bottom surface below a bottom surface of the STI layer. Currently amended
The semiconductor device of claim 20, wherein the bottommost nanowire channel has a chevron shape. Previously presented
The semiconductor device of claim 20, wherein a thickness of the bottommost nanowire channel is smaller than its critical thickness. Previously presented
The semiconductor device of claim 20, wherein the bottommost nanowire channel comprises a material selected from the group consisting of I nGaAs, InAs, I nSb. Previously presented
The semiconductor device of claim 20, wherein each of the trenches in the STI layer on opposite sides of the gate region has a width that is substantially equal to a width of the bottommost nanowire channel. Previously presented
The semiconductor device of claim 20, further comprising additional nanowire channels above the bottommost nanowire channel, each extending from the source region to the drain region, and wherein the gate structure wrapped around the additional nanowire channels in the gate region. Previously presented
A semiconductor device comprising: a shallow trench isolation (STI) layer; a gate structure completely surrounding a bottommost nanowire channel in a gate region, the gate structure in a g ate trench in the STI layer, the gate trench having a bottom, wherein the bottom of the gate trench in the STI layer is below a bottom surface of the bottommost nanowire channel, and wherein the bottommost nanowire channel has a chevron shape; and a source region and a drain region on opposite ends of the bottommost nanowire channel at least partially formed within trenches in the STI layer on opposite sides of the gate region, wherein a top surface of the STI layer is above a top surface of the bottommost nanowire channel. Previously presented
The semiconductor device of claim 26, wherein a thickness of the bottommost nanowire channel is smaller than its critical thickness. Previously presented
The semiconductor device of claim 26, wherein the bottommost nanowire channel comprises a material selected from the group consisting of I nGaAs, InAs, InSb. Previously presented
The semiconductor device of claim 26, wherein each of the trenches in the STI layer on opposite sides of the gate region has a width that is substantially equal to a width of the bottommost nanowire channel. Previously presented
The semiconductor device of claim 26, further comprising additional nanowire channels above the bottommost nanowire channel, each extending from the source region to the drain region, and wherein the gate structure wrapped around the additional nanowire channels in the gate region. Previously presented
A semiconductor device comprising: a shallow trench isolation (STI) layer; a gate structure completely surrounding a bottommost nanowire channel in a gate region, the gate structure in a g ate trench in the STI layer, the gate trench having a bottom, wherein the bottom of the gate trench in the STI layer is below a bottom surface of the bottommost nanowire channel; and a source region and a drain re g ion on opposite ends of the bottommost nanowire channel at least partially formed within trenches in the STI layer on opposite sides of the gate region, wherein a top surface of the STI layer is above a top surface of the bottommost nanowire channel, and wherein a portion of the source region and a portion of the drain region are on a buffer layer, the buffer layer having a bottom surface below a bottom surface of the ST I layer. Currently amended
The semiconductor device of claim 31, wherein the bottommost nanowire channel has a chevron shape. Previously presented
The semiconductor device of claim 31, wherein a thickness of the bottommost nanowire channel is smaller than its critical thickness. Previously presented
The semiconductor device of claim 31, wherein the bottommost nanowire channel comprises a material selected from the group consisting of 4 I nGaAs, InAs, I nSb. Previously presented
The semiconductor device of claim 31, wherein each of the trenches in the STI layer on opposite sides of the gate region has a width that is substantially equal to a width of the bottommost nanowire channel. Previously presented
The semiconductor device of claim 31, further comprising additional nanowire channels above the bottommost nanowire channel, each extending from the source region to the drain region, and wherein the gate structure wrapped around the additional nanowire channels in the gate region. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
gate-all-around nanowire transistor with buffer layer (claim 20)
gate-all-around nanowire transistor with chevron-shape channel (claim 26)
Materials described outside the worked examples.
STI layer
buffer layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 2–10 nm | — |
Thickness | 5–30 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,651,288Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a perspective view of the device that includes a plurality of fins formed on a substrate, according to an embodiment.
Figure 2 illustrates a perspective view of the device after a shallow trench isolation (STI) layer is formed on top of the substrate and the fins, according to an embodiment.
Figure 3 illustrates a perspective view of the device after the fins are recessed to form a plurality of trenches, according to an embodiment.
Figure 4A illustrates a perspective view of the device after multi-layer stacks are formed in the trenches, according to an embodiment.
Figure 4B illustrates a perspective view of the device after multi-layer stacks including multiple channel layers are formed in the trenches, according to an embodiment.
Figure 4C illustrates a perspective view of the device having a chevron shaped channel layer, according to an embodiment.
Figure 5 illustrates a perspective view of the device after a cap layer is polished to the same height as the STI layer, according to an embodiment.
Figure 6 illustrates a perspective view of the device after the STI layer is recessed to expose the cap layer within the multi-layer stacks, according to an embodiment.
Figure 7 illustrates a perspective view of the device after a sacrificial gate electrode and sidewall spacers are formed over the cap layer and the STI layer, according to an embodiment.
Figure 8 illustrates a perspective view of the device after portions of the multi-layer stack are recessed to form replacement source/drain (S/D) trenches, according to an embodiment.
Figure 9 illustrates a perspective view of the device after a replacement S/D region is formed in the S/D trenches.
Figure 1O A illustrates a perspective view of the device after an interlayer dielectric (ILD) is formed over the exposed surfaces, according to an embodiment. [0017] Figure lO B illustrates a cross-sectional view of the device illustrated in Figure IO A along the line A, according to an embodiment.
Figure 1 B illustrates a cross-sectional view of the device illustrated in
Figure 1 A along the line A, according to an embodiment.
Figure 12A illustrates a perspective view of the device af t er the STI layer within the sidewall spacers is recessed and the cap layer and the buffer layer are etched to expose channel layer, according to an embodiment.
Figure 12B illustrates a cross-sectional view of the device illustrated in
Figure 13 illustrates a cross-sectional view of the device illustrated in figure 12A along the line A after formation of internal spacers, according to an embodiment.
Figure 14A illustrates a cross-sectional view of the device illustrated in
Figure 14B illustrates a cross-sectional view of the device illustrated in
Figure 15 perspective view of the device after formation of the S/D regions, according to an embodiment.
Figure 16 is a cross-sectional illustration of an interposer implementing one or more embodiments of the invention.
Figure 17 is a schematic of a computing device built in accordance with an embodiment of the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
- 19. Canceled
Canceled
A semiconductor device comprising: a shallow trench isolation (STI) layer; a gate structure completely surrounding a bottommost nanowire channel in a gate region, the gate structure in a gate trench in the S TI layer, the gate trench having a bottom, wherein the bottom of the gate trench in the ST I layer is below a bottom surface of the bottommost nanowire channel; and a source region and a drain region on opposite ends of the bottommost nanowire channel at least partially formed within trenches in the STI layer on opposite sides of the gate region, wherein a top surface of the STI layer is above a top surface of the bottommost nanowire channel, [[and]] wherein a top surface of the source region is above the top surface of the STI layer, and a top surface of the drain region is above the top surface of the STI layer, and wherein a portion of the source region and a portion of the drain region are on a buffer layer, the buffer layer having a bottom surface below a bottom surface of the STI layer. Currently amended
The semiconductor device of claim 20, wherein the bottommost nanowire channel has a chevron shape. Previously presented
The semiconductor device of claim 20, wherein a thickness of the bottommost nanowire channel is smaller than its critical thickness. Previously presented
The semiconductor device of claim 20, wherein the bottommost nanowire channel comprises a material selected from the group consisting of I nGaAs, InAs, I nSb. Previously presented
The semiconductor device of claim 20, wherein each of the trenches in the STI layer on opposite sides of the gate region has a width that is substantially equal to a width of the bottommost nanowire channel. Previously presented
The semiconductor device of claim 20, further comprising additional nanowire channels above the bottommost nanowire channel, each extending from the source region to the drain region, and wherein the gate structure wrapped around the additional nanowire channels in the gate region. Previously presented
A semiconductor device comprising: a shallow trench isolation (STI) layer; a gate structure completely surrounding a bottommost nanowire channel in a gate region, the gate structure in a g ate trench in the STI layer, the gate trench having a bottom, wherein the bottom of the gate trench in the STI layer is below a bottom surface of the bottommost nanowire channel, and wherein the bottommost nanowire channel has a chevron shape; and a source region and a drain region on opposite ends of the bottommost nanowire channel at least partially formed within trenches in the STI layer on opposite sides of the gate region, wherein a top surface of the STI layer is above a top surface of the bottommost nanowire channel. Previously presented
The semiconductor device of claim 26, wherein a thickness of the bottommost nanowire channel is smaller than its critical thickness. Previously presented
The semiconductor device of claim 26, wherein the bottommost nanowire channel comprises a material selected from the group consisting of I nGaAs, InAs, InSb. Previously presented
The semiconductor device of claim 26, wherein each of the trenches in the STI layer on opposite sides of the gate region has a width that is substantially equal to a width of the bottommost nanowire channel. Previously presented
The semiconductor device of claim 26, further comprising additional nanowire channels above the bottommost nanowire channel, each extending from the source region to the drain region, and wherein the gate structure wrapped around the additional nanowire channels in the gate region. Previously presented
A semiconductor device comprising: a shallow trench isolation (STI) layer; a gate structure completely surrounding a bottommost nanowire channel in a gate region, the gate structure in a g ate trench in the STI layer, the gate trench having a bottom, wherein the bottom of the gate trench in the STI layer is below a bottom surface of the bottommost nanowire channel; and a source region and a drain re g ion on opposite ends of the bottommost nanowire channel at least partially formed within trenches in the STI layer on opposite sides of the gate region, wherein a top surface of the STI layer is above a top surface of the bottommost nanowire channel, and wherein a portion of the source region and a portion of the drain region are on a buffer layer, the buffer layer having a bottom surface below a bottom surface of the ST I layer. Currently amended
The semiconductor device of claim 31, wherein the bottommost nanowire channel has a chevron shape. Previously presented
The semiconductor device of claim 31, wherein a thickness of the bottommost nanowire channel is smaller than its critical thickness. Previously presented
The semiconductor device of claim 31, wherein the bottommost nanowire channel comprises a material selected from the group consisting of 4 I nGaAs, InAs, I nSb. Previously presented
The semiconductor device of claim 31, wherein each of the trenches in the STI layer on opposite sides of the gate region has a width that is substantially equal to a width of the bottommost nanowire channel. Previously presented
The semiconductor device of claim 31, further comprising additional nanowire channels above the bottommost nanowire channel, each extending from the source region to the drain region, and wherein the gate structure wrapped around the additional nanowire channels in the gate region. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
gate-all-around nanowire transistor with buffer layer (claim 20)
gate-all-around nanowire transistor with chevron-shape channel (claim 26)
Materials described outside the worked examples.
STI layer
buffer layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 2–10 nm | — |
Thickness | 5–30 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,651,288Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a perspective view of the device that includes a plurality of fins formed on a substrate, according to an embodiment.
Figure 2 illustrates a perspective view of the device after a shallow trench isolation (STI) layer is formed on top of the substrate and the fins, according to an embodiment.
Figure 3 illustrates a perspective view of the device after the fins are recessed to form a plurality of trenches, according to an embodiment.
Figure 4A illustrates a perspective view of the device after multi-layer stacks are formed in the trenches, according to an embodiment.
Figure 4B illustrates a perspective view of the device after multi-layer stacks including multiple channel layers are formed in the trenches, according to an embodiment.
Figure 4C illustrates a perspective view of the device having a chevron shaped channel layer, according to an embodiment.
Figure 5 illustrates a perspective view of the device after a cap layer is polished to the same height as the STI layer, according to an embodiment.
Figure 6 illustrates a perspective view of the device after the STI layer is recessed to expose the cap layer within the multi-layer stacks, according to an embodiment.
Figure 7 illustrates a perspective view of the device after a sacrificial gate electrode and sidewall spacers are formed over the cap layer and the STI layer, according to an embodiment.
Figure 8 illustrates a perspective view of the device after portions of the multi-layer stack are recessed to form replacement source/drain (S/D) trenches, according to an embodiment.
Figure 9 illustrates a perspective view of the device after a replacement S/D region is formed in the S/D trenches.
Figure 1O A illustrates a perspective view of the device after an interlayer dielectric (ILD) is formed over the exposed surfaces, according to an embodiment. [0017] Figure lO B illustrates a cross-sectional view of the device illustrated in Figure IO A along the line A, according to an embodiment.
Figure 1 B illustrates a cross-sectional view of the device illustrated in
Figure 1 A along the line A, according to an embodiment.
Figure 12A illustrates a perspective view of the device af t er the STI layer within the sidewall spacers is recessed and the cap layer and the buffer layer are etched to expose channel layer, according to an embodiment.
Figure 12B illustrates a cross-sectional view of the device illustrated in
Figure 13 illustrates a cross-sectional view of the device illustrated in figure 12A along the line A after formation of internal spacers, according to an embodiment.
Figure 14A illustrates a cross-sectional view of the device illustrated in
Figure 14B illustrates a cross-sectional view of the device illustrated in
Figure 15 perspective view of the device after formation of the S/D regions, according to an embodiment.
Figure 16 is a cross-sectional illustration of an interposer implementing one or more embodiments of the invention.
Figure 17 is a schematic of a computing device built in accordance with an embodiment of the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
- 19. Canceled
Canceled
A semiconductor device comprising: a shallow trench isolation (STI) layer; a gate structure completely surrounding a bottommost nanowire channel in a gate region, the gate structure in a gate trench in the S TI layer, the gate trench having a bottom, wherein the bottom of the gate trench in the ST I layer is below a bottom surface of the bottommost nanowire channel; and a source region and a drain region on opposite ends of the bottommost nanowire channel at least partially formed within trenches in the STI layer on opposite sides of the gate region, wherein a top surface of the STI layer is above a top surface of the bottommost nanowire channel, [[and]] wherein a top surface of the source region is above the top surface of the STI layer, and a top surface of the drain region is above the top surface of the STI layer, and wherein a portion of the source region and a portion of the drain region are on a buffer layer, the buffer layer having a bottom surface below a bottom surface of the STI layer. Currently amended
The semiconductor device of claim 20, wherein the bottommost nanowire channel has a chevron shape. Previously presented
The semiconductor device of claim 20, wherein a thickness of the bottommost nanowire channel is smaller than its critical thickness. Previously presented
The semiconductor device of claim 20, wherein the bottommost nanowire channel comprises a material selected from the group consisting of I nGaAs, InAs, I nSb. Previously presented
The semiconductor device of claim 20, wherein each of the trenches in the STI layer on opposite sides of the gate region has a width that is substantially equal to a width of the bottommost nanowire channel. Previously presented
The semiconductor device of claim 20, further comprising additional nanowire channels above the bottommost nanowire channel, each extending from the source region to the drain region, and wherein the gate structure wrapped around the additional nanowire channels in the gate region. Previously presented
A semiconductor device comprising: a shallow trench isolation (STI) layer; a gate structure completely surrounding a bottommost nanowire channel in a gate region, the gate structure in a g ate trench in the STI layer, the gate trench having a bottom, wherein the bottom of the gate trench in the STI layer is below a bottom surface of the bottommost nanowire channel, and wherein the bottommost nanowire channel has a chevron shape; and a source region and a drain region on opposite ends of the bottommost nanowire channel at least partially formed within trenches in the STI layer on opposite sides of the gate region, wherein a top surface of the STI layer is above a top surface of the bottommost nanowire channel. Previously presented
The semiconductor device of claim 26, wherein a thickness of the bottommost nanowire channel is smaller than its critical thickness. Previously presented
The semiconductor device of claim 26, wherein the bottommost nanowire channel comprises a material selected from the group consisting of I nGaAs, InAs, InSb. Previously presented
The semiconductor device of claim 26, wherein each of the trenches in the STI layer on opposite sides of the gate region has a width that is substantially equal to a width of the bottommost nanowire channel. Previously presented
The semiconductor device of claim 26, further comprising additional nanowire channels above the bottommost nanowire channel, each extending from the source region to the drain region, and wherein the gate structure wrapped around the additional nanowire channels in the gate region. Previously presented
A semiconductor device comprising: a shallow trench isolation (STI) layer; a gate structure completely surrounding a bottommost nanowire channel in a gate region, the gate structure in a g ate trench in the STI layer, the gate trench having a bottom, wherein the bottom of the gate trench in the STI layer is below a bottom surface of the bottommost nanowire channel; and a source region and a drain re g ion on opposite ends of the bottommost nanowire channel at least partially formed within trenches in the STI layer on opposite sides of the gate region, wherein a top surface of the STI layer is above a top surface of the bottommost nanowire channel, and wherein a portion of the source region and a portion of the drain region are on a buffer layer, the buffer layer having a bottom surface below a bottom surface of the ST I layer. Currently amended
The semiconductor device of claim 31, wherein the bottommost nanowire channel has a chevron shape. Previously presented
The semiconductor device of claim 31, wherein a thickness of the bottommost nanowire channel is smaller than its critical thickness. Previously presented
The semiconductor device of claim 31, wherein the bottommost nanowire channel comprises a material selected from the group consisting of 4 I nGaAs, InAs, I nSb. Previously presented
The semiconductor device of claim 31, wherein each of the trenches in the STI layer on opposite sides of the gate region has a width that is substantially equal to a width of the bottommost nanowire channel. Previously presented
The semiconductor device of claim 31, further comprising additional nanowire channels above the bottommost nanowire channel, each extending from the source region to the drain region, and wherein the gate structure wrapped around the additional nanowire channels in the gate region. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
gate-all-around nanowire transistor with buffer layer (claim 20)
gate-all-around nanowire transistor with chevron-shape channel (claim 26)
Materials described outside the worked examples.
STI layer
buffer layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 2–10 nm | — |
Thickness | 5–30 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,651,288Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a perspective view of the device that includes a plurality of fins formed on a substrate, according to an embodiment.
Figure 2 illustrates a perspective view of the device after a shallow trench isolation (STI) layer is formed on top of the substrate and the fins, according to an embodiment.
Figure 3 illustrates a perspective view of the device after the fins are recessed to form a plurality of trenches, according to an embodiment.
Figure 4A illustrates a perspective view of the device after multi-layer stacks are formed in the trenches, according to an embodiment.
Figure 4B illustrates a perspective view of the device after multi-layer stacks including multiple channel layers are formed in the trenches, according to an embodiment.
Figure 4C illustrates a perspective view of the device having a chevron shaped channel layer, according to an embodiment.
Figure 5 illustrates a perspective view of the device after a cap layer is polished to the same height as the STI layer, according to an embodiment.
Figure 6 illustrates a perspective view of the device after the STI layer is recessed to expose the cap layer within the multi-layer stacks, according to an embodiment.
Figure 7 illustrates a perspective view of the device after a sacrificial gate electrode and sidewall spacers are formed over the cap layer and the STI layer, according to an embodiment.
Figure 8 illustrates a perspective view of the device after portions of the multi-layer stack are recessed to form replacement source/drain (S/D) trenches, according to an embodiment.
Figure 9 illustrates a perspective view of the device after a replacement S/D region is formed in the S/D trenches.
Figure 1O A illustrates a perspective view of the device after an interlayer dielectric (ILD) is formed over the exposed surfaces, according to an embodiment. [0017] Figure lO B illustrates a cross-sectional view of the device illustrated in Figure IO A along the line A, according to an embodiment.
Figure 1 B illustrates a cross-sectional view of the device illustrated in
Figure 1 A along the line A, according to an embodiment.
Figure 12A illustrates a perspective view of the device af t er the STI layer within the sidewall spacers is recessed and the cap layer and the buffer layer are etched to expose channel layer, according to an embodiment.
Figure 12B illustrates a cross-sectional view of the device illustrated in
Figure 13 illustrates a cross-sectional view of the device illustrated in figure 12A along the line A after formation of internal spacers, according to an embodiment.
Figure 14A illustrates a cross-sectional view of the device illustrated in
Figure 14B illustrates a cross-sectional view of the device illustrated in
Figure 15 perspective view of the device after formation of the S/D regions, according to an embodiment.
Figure 16 is a cross-sectional illustration of an interposer implementing one or more embodiments of the invention.
Figure 17 is a schematic of a computing device built in accordance with an embodiment of the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
- 19. Canceled
Canceled
A semiconductor device comprising: a shallow trench isolation (STI) layer; a gate structure completely surrounding a bottommost nanowire channel in a gate region, the gate structure in a gate trench in the S TI layer, the gate trench having a bottom, wherein the bottom of the gate trench in the ST I layer is below a bottom surface of the bottommost nanowire channel; and a source region and a drain region on opposite ends of the bottommost nanowire channel at least partially formed within trenches in the STI layer on opposite sides of the gate region, wherein a top surface of the STI layer is above a top surface of the bottommost nanowire channel, [[and]] wherein a top surface of the source region is above the top surface of the STI layer, and a top surface of the drain region is above the top surface of the STI layer, and wherein a portion of the source region and a portion of the drain region are on a buffer layer, the buffer layer having a bottom surface below a bottom surface of the STI layer. Currently amended
The semiconductor device of claim 20, wherein the bottommost nanowire channel has a chevron shape. Previously presented
The semiconductor device of claim 20, wherein a thickness of the bottommost nanowire channel is smaller than its critical thickness. Previously presented
The semiconductor device of claim 20, wherein the bottommost nanowire channel comprises a material selected from the group consisting of I nGaAs, InAs, I nSb. Previously presented
The semiconductor device of claim 20, wherein each of the trenches in the STI layer on opposite sides of the gate region has a width that is substantially equal to a width of the bottommost nanowire channel. Previously presented
The semiconductor device of claim 20, further comprising additional nanowire channels above the bottommost nanowire channel, each extending from the source region to the drain region, and wherein the gate structure wrapped around the additional nanowire channels in the gate region. Previously presented
A semiconductor device comprising: a shallow trench isolation (STI) layer; a gate structure completely surrounding a bottommost nanowire channel in a gate region, the gate structure in a g ate trench in the STI layer, the gate trench having a bottom, wherein the bottom of the gate trench in the STI layer is below a bottom surface of the bottommost nanowire channel, and wherein the bottommost nanowire channel has a chevron shape; and a source region and a drain region on opposite ends of the bottommost nanowire channel at least partially formed within trenches in the STI layer on opposite sides of the gate region, wherein a top surface of the STI layer is above a top surface of the bottommost nanowire channel. Previously presented
The semiconductor device of claim 26, wherein a thickness of the bottommost nanowire channel is smaller than its critical thickness. Previously presented
The semiconductor device of claim 26, wherein the bottommost nanowire channel comprises a material selected from the group consisting of I nGaAs, InAs, InSb. Previously presented
The semiconductor device of claim 26, wherein each of the trenches in the STI layer on opposite sides of the gate region has a width that is substantially equal to a width of the bottommost nanowire channel. Previously presented
The semiconductor device of claim 26, further comprising additional nanowire channels above the bottommost nanowire channel, each extending from the source region to the drain region, and wherein the gate structure wrapped around the additional nanowire channels in the gate region. Previously presented
A semiconductor device comprising: a shallow trench isolation (STI) layer; a gate structure completely surrounding a bottommost nanowire channel in a gate region, the gate structure in a g ate trench in the STI layer, the gate trench having a bottom, wherein the bottom of the gate trench in the STI layer is below a bottom surface of the bottommost nanowire channel; and a source region and a drain re g ion on opposite ends of the bottommost nanowire channel at least partially formed within trenches in the STI layer on opposite sides of the gate region, wherein a top surface of the STI layer is above a top surface of the bottommost nanowire channel, and wherein a portion of the source region and a portion of the drain region are on a buffer layer, the buffer layer having a bottom surface below a bottom surface of the ST I layer. Currently amended
The semiconductor device of claim 31, wherein the bottommost nanowire channel has a chevron shape. Previously presented
The semiconductor device of claim 31, wherein a thickness of the bottommost nanowire channel is smaller than its critical thickness. Previously presented
The semiconductor device of claim 31, wherein the bottommost nanowire channel comprises a material selected from the group consisting of 4 I nGaAs, InAs, I nSb. Previously presented
The semiconductor device of claim 31, wherein each of the trenches in the STI layer on opposite sides of the gate region has a width that is substantially equal to a width of the bottommost nanowire channel. Previously presented
The semiconductor device of claim 31, further comprising additional nanowire channels above the bottommost nanowire channel, each extending from the source region to the drain region, and wherein the gate structure wrapped around the additional nanowire channels in the gate region. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
gate-all-around nanowire transistor with buffer layer (claim 20)
gate-all-around nanowire transistor with chevron-shape channel (claim 26)
Materials described outside the worked examples.
STI layer
buffer layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 2–10 nm | — |
Thickness | 5–30 nm |
Related documents with shared materials, methods, properties, or citations.
gate-all-around nanowire transistor with buffer layer (claim 31)
pseudomorphic InGaAs gate-all-around nanowire transistor (described embodiment)
InGaAs
InAs
InSb
cap layer
silicon oxide (STI)
SiO₂
| — |
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV | — |
Thickness | 10–20 nm | — |
Thickness | 50–150 nm | — |
Thickness | 1–100 nm | — |
Thickness | 10–12 nm | — |
Thickness | 0–20 nm | — |
gate-all-around nanowire transistor with buffer layer (claim 31)
pseudomorphic InGaAs gate-all-around nanowire transistor (described embodiment)
InGaAs
InAs
InSb
cap layer
silicon oxide (STI)
SiO₂
| — |
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV | — |
Thickness | 10–20 nm | — |
Thickness | 50–150 nm | — |
Thickness | 1–100 nm | — |
Thickness | 10–12 nm | — |
Thickness | 0–20 nm | — |
gate-all-around nanowire transistor with buffer layer (claim 31)
pseudomorphic InGaAs gate-all-around nanowire transistor (described embodiment)
InGaAs
InAs
InSb
cap layer
silicon oxide (STI)
SiO₂
| — |
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV | — |
Thickness | 10–20 nm | — |
Thickness | 50–150 nm | — |
Thickness | 1–100 nm | — |
Thickness | 10–12 nm | — |
Thickness | 0–20 nm | — |
gate-all-around nanowire transistor with buffer layer (claim 31)
pseudomorphic InGaAs gate-all-around nanowire transistor (described embodiment)
InGaAs
InAs
InSb
cap layer
silicon oxide (STI)
SiO₂
| — |
— | 4.9–5.2 eV | — |
— | 3.9–4.2 eV | — |
Thickness | 10–20 nm | — |
Thickness | 50–150 nm | — |
Thickness | 1–100 nm | — |
Thickness | 10–12 nm | — |
Thickness | 0–20 nm | — |
