Patent
US 10,290,709APPARATUS AND METHODS TO CREATE AN INDIUM GALLIUM ARSENIDE ACTIVE CHANNEL HAVING INDIUM RICH SURFACES
Glenn A. Glass
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
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US 10,290,709Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1; however, it is understood that any appropriate number of fins 112 could be fabricated. In one embodiment, an etch mask (not shown) may be patterned on …
FIG. 2, a dielectric material may be deposited, by any appropriate deposition 25 process, over the substrate 102 and the fins 112, and the dielectric material …
FIG. 3). The sub-structure 144 may be formed 10 by any known formation process. In one embodiment of the present description, the sub- structure may be a high …
FIG. 4, a nucleation layer 142 may be formed in the nucleation trench 132. 5 The nucleation layer 142 may be formed by any formation process and may be any …
FIG. 5) and the thickness T a of the active channel 146 may be in the range, for example, of 500 to 5000 A, in accordance with some specific example …
FIG. 6, the portion 148 of the indium gallium arsenide active 5 channel 146 may be removed, such as by chemical mechanical planarization. As shown in
FIG. 7 with the higher indium concentration having darker shading. This indium distribution is graphically illustrated in
FIG. 8 with the x-axis being the distance from one indium rich surface 145 1 to the opposing indium rich surface 145 2 of the indium gallium arsenide active …
FIG. 9, the isolation structures 122 may be recessed, such as by an etching process, such that at least a portion of the indium gallium arsenide active channel …
FIG. 10) will result in high electron mobility and the electrostatics in terms of the ability to turn a transistor on and off will be better, i.e., faster …
FIG. 11, a gate spacer 156 may be deposited and patterned on the gate electrode 154 with well-known deposition and etching techniques. The gate spacer 156 may …
FIG. 12, the indium gallium arsenide active channel 146 may be formed on the sub-structure 144 within the trench 124 (see
FIG. 13, the portion 148 of the indium gallium arsenide active channel 146 may be removed, such as by chemical mechanical planarization. As shown in
FIG. 14 with the 5 indium having darker shading. This indium distribution is graphically illustrated in
FIG. 15 with the x-axis being the distance from one indium rich surface 145 1 to the opposing indium rich surface 145 2 of the indium gallium arsenide active …
FIG. 16, the isolation structures 122 may be recessed, such as by an etching process, such that at least a portion of the indium gallium arsenide active …
FIG. 17, at least one gate 150 may be form over the portion of the indium gallium arsenide active channel 146 extending above the isolation structures 122. The …
FIG. 18, a gate spacer 156 may be deposited and patterned on the gate electrode 154 with well-known 30 deposition and etching techniques. It is understood that …
FIG. 19. The sacrificial gate electrode 154 and the gate dielectric may be removed to expose the indium gallium arsenide active channel 146 between the …
FIG. 20 with only cross- sectioned structures shown). 15 As shown in
FIG. 22, the isolation structures 122 may be recessed within the exposed indium gallium arsenide active channel region 146, such as by etching, to expose a …
FIG. 23. 20 A dielectric material 166 may be deposited to fill the space lef t from the removal for the sub-structure 144 (see
FIG. 24, or to form a void 168, as shown in
FIG. 25. Thereaf t er, the remaining components of a transistor may be formed following a known processing flow, such as a t ri -gate processing flow, as will be …
FIG. 26, a gate oxide 25 layer 172 may be formed to surround the exposed active channel 146 and a gate electrode layer 174 may be formed to surround the gate …
FIG. 27 illustrates a computing device in accordance with one implementation of the present description. DESCRIPTION OF EMBODIMENTS 5 In the following detailed …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A microelectronic structure comprising: a substrate having a first surface: and an indium gallium arsenide active channel, wherein the indium gallium arsenide active channel comprises a fin having a pair of opposing surfaces that are substantially perpendicular to the first surface of the substrate, wherein each of the surfaces has an indium content higher than the average indium content of the indium gallium arsenide active channel, and wherein the indium content of the indium gallium arsenide active channel is graded between a higher indium content at each of the pair of opposing surfaces to a lower indium content at a center region between the pair of opposing surfaces. Currently amended
- 4. Canceled
Canceled
The microelectronic structure of claim [[3]] 1 L further including a sub- structure formed between the indium gallium arsenide active channel and the substrate, wherein the sub-structure abuts the indium gallium arsenide active channel. Currently amended
The microelectronic structure of claim 5, wherein the sub-structure comprises a dopant and a material selected from the group consisting of indium gallium arsenide, indium arsenide, indium antimonide. Withdrawn
The microelectronic structure of claim 5, wherein the sub-structure comprises a material selected from the group consisting of indium aluminum arsenide, indium phosphide, gallium phosphide, gallium arsenide, gallium arsenide antimonide, aluminum arsenide antimonide, indium aluminum gallium arsenide, indium aluminum gallium phosphide, and aluminum gallium arsenide. Original
The microelectronic structure of claim 3, further including an insulative buffer formed between the indium gallium arsenide active channel and the substrate. Withdrawn
The microelectronic structure of claim 3, further including a nucleation trench extending into the substrate and a nucleation layer abutting the nucleation trench. Original
The microelectronic structure of claim 11, wherein the nucleation trench comprises a nucleation trench having (111) faceting. Original
The microelectronic structure of claim 11, wherein the nucleation layer comprises a material selected from the group consisting of indium phosphide, gallium phosphide, and gallium arsenide. Original
-23. Canceled
Canceled
An electronic system, comprising: a board; and a microelectronic device attached to the board, wherein the microelectronic device includes at least one microelectronic structure comprising: a substrate having a first surface; and an indium gallium arsenide active channel, wherein the indium gallium arsenide active channel comprises a fin having a pair of opposing surfaces that are substantially perpendicular to the first surface of the substrate, wherein each of the surfaces has an indium content higher than the average indium content of the indium gallium arsenide active channel, and wherein the indium content of the indium gallium arsenide active channel is graded between a higher indium content at each of the pair of opposing surfaces to a lower indium content at a center region between the pair of opposing surfaces. Currently amended
- 27. Canceled
Canceled
The electronic system of claim [[26]] 2 4, further including a sub- structure formed between the indium gallium arsenide active channel and the substrate, wherein the sub-structure abuts the indium gallium arsenide active channel. Currently amended
The electronic system of claim 28, wherein the sub-structure comprises a dopant and a material selected from the group consisting of indium gallium arsenide, indium arsenide, indium antimonide. Withdrawn
The electronic system of claim 28, wherein the sub-structure comprises a material selected from the group consisting of indium aluminum arsenide, indium phosphide, gallium phosphide, gallium arsenide, gallium arsenide antimonide, aluminum arsenide antimonide, indium aluminum gallium arsenide, indium aluminum gallium phosphide, and aluminum gallium arsenide. Previously presented
The electronic system of claim 26, further including an insulative buffer formed between the indium gallium arsenide active channel and the substrate. Withdrawn
The electronic system of claim 26, further including a nucleation trench extending into the substrate and a nucleation layer abutting the nucleation trench. Previously presented
The electronic system of claim 34, wherein the nucleation trench comprises a nucleation trench having (111) faceting. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
non-planar transistor microelectronic structure (fin-based)
electronic system with non-planar transistor microelectronic device
Materials described outside the worked examples.
indium gallium arsenide
InGaAs
silicon
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3). The sub-structure 144 may be formed 10 by any known formation process. In one embodiment of the present description, the sub- structure may be a high …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 300–650 °C | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
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US 10,290,709Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1; however, it is understood that any appropriate number of fins 112 could be fabricated. In one embodiment, an etch mask (not shown) may be patterned on …
FIG. 2, a dielectric material may be deposited, by any appropriate deposition 25 process, over the substrate 102 and the fins 112, and the dielectric material …
FIG. 3). The sub-structure 144 may be formed 10 by any known formation process. In one embodiment of the present description, the sub- structure may be a high …
FIG. 4, a nucleation layer 142 may be formed in the nucleation trench 132. 5 The nucleation layer 142 may be formed by any formation process and may be any …
FIG. 5) and the thickness T a of the active channel 146 may be in the range, for example, of 500 to 5000 A, in accordance with some specific example …
FIG. 6, the portion 148 of the indium gallium arsenide active 5 channel 146 may be removed, such as by chemical mechanical planarization. As shown in
FIG. 7 with the higher indium concentration having darker shading. This indium distribution is graphically illustrated in
FIG. 8 with the x-axis being the distance from one indium rich surface 145 1 to the opposing indium rich surface 145 2 of the indium gallium arsenide active …
FIG. 9, the isolation structures 122 may be recessed, such as by an etching process, such that at least a portion of the indium gallium arsenide active channel …
FIG. 10) will result in high electron mobility and the electrostatics in terms of the ability to turn a transistor on and off will be better, i.e., faster …
FIG. 11, a gate spacer 156 may be deposited and patterned on the gate electrode 154 with well-known deposition and etching techniques. The gate spacer 156 may …
FIG. 12, the indium gallium arsenide active channel 146 may be formed on the sub-structure 144 within the trench 124 (see
FIG. 13, the portion 148 of the indium gallium arsenide active channel 146 may be removed, such as by chemical mechanical planarization. As shown in
FIG. 14 with the 5 indium having darker shading. This indium distribution is graphically illustrated in
FIG. 15 with the x-axis being the distance from one indium rich surface 145 1 to the opposing indium rich surface 145 2 of the indium gallium arsenide active …
FIG. 16, the isolation structures 122 may be recessed, such as by an etching process, such that at least a portion of the indium gallium arsenide active …
FIG. 17, at least one gate 150 may be form over the portion of the indium gallium arsenide active channel 146 extending above the isolation structures 122. The …
FIG. 18, a gate spacer 156 may be deposited and patterned on the gate electrode 154 with well-known 30 deposition and etching techniques. It is understood that …
FIG. 19. The sacrificial gate electrode 154 and the gate dielectric may be removed to expose the indium gallium arsenide active channel 146 between the …
FIG. 20 with only cross- sectioned structures shown). 15 As shown in
FIG. 22, the isolation structures 122 may be recessed within the exposed indium gallium arsenide active channel region 146, such as by etching, to expose a …
FIG. 23. 20 A dielectric material 166 may be deposited to fill the space lef t from the removal for the sub-structure 144 (see
FIG. 24, or to form a void 168, as shown in
FIG. 25. Thereaf t er, the remaining components of a transistor may be formed following a known processing flow, such as a t ri -gate processing flow, as will be …
FIG. 26, a gate oxide 25 layer 172 may be formed to surround the exposed active channel 146 and a gate electrode layer 174 may be formed to surround the gate …
FIG. 27 illustrates a computing device in accordance with one implementation of the present description. DESCRIPTION OF EMBODIMENTS 5 In the following detailed …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A microelectronic structure comprising: a substrate having a first surface: and an indium gallium arsenide active channel, wherein the indium gallium arsenide active channel comprises a fin having a pair of opposing surfaces that are substantially perpendicular to the first surface of the substrate, wherein each of the surfaces has an indium content higher than the average indium content of the indium gallium arsenide active channel, and wherein the indium content of the indium gallium arsenide active channel is graded between a higher indium content at each of the pair of opposing surfaces to a lower indium content at a center region between the pair of opposing surfaces. Currently amended
- 4. Canceled
Canceled
The microelectronic structure of claim [[3]] 1 L further including a sub- structure formed between the indium gallium arsenide active channel and the substrate, wherein the sub-structure abuts the indium gallium arsenide active channel. Currently amended
The microelectronic structure of claim 5, wherein the sub-structure comprises a dopant and a material selected from the group consisting of indium gallium arsenide, indium arsenide, indium antimonide. Withdrawn
The microelectronic structure of claim 5, wherein the sub-structure comprises a material selected from the group consisting of indium aluminum arsenide, indium phosphide, gallium phosphide, gallium arsenide, gallium arsenide antimonide, aluminum arsenide antimonide, indium aluminum gallium arsenide, indium aluminum gallium phosphide, and aluminum gallium arsenide. Original
The microelectronic structure of claim 3, further including an insulative buffer formed between the indium gallium arsenide active channel and the substrate. Withdrawn
The microelectronic structure of claim 3, further including a nucleation trench extending into the substrate and a nucleation layer abutting the nucleation trench. Original
The microelectronic structure of claim 11, wherein the nucleation trench comprises a nucleation trench having (111) faceting. Original
The microelectronic structure of claim 11, wherein the nucleation layer comprises a material selected from the group consisting of indium phosphide, gallium phosphide, and gallium arsenide. Original
-23. Canceled
Canceled
An electronic system, comprising: a board; and a microelectronic device attached to the board, wherein the microelectronic device includes at least one microelectronic structure comprising: a substrate having a first surface; and an indium gallium arsenide active channel, wherein the indium gallium arsenide active channel comprises a fin having a pair of opposing surfaces that are substantially perpendicular to the first surface of the substrate, wherein each of the surfaces has an indium content higher than the average indium content of the indium gallium arsenide active channel, and wherein the indium content of the indium gallium arsenide active channel is graded between a higher indium content at each of the pair of opposing surfaces to a lower indium content at a center region between the pair of opposing surfaces. Currently amended
- 27. Canceled
Canceled
The electronic system of claim [[26]] 2 4, further including a sub- structure formed between the indium gallium arsenide active channel and the substrate, wherein the sub-structure abuts the indium gallium arsenide active channel. Currently amended
The electronic system of claim 28, wherein the sub-structure comprises a dopant and a material selected from the group consisting of indium gallium arsenide, indium arsenide, indium antimonide. Withdrawn
The electronic system of claim 28, wherein the sub-structure comprises a material selected from the group consisting of indium aluminum arsenide, indium phosphide, gallium phosphide, gallium arsenide, gallium arsenide antimonide, aluminum arsenide antimonide, indium aluminum gallium arsenide, indium aluminum gallium phosphide, and aluminum gallium arsenide. Previously presented
The electronic system of claim 26, further including an insulative buffer formed between the indium gallium arsenide active channel and the substrate. Withdrawn
The electronic system of claim 26, further including a nucleation trench extending into the substrate and a nucleation layer abutting the nucleation trench. Previously presented
The electronic system of claim 34, wherein the nucleation trench comprises a nucleation trench having (111) faceting. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
non-planar transistor microelectronic structure (fin-based)
electronic system with non-planar transistor microelectronic device
Materials described outside the worked examples.
indium gallium arsenide
InGaAs
silicon
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3). The sub-structure 144 may be formed 10 by any known formation process. In one embodiment of the present description, the sub- structure may be a high …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 300–650 °C | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,290,709Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1; however, it is understood that any appropriate number of fins 112 could be fabricated. In one embodiment, an etch mask (not shown) may be patterned on …
FIG. 2, a dielectric material may be deposited, by any appropriate deposition 25 process, over the substrate 102 and the fins 112, and the dielectric material …
FIG. 3). The sub-structure 144 may be formed 10 by any known formation process. In one embodiment of the present description, the sub- structure may be a high …
FIG. 4, a nucleation layer 142 may be formed in the nucleation trench 132. 5 The nucleation layer 142 may be formed by any formation process and may be any …
FIG. 5) and the thickness T a of the active channel 146 may be in the range, for example, of 500 to 5000 A, in accordance with some specific example …
FIG. 6, the portion 148 of the indium gallium arsenide active 5 channel 146 may be removed, such as by chemical mechanical planarization. As shown in
FIG. 7 with the higher indium concentration having darker shading. This indium distribution is graphically illustrated in
FIG. 8 with the x-axis being the distance from one indium rich surface 145 1 to the opposing indium rich surface 145 2 of the indium gallium arsenide active …
FIG. 9, the isolation structures 122 may be recessed, such as by an etching process, such that at least a portion of the indium gallium arsenide active channel …
FIG. 10) will result in high electron mobility and the electrostatics in terms of the ability to turn a transistor on and off will be better, i.e., faster …
FIG. 11, a gate spacer 156 may be deposited and patterned on the gate electrode 154 with well-known deposition and etching techniques. The gate spacer 156 may …
FIG. 12, the indium gallium arsenide active channel 146 may be formed on the sub-structure 144 within the trench 124 (see
FIG. 13, the portion 148 of the indium gallium arsenide active channel 146 may be removed, such as by chemical mechanical planarization. As shown in
FIG. 14 with the 5 indium having darker shading. This indium distribution is graphically illustrated in
FIG. 15 with the x-axis being the distance from one indium rich surface 145 1 to the opposing indium rich surface 145 2 of the indium gallium arsenide active …
FIG. 16, the isolation structures 122 may be recessed, such as by an etching process, such that at least a portion of the indium gallium arsenide active …
FIG. 17, at least one gate 150 may be form over the portion of the indium gallium arsenide active channel 146 extending above the isolation structures 122. The …
FIG. 18, a gate spacer 156 may be deposited and patterned on the gate electrode 154 with well-known 30 deposition and etching techniques. It is understood that …
FIG. 19. The sacrificial gate electrode 154 and the gate dielectric may be removed to expose the indium gallium arsenide active channel 146 between the …
FIG. 20 with only cross- sectioned structures shown). 15 As shown in
FIG. 22, the isolation structures 122 may be recessed within the exposed indium gallium arsenide active channel region 146, such as by etching, to expose a …
FIG. 23. 20 A dielectric material 166 may be deposited to fill the space lef t from the removal for the sub-structure 144 (see
FIG. 24, or to form a void 168, as shown in
FIG. 25. Thereaf t er, the remaining components of a transistor may be formed following a known processing flow, such as a t ri -gate processing flow, as will be …
FIG. 26, a gate oxide 25 layer 172 may be formed to surround the exposed active channel 146 and a gate electrode layer 174 may be formed to surround the gate …
FIG. 27 illustrates a computing device in accordance with one implementation of the present description. DESCRIPTION OF EMBODIMENTS 5 In the following detailed …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A microelectronic structure comprising: a substrate having a first surface: and an indium gallium arsenide active channel, wherein the indium gallium arsenide active channel comprises a fin having a pair of opposing surfaces that are substantially perpendicular to the first surface of the substrate, wherein each of the surfaces has an indium content higher than the average indium content of the indium gallium arsenide active channel, and wherein the indium content of the indium gallium arsenide active channel is graded between a higher indium content at each of the pair of opposing surfaces to a lower indium content at a center region between the pair of opposing surfaces. Currently amended
- 4. Canceled
Canceled
The microelectronic structure of claim [[3]] 1 L further including a sub- structure formed between the indium gallium arsenide active channel and the substrate, wherein the sub-structure abuts the indium gallium arsenide active channel. Currently amended
The microelectronic structure of claim 5, wherein the sub-structure comprises a dopant and a material selected from the group consisting of indium gallium arsenide, indium arsenide, indium antimonide. Withdrawn
The microelectronic structure of claim 5, wherein the sub-structure comprises a material selected from the group consisting of indium aluminum arsenide, indium phosphide, gallium phosphide, gallium arsenide, gallium arsenide antimonide, aluminum arsenide antimonide, indium aluminum gallium arsenide, indium aluminum gallium phosphide, and aluminum gallium arsenide. Original
The microelectronic structure of claim 3, further including an insulative buffer formed between the indium gallium arsenide active channel and the substrate. Withdrawn
The microelectronic structure of claim 3, further including a nucleation trench extending into the substrate and a nucleation layer abutting the nucleation trench. Original
The microelectronic structure of claim 11, wherein the nucleation trench comprises a nucleation trench having (111) faceting. Original
The microelectronic structure of claim 11, wherein the nucleation layer comprises a material selected from the group consisting of indium phosphide, gallium phosphide, and gallium arsenide. Original
-23. Canceled
Canceled
An electronic system, comprising: a board; and a microelectronic device attached to the board, wherein the microelectronic device includes at least one microelectronic structure comprising: a substrate having a first surface; and an indium gallium arsenide active channel, wherein the indium gallium arsenide active channel comprises a fin having a pair of opposing surfaces that are substantially perpendicular to the first surface of the substrate, wherein each of the surfaces has an indium content higher than the average indium content of the indium gallium arsenide active channel, and wherein the indium content of the indium gallium arsenide active channel is graded between a higher indium content at each of the pair of opposing surfaces to a lower indium content at a center region between the pair of opposing surfaces. Currently amended
- 27. Canceled
Canceled
The electronic system of claim [[26]] 2 4, further including a sub- structure formed between the indium gallium arsenide active channel and the substrate, wherein the sub-structure abuts the indium gallium arsenide active channel. Currently amended
The electronic system of claim 28, wherein the sub-structure comprises a dopant and a material selected from the group consisting of indium gallium arsenide, indium arsenide, indium antimonide. Withdrawn
The electronic system of claim 28, wherein the sub-structure comprises a material selected from the group consisting of indium aluminum arsenide, indium phosphide, gallium phosphide, gallium arsenide, gallium arsenide antimonide, aluminum arsenide antimonide, indium aluminum gallium arsenide, indium aluminum gallium phosphide, and aluminum gallium arsenide. Previously presented
The electronic system of claim 26, further including an insulative buffer formed between the indium gallium arsenide active channel and the substrate. Withdrawn
The electronic system of claim 26, further including a nucleation trench extending into the substrate and a nucleation layer abutting the nucleation trench. Previously presented
The electronic system of claim 34, wherein the nucleation trench comprises a nucleation trench having (111) faceting. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
non-planar transistor microelectronic structure (fin-based)
electronic system with non-planar transistor microelectronic device
Materials described outside the worked examples.
indium gallium arsenide
InGaAs
silicon
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3). The sub-structure 144 may be formed 10 by any known formation process. In one embodiment of the present description, the sub- structure may be a high …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 300–650 °C | — |
Temperature |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,290,709Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1; however, it is understood that any appropriate number of fins 112 could be fabricated. In one embodiment, an etch mask (not shown) may be patterned on …
FIG. 2, a dielectric material may be deposited, by any appropriate deposition 25 process, over the substrate 102 and the fins 112, and the dielectric material …
FIG. 3). The sub-structure 144 may be formed 10 by any known formation process. In one embodiment of the present description, the sub- structure may be a high …
FIG. 4, a nucleation layer 142 may be formed in the nucleation trench 132. 5 The nucleation layer 142 may be formed by any formation process and may be any …
FIG. 5) and the thickness T a of the active channel 146 may be in the range, for example, of 500 to 5000 A, in accordance with some specific example …
FIG. 6, the portion 148 of the indium gallium arsenide active 5 channel 146 may be removed, such as by chemical mechanical planarization. As shown in
FIG. 7 with the higher indium concentration having darker shading. This indium distribution is graphically illustrated in
FIG. 8 with the x-axis being the distance from one indium rich surface 145 1 to the opposing indium rich surface 145 2 of the indium gallium arsenide active …
FIG. 9, the isolation structures 122 may be recessed, such as by an etching process, such that at least a portion of the indium gallium arsenide active channel …
FIG. 10) will result in high electron mobility and the electrostatics in terms of the ability to turn a transistor on and off will be better, i.e., faster …
FIG. 11, a gate spacer 156 may be deposited and patterned on the gate electrode 154 with well-known deposition and etching techniques. The gate spacer 156 may …
FIG. 12, the indium gallium arsenide active channel 146 may be formed on the sub-structure 144 within the trench 124 (see
FIG. 13, the portion 148 of the indium gallium arsenide active channel 146 may be removed, such as by chemical mechanical planarization. As shown in
FIG. 14 with the 5 indium having darker shading. This indium distribution is graphically illustrated in
FIG. 15 with the x-axis being the distance from one indium rich surface 145 1 to the opposing indium rich surface 145 2 of the indium gallium arsenide active …
FIG. 16, the isolation structures 122 may be recessed, such as by an etching process, such that at least a portion of the indium gallium arsenide active …
FIG. 17, at least one gate 150 may be form over the portion of the indium gallium arsenide active channel 146 extending above the isolation structures 122. The …
FIG. 18, a gate spacer 156 may be deposited and patterned on the gate electrode 154 with well-known 30 deposition and etching techniques. It is understood that …
FIG. 19. The sacrificial gate electrode 154 and the gate dielectric may be removed to expose the indium gallium arsenide active channel 146 between the …
FIG. 20 with only cross- sectioned structures shown). 15 As shown in
FIG. 22, the isolation structures 122 may be recessed within the exposed indium gallium arsenide active channel region 146, such as by etching, to expose a …
FIG. 23. 20 A dielectric material 166 may be deposited to fill the space lef t from the removal for the sub-structure 144 (see
FIG. 24, or to form a void 168, as shown in
FIG. 25. Thereaf t er, the remaining components of a transistor may be formed following a known processing flow, such as a t ri -gate processing flow, as will be …
FIG. 26, a gate oxide 25 layer 172 may be formed to surround the exposed active channel 146 and a gate electrode layer 174 may be formed to surround the gate …
FIG. 27 illustrates a computing device in accordance with one implementation of the present description. DESCRIPTION OF EMBODIMENTS 5 In the following detailed …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A microelectronic structure comprising: a substrate having a first surface: and an indium gallium arsenide active channel, wherein the indium gallium arsenide active channel comprises a fin having a pair of opposing surfaces that are substantially perpendicular to the first surface of the substrate, wherein each of the surfaces has an indium content higher than the average indium content of the indium gallium arsenide active channel, and wherein the indium content of the indium gallium arsenide active channel is graded between a higher indium content at each of the pair of opposing surfaces to a lower indium content at a center region between the pair of opposing surfaces. Currently amended
- 4. Canceled
Canceled
The microelectronic structure of claim [[3]] 1 L further including a sub- structure formed between the indium gallium arsenide active channel and the substrate, wherein the sub-structure abuts the indium gallium arsenide active channel. Currently amended
The microelectronic structure of claim 5, wherein the sub-structure comprises a dopant and a material selected from the group consisting of indium gallium arsenide, indium arsenide, indium antimonide. Withdrawn
The microelectronic structure of claim 5, wherein the sub-structure comprises a material selected from the group consisting of indium aluminum arsenide, indium phosphide, gallium phosphide, gallium arsenide, gallium arsenide antimonide, aluminum arsenide antimonide, indium aluminum gallium arsenide, indium aluminum gallium phosphide, and aluminum gallium arsenide. Original
The microelectronic structure of claim 3, further including an insulative buffer formed between the indium gallium arsenide active channel and the substrate. Withdrawn
The microelectronic structure of claim 3, further including a nucleation trench extending into the substrate and a nucleation layer abutting the nucleation trench. Original
The microelectronic structure of claim 11, wherein the nucleation trench comprises a nucleation trench having (111) faceting. Original
The microelectronic structure of claim 11, wherein the nucleation layer comprises a material selected from the group consisting of indium phosphide, gallium phosphide, and gallium arsenide. Original
-23. Canceled
Canceled
An electronic system, comprising: a board; and a microelectronic device attached to the board, wherein the microelectronic device includes at least one microelectronic structure comprising: a substrate having a first surface; and an indium gallium arsenide active channel, wherein the indium gallium arsenide active channel comprises a fin having a pair of opposing surfaces that are substantially perpendicular to the first surface of the substrate, wherein each of the surfaces has an indium content higher than the average indium content of the indium gallium arsenide active channel, and wherein the indium content of the indium gallium arsenide active channel is graded between a higher indium content at each of the pair of opposing surfaces to a lower indium content at a center region between the pair of opposing surfaces. Currently amended
- 27. Canceled
Canceled
The electronic system of claim [[26]] 2 4, further including a sub- structure formed between the indium gallium arsenide active channel and the substrate, wherein the sub-structure abuts the indium gallium arsenide active channel. Currently amended
The electronic system of claim 28, wherein the sub-structure comprises a dopant and a material selected from the group consisting of indium gallium arsenide, indium arsenide, indium antimonide. Withdrawn
The electronic system of claim 28, wherein the sub-structure comprises a material selected from the group consisting of indium aluminum arsenide, indium phosphide, gallium phosphide, gallium arsenide, gallium arsenide antimonide, aluminum arsenide antimonide, indium aluminum gallium arsenide, indium aluminum gallium phosphide, and aluminum gallium arsenide. Previously presented
The electronic system of claim 26, further including an insulative buffer formed between the indium gallium arsenide active channel and the substrate. Withdrawn
The electronic system of claim 26, further including a nucleation trench extending into the substrate and a nucleation layer abutting the nucleation trench. Previously presented
The electronic system of claim 34, wherein the nucleation trench comprises a nucleation trench having (111) faceting. Previously presented
Layer stacks claimed or described, ordered top of device to substrate.
non-planar transistor microelectronic structure (fin-based)
electronic system with non-planar transistor microelectronic device
Materials described outside the worked examples.
indium gallium arsenide
InGaAs
silicon
Si
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3). The sub-structure 144 may be formed 10 by any known formation process. In one embodiment of the present description, the sub- structure may be a high …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Temperature | 300–650 °C | — |
Temperature |
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FIG. 5) and the thickness T a of the active channel 146 may be in the range, for example, of 500 to 5000 A, in accordance with some specific example …
FIG. 10) will result in high electron mobility and the electrostatics in terms of the ability to turn a transistor on and off will be better, i.e., faster …
FIG. 25. Thereaf t er, the remaining components of a transistor may be formed following a known processing flow, such as a t ri -gate processing flow, as will be …
FIG. 26, a gate oxide 25 layer 172 may be formed to surround the exposed active channel 146 and a gate electrode layer 174 may be formed to surround the gate …
| 400–600 °C |
| — |
Flow Rate | 10–300 sccm | — |
Flow Rate | 100–1000 sccm | — |
Temperature | 400–500 °C | — |
Flow Rate | 10–100 sccm | — |
Pressure | 1–760 Torr | — |
Flow Rate | ≤ 1 sccm | — |
Thickness | ≤ 25 nm | — |
Flow Rate | ≥ 1 sccm | — |
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indium aluminum arsenide
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FIG. 5) and the thickness T a of the active channel 146 may be in the range, for example, of 500 to 5000 A, in accordance with some specific example …
FIG. 10) will result in high electron mobility and the electrostatics in terms of the ability to turn a transistor on and off will be better, i.e., faster …
FIG. 25. Thereaf t er, the remaining components of a transistor may be formed following a known processing flow, such as a t ri -gate processing flow, as will be …
FIG. 26, a gate oxide 25 layer 172 may be formed to surround the exposed active channel 146 and a gate electrode layer 174 may be formed to surround the gate …
| 400–600 °C |
| — |
Flow Rate | 10–300 sccm | — |
Flow Rate | 100–1000 sccm | — |
Temperature | 400–500 °C | — |
Flow Rate | 10–100 sccm | — |
Pressure | 1–760 Torr | — |
Flow Rate | ≤ 1 sccm | — |
Thickness | ≤ 25 nm | — |
Flow Rate | ≥ 1 sccm | — |
indium arsenide
InAs
indium antimonide
InSb
indium aluminum arsenide
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indium phosphide
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gallium phosphide
GaP
gallium arsenide
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gallium arsenide antimonide
GaAsSb
aluminum arsenide antimonide
AlAsSb
indium aluminum gallium arsenide
InAlGaAs
indium aluminum gallium phosphide
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aluminum gallium arsenide
AlGaAs
silicon oxide
SiO₂
FIG. 5) and the thickness T a of the active channel 146 may be in the range, for example, of 500 to 5000 A, in accordance with some specific example …
FIG. 10) will result in high electron mobility and the electrostatics in terms of the ability to turn a transistor on and off will be better, i.e., faster …
FIG. 25. Thereaf t er, the remaining components of a transistor may be formed following a known processing flow, such as a t ri -gate processing flow, as will be …
FIG. 26, a gate oxide 25 layer 172 may be formed to surround the exposed active channel 146 and a gate electrode layer 174 may be formed to surround the gate …
| 400–600 °C |
| — |
Flow Rate | 10–300 sccm | — |
Flow Rate | 100–1000 sccm | — |
Temperature | 400–500 °C | — |
Flow Rate | 10–100 sccm | — |
Pressure | 1–760 Torr | — |
Flow Rate | ≤ 1 sccm | — |
Thickness | ≤ 25 nm | — |
Flow Rate | ≥ 1 sccm | — |
indium arsenide
InAs
indium antimonide
InSb
indium aluminum arsenide
InAlAs
indium phosphide
InP
gallium phosphide
GaP
gallium arsenide
GaAs
gallium arsenide antimonide
GaAsSb
aluminum arsenide antimonide
AlAsSb
indium aluminum gallium arsenide
InAlGaAs
indium aluminum gallium phosphide
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aluminum gallium arsenide
AlGaAs
silicon oxide
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FIG. 5) and the thickness T a of the active channel 146 may be in the range, for example, of 500 to 5000 A, in accordance with some specific example …
FIG. 10) will result in high electron mobility and the electrostatics in terms of the ability to turn a transistor on and off will be better, i.e., faster …
FIG. 25. Thereaf t er, the remaining components of a transistor may be formed following a known processing flow, such as a t ri -gate processing flow, as will be …
FIG. 26, a gate oxide 25 layer 172 may be formed to surround the exposed active channel 146 and a gate electrode layer 174 may be formed to surround the gate …
| 400–600 °C |
| — |
Flow Rate | 10–300 sccm | — |
Flow Rate | 100–1000 sccm | — |
Temperature | 400–500 °C | — |
Flow Rate | 10–100 sccm | — |
Pressure | 1–760 Torr | — |
Flow Rate | ≤ 1 sccm | — |
Thickness | ≤ 25 nm | — |
Flow Rate | ≥ 1 sccm | — |