Patent
US 9,852,903SYSTEM AND METHOD IN INDIUM-GALLIUM-ARSENIDE CHANNEL HEIGHT CONTROL FOR SUB 7NM FINFET
CHUN YAN, XINYU BAO
US
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Patent
Atlas literature
Patent
US 9,852,903Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a schematic, cross-sectional view of a plasma processing chamber within which embodiments of the disclosure may be performed.
Figure 2 illustrates a schematic top view of a cluster tool within which embodiments of the disclosure may be performed.
Figure 3 illustrates operations of a method according to embodiments disclosed herein.
Figures 4A-4F illustrate a partial, cross-sectional view of a transistor at various stages of fabrication according to embodiments disclosed herein. [0014] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
6.083226 (PATENT)
Layer stacks claimed or described, ordered top of device to substrate.
FinFET/TFET with group III-V semiconductor channel
Materials described outside the worked examples.
group III-V semiconductor (InGaAs)
indium gallium arsenide
InGaAs
oxide layer (group III-V native oxide)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figures 4A-4F illustrate a partial, cross-sectional view of a transistor at various stages of fabrication according to embodiments disclosed herein. [0014] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
— | ≤ 50 eV | — |
— |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,852,903Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a schematic, cross-sectional view of a plasma processing chamber within which embodiments of the disclosure may be performed.
Figure 2 illustrates a schematic top view of a cluster tool within which embodiments of the disclosure may be performed.
Figure 3 illustrates operations of a method according to embodiments disclosed herein.
Figures 4A-4F illustrate a partial, cross-sectional view of a transistor at various stages of fabrication according to embodiments disclosed herein. [0014] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
6.083226 (PATENT)
Layer stacks claimed or described, ordered top of device to substrate.
FinFET/TFET with group III-V semiconductor channel
Materials described outside the worked examples.
group III-V semiconductor (InGaAs)
indium gallium arsenide
InGaAs
oxide layer (group III-V native oxide)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figures 4A-4F illustrate a partial, cross-sectional view of a transistor at various stages of fabrication according to embodiments disclosed herein. [0014] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
— | ≤ 50 eV | — |
— |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,852,903Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a schematic, cross-sectional view of a plasma processing chamber within which embodiments of the disclosure may be performed.
Figure 2 illustrates a schematic top view of a cluster tool within which embodiments of the disclosure may be performed.
Figure 3 illustrates operations of a method according to embodiments disclosed herein.
Figures 4A-4F illustrate a partial, cross-sectional view of a transistor at various stages of fabrication according to embodiments disclosed herein. [0014] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
6.083226 (PATENT)
Layer stacks claimed or described, ordered top of device to substrate.
FinFET/TFET with group III-V semiconductor channel
Materials described outside the worked examples.
group III-V semiconductor (InGaAs)
indium gallium arsenide
InGaAs
oxide layer (group III-V native oxide)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figures 4A-4F illustrate a partial, cross-sectional view of a transistor at various stages of fabrication according to embodiments disclosed herein. [0014] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
— | ≤ 50 eV | — |
— |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,852,903Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 illustrates a schematic, cross-sectional view of a plasma processing chamber within which embodiments of the disclosure may be performed.
Figure 2 illustrates a schematic top view of a cluster tool within which embodiments of the disclosure may be performed.
Figure 3 illustrates operations of a method according to embodiments disclosed herein.
Figures 4A-4F illustrate a partial, cross-sectional view of a transistor at various stages of fabrication according to embodiments disclosed herein. [0014] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
6.083226 (PATENT)
Layer stacks claimed or described, ordered top of device to substrate.
FinFET/TFET with group III-V semiconductor channel
Materials described outside the worked examples.
group III-V semiconductor (InGaAs)
indium gallium arsenide
InGaAs
oxide layer (group III-V native oxide)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figures 4A-4F illustrate a partial, cross-sectional view of a transistor at various stages of fabrication according to embodiments disclosed herein. [0014] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
— | ≤ 50 eV | — |
— |
Related documents with shared materials, methods, properties, or citations.
evaporable layer
| — |
Thickness | ≤ 7 nm | — |
evaporable layer
| — |
Thickness | ≤ 7 nm | — |
evaporable layer
| — |
Thickness | ≤ 7 nm | — |
evaporable layer
| — |
Thickness | ≤ 7 nm | — |