Patent
US 9,666,508GALLIUM ARSENIDE DEVICES WITH COPPER BACKSIDE FOR DIRECT DIE SOLDER ATTACH
Hong Shen
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,666,508Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows an example of attaching a singulated GaAs die to a die attach pad on a substrate.
Figures 2A-2B show an example sequence of attaching a GaAs die to a substrate using standard processes.
Figures 3A-3B show an example sequence of attaching a GaAs die to a substrate using a direct die solder process.
Figure 4 shows an example sequence of wafer processing for forming singulated GaAs dies for attachment to a substrate.
Figures 5A-5R show examples of structures at various stages of the processing sequence of
Figure 6 is a block diagram representing the copper metallization process according to various aspects of the present invention.
Figures 7A-7 D show examples of structures at various stages of the processing sequence of
Figure 8 is a schematic drawing of solder die attach of GaAs dies according to one embodiment -6-
Figure 9A is a cross-sectional view of a GaAs die with solder die attach according to one embodiment.
Figure 9B is a cross-sectional view of a GaAs die with epoxy die attach.
Figure 10 shows a comparison of maximum operating temperatures between solder die attach according to one embodiment and epoxy die attach.
Figure 11 shows a comparison of thermal resistance between solder die attach according to one embodiment and epoxy die attach.
Figure 12 shows failure of a traditional GaAs device with conventional NiV barrier layer and gold finish due to Cu-Sn intermetallic compound formation.
Figure 13 is a block diagram representing the direct die solder process according to various aspects of the present invention.
Figures 14A-14 C show examples of structures at various stages of the processing sequence of
Figure 15 shows an electrical comparison between solder die attach according to one embodiment and an epoxy die attach.
Figure 16 shows a cross-section of a Ni-plated through wafer via.
Figure 17 shows a cross-section of a Ni-plated through wafer via.
Figures 18A-18D show an example sequence of singulating a GaAs integrated circuit die from a wafer.
Figure 19 shows an example sequence of ball grid array packaging of singulated GaAs integrated circuit dies, according to one embodiment.
Figures 20A-20H show examples of structures at various stages of the processing sequence of
Figure 21 shows an example shows an example sequence of land grid array packaging of singulated GaAs integrated circuit dies, according to one embodiment.
Figures 22A-22G show examples of structures at various stages of the processing sequence of
Figure 23 shows an example shows an example sequence of leadframe packaging of singulated GaAs integrated circuit dies, according to one embodiment.
Figures 24A-24D show examples of structures at various stages of the processing sequence of
Figures 25A-25E show examples of structures at various stages of the processing sequence of
Figure 26 illustrates a GaAs integrated circuit device made according to various methods of the present invention, mounted onto a printed circuit board.
Figure 27 illustrates an electronic device incorporating a GaAs integrated circuit device made according to various methods of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
A gallium-arsenide (GaAs) device comprising: a GaAs wafer having a catalyzed copper backside contact pad; a die attach pad, the die attach pad and the GaAs wafer having approximately the same footprint; a solder layer disposed between the catalyzed copper backside contact pad and the die attach pad, the solder layer configured to connect the GaAs wafer and the die attach pad; and a nickel-plated barrier layer disposed between the catalyzed copper backside contact pad and the solder layer.
The GaAs device of claim 2 wherein the GaAs wafer self-aligns with the die attach pad after reflow of the solder layer.
The GaAs device of claim 2 wherein the copper backside contact pad is catalyzed with palladium.
The GaAs device of claim 2 wherein the copper backside contact pad is catalyzed with dimethyl amine borane.
The GaAs device of claim 2 wherein the copper backside contact pad is catalyzed with both palladium and dimethyl amine borane.
The GaAs device of claim 2 wherein the GaAs wafer has a thickness of between 50-150 pm.
The GaAs device of claim 2 wherein the catalyzed copper backside contact pad has a thermal conductivity of approximately 4 W/c mK.
The GaAs device of claim 2 wherein a size of the die attach pad does not exceed a size of the GaAs wafer by more than 150 microns in at least one direction. -2- Application No.: 15/352240 Filing Date:
The GaAs device of claim 2 wherein the die attach pad is located on a substrate.
A method for manufacturing a gallium-arsenide (GaAs) device, the method comprising: preparing a GaAs wafer having a copper backside contact pad; catalyzing the copper backside contact pad; applying a nickel barrier layer onto the catalyzed copper backside pad; preparing a die attach pad having approximately the same footprint as the GaAs wafer; and soldering the catalyzed copper backside contact pad to the die attach pad.
The method of claim 12 wherein the applying is electroless nickel plating.
The method of claim 12 wherein the nickel barrier layer is applied by sputtering or nickel flash.
The method of claim 12 wherein the catalyzing is performed prior to the plating.
The method of claim 12 wherein the die attach pad is connected to a substrate.
The method of claim 12 wherein a size of the die attach pad does not exceed a size of the GaAs wafer by more than 150 microns in at least one direction.
A packaged gallium-arsenide (GaAs) integrated circuit comprising: a printed circuit board; a die attach pad connected to the printed circuit board; -3- Application No.: 15/352240 Filing Date: a GaAs wafer having a catalyzed copper backside contact pad, the GaAs wafer having approximately the same footprint as the die attach pad; a solder layer disposed between the catalyzed copper backside contact pad and the die attach pad, the solder layer configured to connect the GaAs wafer and the die attach pad; and a nickel-plated barrier layer disposed between the catalyzed copper backside contact pad and the solder layer.
The packaged GaAs integrated circuit of claim 18 wherein a size of the die attach pad does not exceed a size of the GaAs wafer by more than 150 microns in at least one direction.
The packaged GaAs integrated circuit of claim 18 wherein the copper backside contact pad is catalyzed with both palladium and dimethyl amine borane.
The packaged GaAs integrated circuit of claim 18 wherein the catalyzed copper backside contact pad has a thermal conductivity of approximately 4 W/cmK. -4-
Layer stacks claimed or described, ordered top of device to substrate.
GaAs device with copper backside direct die solder attach
packaged GaAs integrated circuit on printed circuit board
Materials described outside the worked examples.
catalyzed copper backside contact pad
Cu
solder layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 15 shows an electrical comparison between solder die attach according to one embodiment and an epoxy die attach.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thermal Conductivity | 4 W/cmK | Cu |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,666,508Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows an example of attaching a singulated GaAs die to a die attach pad on a substrate.
Figures 2A-2B show an example sequence of attaching a GaAs die to a substrate using standard processes.
Figures 3A-3B show an example sequence of attaching a GaAs die to a substrate using a direct die solder process.
Figure 4 shows an example sequence of wafer processing for forming singulated GaAs dies for attachment to a substrate.
Figures 5A-5R show examples of structures at various stages of the processing sequence of
Figure 6 is a block diagram representing the copper metallization process according to various aspects of the present invention.
Figures 7A-7 D show examples of structures at various stages of the processing sequence of
Figure 8 is a schematic drawing of solder die attach of GaAs dies according to one embodiment -6-
Figure 9A is a cross-sectional view of a GaAs die with solder die attach according to one embodiment.
Figure 9B is a cross-sectional view of a GaAs die with epoxy die attach.
Figure 10 shows a comparison of maximum operating temperatures between solder die attach according to one embodiment and epoxy die attach.
Figure 11 shows a comparison of thermal resistance between solder die attach according to one embodiment and epoxy die attach.
Figure 12 shows failure of a traditional GaAs device with conventional NiV barrier layer and gold finish due to Cu-Sn intermetallic compound formation.
Figure 13 is a block diagram representing the direct die solder process according to various aspects of the present invention.
Figures 14A-14 C show examples of structures at various stages of the processing sequence of
Figure 15 shows an electrical comparison between solder die attach according to one embodiment and an epoxy die attach.
Figure 16 shows a cross-section of a Ni-plated through wafer via.
Figure 17 shows a cross-section of a Ni-plated through wafer via.
Figures 18A-18D show an example sequence of singulating a GaAs integrated circuit die from a wafer.
Figure 19 shows an example sequence of ball grid array packaging of singulated GaAs integrated circuit dies, according to one embodiment.
Figures 20A-20H show examples of structures at various stages of the processing sequence of
Figure 21 shows an example shows an example sequence of land grid array packaging of singulated GaAs integrated circuit dies, according to one embodiment.
Figures 22A-22G show examples of structures at various stages of the processing sequence of
Figure 23 shows an example shows an example sequence of leadframe packaging of singulated GaAs integrated circuit dies, according to one embodiment.
Figures 24A-24D show examples of structures at various stages of the processing sequence of
Figures 25A-25E show examples of structures at various stages of the processing sequence of
Figure 26 illustrates a GaAs integrated circuit device made according to various methods of the present invention, mounted onto a printed circuit board.
Figure 27 illustrates an electronic device incorporating a GaAs integrated circuit device made according to various methods of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
A gallium-arsenide (GaAs) device comprising: a GaAs wafer having a catalyzed copper backside contact pad; a die attach pad, the die attach pad and the GaAs wafer having approximately the same footprint; a solder layer disposed between the catalyzed copper backside contact pad and the die attach pad, the solder layer configured to connect the GaAs wafer and the die attach pad; and a nickel-plated barrier layer disposed between the catalyzed copper backside contact pad and the solder layer.
The GaAs device of claim 2 wherein the GaAs wafer self-aligns with the die attach pad after reflow of the solder layer.
The GaAs device of claim 2 wherein the copper backside contact pad is catalyzed with palladium.
The GaAs device of claim 2 wherein the copper backside contact pad is catalyzed with dimethyl amine borane.
The GaAs device of claim 2 wherein the copper backside contact pad is catalyzed with both palladium and dimethyl amine borane.
The GaAs device of claim 2 wherein the GaAs wafer has a thickness of between 50-150 pm.
The GaAs device of claim 2 wherein the catalyzed copper backside contact pad has a thermal conductivity of approximately 4 W/c mK.
The GaAs device of claim 2 wherein a size of the die attach pad does not exceed a size of the GaAs wafer by more than 150 microns in at least one direction. -2- Application No.: 15/352240 Filing Date:
The GaAs device of claim 2 wherein the die attach pad is located on a substrate.
A method for manufacturing a gallium-arsenide (GaAs) device, the method comprising: preparing a GaAs wafer having a copper backside contact pad; catalyzing the copper backside contact pad; applying a nickel barrier layer onto the catalyzed copper backside pad; preparing a die attach pad having approximately the same footprint as the GaAs wafer; and soldering the catalyzed copper backside contact pad to the die attach pad.
The method of claim 12 wherein the applying is electroless nickel plating.
The method of claim 12 wherein the nickel barrier layer is applied by sputtering or nickel flash.
The method of claim 12 wherein the catalyzing is performed prior to the plating.
The method of claim 12 wherein the die attach pad is connected to a substrate.
The method of claim 12 wherein a size of the die attach pad does not exceed a size of the GaAs wafer by more than 150 microns in at least one direction.
A packaged gallium-arsenide (GaAs) integrated circuit comprising: a printed circuit board; a die attach pad connected to the printed circuit board; -3- Application No.: 15/352240 Filing Date: a GaAs wafer having a catalyzed copper backside contact pad, the GaAs wafer having approximately the same footprint as the die attach pad; a solder layer disposed between the catalyzed copper backside contact pad and the die attach pad, the solder layer configured to connect the GaAs wafer and the die attach pad; and a nickel-plated barrier layer disposed between the catalyzed copper backside contact pad and the solder layer.
The packaged GaAs integrated circuit of claim 18 wherein a size of the die attach pad does not exceed a size of the GaAs wafer by more than 150 microns in at least one direction.
The packaged GaAs integrated circuit of claim 18 wherein the copper backside contact pad is catalyzed with both palladium and dimethyl amine borane.
The packaged GaAs integrated circuit of claim 18 wherein the catalyzed copper backside contact pad has a thermal conductivity of approximately 4 W/cmK. -4-
Layer stacks claimed or described, ordered top of device to substrate.
GaAs device with copper backside direct die solder attach
packaged GaAs integrated circuit on printed circuit board
Materials described outside the worked examples.
catalyzed copper backside contact pad
Cu
solder layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 15 shows an electrical comparison between solder die attach according to one embodiment and an epoxy die attach.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thermal Conductivity | 4 W/cmK | Cu |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,666,508Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows an example of attaching a singulated GaAs die to a die attach pad on a substrate.
Figures 2A-2B show an example sequence of attaching a GaAs die to a substrate using standard processes.
Figures 3A-3B show an example sequence of attaching a GaAs die to a substrate using a direct die solder process.
Figure 4 shows an example sequence of wafer processing for forming singulated GaAs dies for attachment to a substrate.
Figures 5A-5R show examples of structures at various stages of the processing sequence of
Figure 6 is a block diagram representing the copper metallization process according to various aspects of the present invention.
Figures 7A-7 D show examples of structures at various stages of the processing sequence of
Figure 8 is a schematic drawing of solder die attach of GaAs dies according to one embodiment -6-
Figure 9A is a cross-sectional view of a GaAs die with solder die attach according to one embodiment.
Figure 9B is a cross-sectional view of a GaAs die with epoxy die attach.
Figure 10 shows a comparison of maximum operating temperatures between solder die attach according to one embodiment and epoxy die attach.
Figure 11 shows a comparison of thermal resistance between solder die attach according to one embodiment and epoxy die attach.
Figure 12 shows failure of a traditional GaAs device with conventional NiV barrier layer and gold finish due to Cu-Sn intermetallic compound formation.
Figure 13 is a block diagram representing the direct die solder process according to various aspects of the present invention.
Figures 14A-14 C show examples of structures at various stages of the processing sequence of
Figure 15 shows an electrical comparison between solder die attach according to one embodiment and an epoxy die attach.
Figure 16 shows a cross-section of a Ni-plated through wafer via.
Figure 17 shows a cross-section of a Ni-plated through wafer via.
Figures 18A-18D show an example sequence of singulating a GaAs integrated circuit die from a wafer.
Figure 19 shows an example sequence of ball grid array packaging of singulated GaAs integrated circuit dies, according to one embodiment.
Figures 20A-20H show examples of structures at various stages of the processing sequence of
Figure 21 shows an example shows an example sequence of land grid array packaging of singulated GaAs integrated circuit dies, according to one embodiment.
Figures 22A-22G show examples of structures at various stages of the processing sequence of
Figure 23 shows an example shows an example sequence of leadframe packaging of singulated GaAs integrated circuit dies, according to one embodiment.
Figures 24A-24D show examples of structures at various stages of the processing sequence of
Figures 25A-25E show examples of structures at various stages of the processing sequence of
Figure 26 illustrates a GaAs integrated circuit device made according to various methods of the present invention, mounted onto a printed circuit board.
Figure 27 illustrates an electronic device incorporating a GaAs integrated circuit device made according to various methods of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
A gallium-arsenide (GaAs) device comprising: a GaAs wafer having a catalyzed copper backside contact pad; a die attach pad, the die attach pad and the GaAs wafer having approximately the same footprint; a solder layer disposed between the catalyzed copper backside contact pad and the die attach pad, the solder layer configured to connect the GaAs wafer and the die attach pad; and a nickel-plated barrier layer disposed between the catalyzed copper backside contact pad and the solder layer.
The GaAs device of claim 2 wherein the GaAs wafer self-aligns with the die attach pad after reflow of the solder layer.
The GaAs device of claim 2 wherein the copper backside contact pad is catalyzed with palladium.
The GaAs device of claim 2 wherein the copper backside contact pad is catalyzed with dimethyl amine borane.
The GaAs device of claim 2 wherein the copper backside contact pad is catalyzed with both palladium and dimethyl amine borane.
The GaAs device of claim 2 wherein the GaAs wafer has a thickness of between 50-150 pm.
The GaAs device of claim 2 wherein the catalyzed copper backside contact pad has a thermal conductivity of approximately 4 W/c mK.
The GaAs device of claim 2 wherein a size of the die attach pad does not exceed a size of the GaAs wafer by more than 150 microns in at least one direction. -2- Application No.: 15/352240 Filing Date:
The GaAs device of claim 2 wherein the die attach pad is located on a substrate.
A method for manufacturing a gallium-arsenide (GaAs) device, the method comprising: preparing a GaAs wafer having a copper backside contact pad; catalyzing the copper backside contact pad; applying a nickel barrier layer onto the catalyzed copper backside pad; preparing a die attach pad having approximately the same footprint as the GaAs wafer; and soldering the catalyzed copper backside contact pad to the die attach pad.
The method of claim 12 wherein the applying is electroless nickel plating.
The method of claim 12 wherein the nickel barrier layer is applied by sputtering or nickel flash.
The method of claim 12 wherein the catalyzing is performed prior to the plating.
The method of claim 12 wherein the die attach pad is connected to a substrate.
The method of claim 12 wherein a size of the die attach pad does not exceed a size of the GaAs wafer by more than 150 microns in at least one direction.
A packaged gallium-arsenide (GaAs) integrated circuit comprising: a printed circuit board; a die attach pad connected to the printed circuit board; -3- Application No.: 15/352240 Filing Date: a GaAs wafer having a catalyzed copper backside contact pad, the GaAs wafer having approximately the same footprint as the die attach pad; a solder layer disposed between the catalyzed copper backside contact pad and the die attach pad, the solder layer configured to connect the GaAs wafer and the die attach pad; and a nickel-plated barrier layer disposed between the catalyzed copper backside contact pad and the solder layer.
The packaged GaAs integrated circuit of claim 18 wherein a size of the die attach pad does not exceed a size of the GaAs wafer by more than 150 microns in at least one direction.
The packaged GaAs integrated circuit of claim 18 wherein the copper backside contact pad is catalyzed with both palladium and dimethyl amine borane.
The packaged GaAs integrated circuit of claim 18 wherein the catalyzed copper backside contact pad has a thermal conductivity of approximately 4 W/cmK. -4-
Layer stacks claimed or described, ordered top of device to substrate.
GaAs device with copper backside direct die solder attach
packaged GaAs integrated circuit on printed circuit board
Materials described outside the worked examples.
catalyzed copper backside contact pad
Cu
solder layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 15 shows an electrical comparison between solder die attach according to one embodiment and an epoxy die attach.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thermal Conductivity | 4 W/cmK | Cu |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,666,508Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows an example of attaching a singulated GaAs die to a die attach pad on a substrate.
Figures 2A-2B show an example sequence of attaching a GaAs die to a substrate using standard processes.
Figures 3A-3B show an example sequence of attaching a GaAs die to a substrate using a direct die solder process.
Figure 4 shows an example sequence of wafer processing for forming singulated GaAs dies for attachment to a substrate.
Figures 5A-5R show examples of structures at various stages of the processing sequence of
Figure 6 is a block diagram representing the copper metallization process according to various aspects of the present invention.
Figures 7A-7 D show examples of structures at various stages of the processing sequence of
Figure 8 is a schematic drawing of solder die attach of GaAs dies according to one embodiment -6-
Figure 9A is a cross-sectional view of a GaAs die with solder die attach according to one embodiment.
Figure 9B is a cross-sectional view of a GaAs die with epoxy die attach.
Figure 10 shows a comparison of maximum operating temperatures between solder die attach according to one embodiment and epoxy die attach.
Figure 11 shows a comparison of thermal resistance between solder die attach according to one embodiment and epoxy die attach.
Figure 12 shows failure of a traditional GaAs device with conventional NiV barrier layer and gold finish due to Cu-Sn intermetallic compound formation.
Figure 13 is a block diagram representing the direct die solder process according to various aspects of the present invention.
Figures 14A-14 C show examples of structures at various stages of the processing sequence of
Figure 15 shows an electrical comparison between solder die attach according to one embodiment and an epoxy die attach.
Figure 16 shows a cross-section of a Ni-plated through wafer via.
Figure 17 shows a cross-section of a Ni-plated through wafer via.
Figures 18A-18D show an example sequence of singulating a GaAs integrated circuit die from a wafer.
Figure 19 shows an example sequence of ball grid array packaging of singulated GaAs integrated circuit dies, according to one embodiment.
Figures 20A-20H show examples of structures at various stages of the processing sequence of
Figure 21 shows an example shows an example sequence of land grid array packaging of singulated GaAs integrated circuit dies, according to one embodiment.
Figures 22A-22G show examples of structures at various stages of the processing sequence of
Figure 23 shows an example shows an example sequence of leadframe packaging of singulated GaAs integrated circuit dies, according to one embodiment.
Figures 24A-24D show examples of structures at various stages of the processing sequence of
Figures 25A-25E show examples of structures at various stages of the processing sequence of
Figure 26 illustrates a GaAs integrated circuit device made according to various methods of the present invention, mounted onto a printed circuit board.
Figure 27 illustrates an electronic device incorporating a GaAs integrated circuit device made according to various methods of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
canceled
A gallium-arsenide (GaAs) device comprising: a GaAs wafer having a catalyzed copper backside contact pad; a die attach pad, the die attach pad and the GaAs wafer having approximately the same footprint; a solder layer disposed between the catalyzed copper backside contact pad and the die attach pad, the solder layer configured to connect the GaAs wafer and the die attach pad; and a nickel-plated barrier layer disposed between the catalyzed copper backside contact pad and the solder layer.
The GaAs device of claim 2 wherein the GaAs wafer self-aligns with the die attach pad after reflow of the solder layer.
The GaAs device of claim 2 wherein the copper backside contact pad is catalyzed with palladium.
The GaAs device of claim 2 wherein the copper backside contact pad is catalyzed with dimethyl amine borane.
The GaAs device of claim 2 wherein the copper backside contact pad is catalyzed with both palladium and dimethyl amine borane.
The GaAs device of claim 2 wherein the GaAs wafer has a thickness of between 50-150 pm.
The GaAs device of claim 2 wherein the catalyzed copper backside contact pad has a thermal conductivity of approximately 4 W/c mK.
The GaAs device of claim 2 wherein a size of the die attach pad does not exceed a size of the GaAs wafer by more than 150 microns in at least one direction. -2- Application No.: 15/352240 Filing Date:
The GaAs device of claim 2 wherein the die attach pad is located on a substrate.
A method for manufacturing a gallium-arsenide (GaAs) device, the method comprising: preparing a GaAs wafer having a copper backside contact pad; catalyzing the copper backside contact pad; applying a nickel barrier layer onto the catalyzed copper backside pad; preparing a die attach pad having approximately the same footprint as the GaAs wafer; and soldering the catalyzed copper backside contact pad to the die attach pad.
The method of claim 12 wherein the applying is electroless nickel plating.
The method of claim 12 wherein the nickel barrier layer is applied by sputtering or nickel flash.
The method of claim 12 wherein the catalyzing is performed prior to the plating.
The method of claim 12 wherein the die attach pad is connected to a substrate.
The method of claim 12 wherein a size of the die attach pad does not exceed a size of the GaAs wafer by more than 150 microns in at least one direction.
A packaged gallium-arsenide (GaAs) integrated circuit comprising: a printed circuit board; a die attach pad connected to the printed circuit board; -3- Application No.: 15/352240 Filing Date: a GaAs wafer having a catalyzed copper backside contact pad, the GaAs wafer having approximately the same footprint as the die attach pad; a solder layer disposed between the catalyzed copper backside contact pad and the die attach pad, the solder layer configured to connect the GaAs wafer and the die attach pad; and a nickel-plated barrier layer disposed between the catalyzed copper backside contact pad and the solder layer.
The packaged GaAs integrated circuit of claim 18 wherein a size of the die attach pad does not exceed a size of the GaAs wafer by more than 150 microns in at least one direction.
The packaged GaAs integrated circuit of claim 18 wherein the copper backside contact pad is catalyzed with both palladium and dimethyl amine borane.
The packaged GaAs integrated circuit of claim 18 wherein the catalyzed copper backside contact pad has a thermal conductivity of approximately 4 W/cmK. -4-
Layer stacks claimed or described, ordered top of device to substrate.
GaAs device with copper backside direct die solder attach
packaged GaAs integrated circuit on printed circuit board
Materials described outside the worked examples.
catalyzed copper backside contact pad
Cu
solder layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
Figure 15 shows an electrical comparison between solder die attach according to one embodiment and an epoxy die attach.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thermal Conductivity | 4 W/cmK | Cu |
Related documents with shared materials, methods, properties, or citations.
nickel-plated barrier layer
Ni
GaAs wafer
GaAs
palladium catalyst
Pd
dimethyl amine borane
| 100–900 Å |
| — |
Temperature | 0–260 °C | — |
Temperature | 51-5K | — |
Thickness | ≥ 150 µm | — |
Temperature | ≥ 135 °C | — |
nickel-plated barrier layer
Ni
GaAs wafer
GaAs
palladium catalyst
Pd
dimethyl amine borane
| 100–900 Å |
| — |
Temperature | 0–260 °C | — |
Temperature | 51-5K | — |
Thickness | ≥ 150 µm | — |
Temperature | ≥ 135 °C | — |
nickel-plated barrier layer
Ni
GaAs wafer
GaAs
palladium catalyst
Pd
dimethyl amine borane
| 100–900 Å |
| — |
Temperature | 0–260 °C | — |
Temperature | 51-5K | — |
Thickness | ≥ 150 µm | — |
Temperature | ≥ 135 °C | — |
nickel-plated barrier layer
Ni
GaAs wafer
GaAs
palladium catalyst
Pd
dimethyl amine borane
| 100–900 Å |
| — |
Temperature | 0–260 °C | — |
Temperature | 51-5K | — |
Thickness | ≥ 150 µm | — |
Temperature | ≥ 135 °C | — |