Patent
US 9,231,068METHODS OF STRESS BALANCING IN GALLIUM ARSENIDE WAFER PROCESSING
Hong Shen
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,231,068Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows an example sequence of wafer processing for forming through-wafer features such as vias.
Figures 2A-2V show examples of structures at various stages of the processing sequence of
Figure 3 is a block diagram representing the via metallization process according to various aspects of the present invention.
Figures 4A-4D show examples of structures at various stages of the processing sequence of
Figures 5A-5 C show examples of a GaAs wafer assembly at various stages of processing.
Figure 6 shows an example sequence of stress balancing in a GaAs wafer assembly.
Figure 7 shows an example sequence of manufacturing a GaAs wafer assembly.
Figures 8A-8D show an example sequence of singulating a GaAs integrated circuit die from a wafer.
Figure 9 shows an example sequence of ball grid array packaging of singulated GaAs integrated circuit dies, according to one embodiment.
Figures 10A-10 H show examples of structures at various stages of the processing sequence of
Figure 11 shows an example shows an example sequence of land grid array packaging of singulated GaAs integrated circuit dies, according to one embodiment.
Figures 12A-12G show examples of structures at various stages of the processing sequence of
Figure 13 shows an example shows an example sequence of leadframe packaging of singulated GaAs integrated circuit dies, according to one embodiment.
Figures 14A-14D show examples of structures at various stages of the processing sequence of
Figures 15A-15E show examples of structures at various stages of the processing sequence of
Figure 16 illustrates a GaAs integrated circuit device made according to various methods of the present invention, mounted onto a printed circuit board.
Figure 17 illustrates an electronic device incorporating a GaAs integrated circuit device made according to various methods of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Application No.: 14/530533 Filing Date: AMENDMENTS TO THE CLAIMS 1. canceled
A GaAs wafer assembly comprising: a GaAs substrate layer, the GaAs substrate layer having a thickness [[s]]; a contact layer, the contact layer configured to apply a tensile stress to the GaAs substrate layer; and a compensating layer, the compensating layer configured to apply a compressive stress onto the GaAs substrate layer that substantially offsets the tensile stress; and a seed layer located between the compensating layer and the contact layer.
The GaAs wafer assembly of Claim 2 wherein the GaAs wafer assembly is substantially free of warpage.
The GaAs wafer assembly of Claim 2 wherein the thickness of the GaAs substrate layer is approximately 675 p m or less.
The GaAs wafer assembly of Claim 2 wherein the thickness of the GaAs substrate layer is approximately 100 pm.
The GaAs wafer assembly of Claim 2 wherein the contact layer comprises includes copper.
The GaAs wafer assembly of Claim 2 wherein the contact layer is selected from the group consisting of nickel, palladium, and gold.
The GaAs wafer assembly of Claim 2 wherein the tensile stress and compressive stress are approximately equal.
The GaAs wafer assembly of Claim 2 wherein the compensating layer is a metal layer.
The GaAs wafer assembly of Claim 2 wherein the compensating layer is located between the GaAs substrate layer and the conductive contact layer.
canceled
The GaAs wafer assembly of Claim [[11]] 2 wherein the seed layer is selected from the group consisting of copper, gold, and palladium.
An integrated circuit comprising: at least one stress-balanced GaAs wafer assembly, the stress-balanced GaAs wafer assembly having a substrate formed from GaAs, the substrate and having a thickness [[s]], a contact layer, the contact layer configured to apply a tensile stress to the GaAs substrate, and a compensating layer selected from the group consisting of nickel vanadium, copper, nickel, and palladium, the compensating layer configured to apply a compressive stress onto the GaAs substrate that substantially offsets the tensile stress.
The integrated circuit of Claim 15 wherein the contact layer is selected from the group consisting of copper, nickel, palladium, and gold.
The integrated circuit of Claim 15 wherein the compensating layer is located between the GaAs substrate and the conductive contact layer.
canceled
An electronic device comprising: a plurality of dies arranged into an array; and at least one stress-balanced GaAs wafer assembly incorporated into at least one of the plurality of dies, the stress-balanced GaAs wafer assembly having a substrate formed from GaAs, the substrate and having a thickness [[s]], a contact layer, the contact layer configured to apply a tensile stress to the GaAs substrate, and a compensating layer located between the substrate and the contact layer, the compensating layer configured to apply a compressive stress onto the GaAs substrate that substantially offsets the tensile stress.
The electronic device of Claim 19 wherein the contact layer is selected from the group consisting of copper, nickel, palladium, and gold and the compensating layer is selected from the group consisting of nickel vanadium, copper, nickel, and palladium.
-3- canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaAs wafer assembly
GaAs integrated circuit
Materials described outside the worked examples.
GaAs substrate
GaAs
contact layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–900 Å | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,231,068Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows an example sequence of wafer processing for forming through-wafer features such as vias.
Figures 2A-2V show examples of structures at various stages of the processing sequence of
Figure 3 is a block diagram representing the via metallization process according to various aspects of the present invention.
Figures 4A-4D show examples of structures at various stages of the processing sequence of
Figures 5A-5 C show examples of a GaAs wafer assembly at various stages of processing.
Figure 6 shows an example sequence of stress balancing in a GaAs wafer assembly.
Figure 7 shows an example sequence of manufacturing a GaAs wafer assembly.
Figures 8A-8D show an example sequence of singulating a GaAs integrated circuit die from a wafer.
Figure 9 shows an example sequence of ball grid array packaging of singulated GaAs integrated circuit dies, according to one embodiment.
Figures 10A-10 H show examples of structures at various stages of the processing sequence of
Figure 11 shows an example shows an example sequence of land grid array packaging of singulated GaAs integrated circuit dies, according to one embodiment.
Figures 12A-12G show examples of structures at various stages of the processing sequence of
Figure 13 shows an example shows an example sequence of leadframe packaging of singulated GaAs integrated circuit dies, according to one embodiment.
Figures 14A-14D show examples of structures at various stages of the processing sequence of
Figures 15A-15E show examples of structures at various stages of the processing sequence of
Figure 16 illustrates a GaAs integrated circuit device made according to various methods of the present invention, mounted onto a printed circuit board.
Figure 17 illustrates an electronic device incorporating a GaAs integrated circuit device made according to various methods of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Application No.: 14/530533 Filing Date: AMENDMENTS TO THE CLAIMS 1. canceled
A GaAs wafer assembly comprising: a GaAs substrate layer, the GaAs substrate layer having a thickness [[s]]; a contact layer, the contact layer configured to apply a tensile stress to the GaAs substrate layer; and a compensating layer, the compensating layer configured to apply a compressive stress onto the GaAs substrate layer that substantially offsets the tensile stress; and a seed layer located between the compensating layer and the contact layer.
The GaAs wafer assembly of Claim 2 wherein the GaAs wafer assembly is substantially free of warpage.
The GaAs wafer assembly of Claim 2 wherein the thickness of the GaAs substrate layer is approximately 675 p m or less.
The GaAs wafer assembly of Claim 2 wherein the thickness of the GaAs substrate layer is approximately 100 pm.
The GaAs wafer assembly of Claim 2 wherein the contact layer comprises includes copper.
The GaAs wafer assembly of Claim 2 wherein the contact layer is selected from the group consisting of nickel, palladium, and gold.
The GaAs wafer assembly of Claim 2 wherein the tensile stress and compressive stress are approximately equal.
The GaAs wafer assembly of Claim 2 wherein the compensating layer is a metal layer.
The GaAs wafer assembly of Claim 2 wherein the compensating layer is located between the GaAs substrate layer and the conductive contact layer.
canceled
The GaAs wafer assembly of Claim [[11]] 2 wherein the seed layer is selected from the group consisting of copper, gold, and palladium.
An integrated circuit comprising: at least one stress-balanced GaAs wafer assembly, the stress-balanced GaAs wafer assembly having a substrate formed from GaAs, the substrate and having a thickness [[s]], a contact layer, the contact layer configured to apply a tensile stress to the GaAs substrate, and a compensating layer selected from the group consisting of nickel vanadium, copper, nickel, and palladium, the compensating layer configured to apply a compressive stress onto the GaAs substrate that substantially offsets the tensile stress.
The integrated circuit of Claim 15 wherein the contact layer is selected from the group consisting of copper, nickel, palladium, and gold.
The integrated circuit of Claim 15 wherein the compensating layer is located between the GaAs substrate and the conductive contact layer.
canceled
An electronic device comprising: a plurality of dies arranged into an array; and at least one stress-balanced GaAs wafer assembly incorporated into at least one of the plurality of dies, the stress-balanced GaAs wafer assembly having a substrate formed from GaAs, the substrate and having a thickness [[s]], a contact layer, the contact layer configured to apply a tensile stress to the GaAs substrate, and a compensating layer located between the substrate and the contact layer, the compensating layer configured to apply a compressive stress onto the GaAs substrate that substantially offsets the tensile stress.
The electronic device of Claim 19 wherein the contact layer is selected from the group consisting of copper, nickel, palladium, and gold and the compensating layer is selected from the group consisting of nickel vanadium, copper, nickel, and palladium.
-3- canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaAs wafer assembly
GaAs integrated circuit
Materials described outside the worked examples.
GaAs substrate
GaAs
contact layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–900 Å | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,231,068Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows an example sequence of wafer processing for forming through-wafer features such as vias.
Figures 2A-2V show examples of structures at various stages of the processing sequence of
Figure 3 is a block diagram representing the via metallization process according to various aspects of the present invention.
Figures 4A-4D show examples of structures at various stages of the processing sequence of
Figures 5A-5 C show examples of a GaAs wafer assembly at various stages of processing.
Figure 6 shows an example sequence of stress balancing in a GaAs wafer assembly.
Figure 7 shows an example sequence of manufacturing a GaAs wafer assembly.
Figures 8A-8D show an example sequence of singulating a GaAs integrated circuit die from a wafer.
Figure 9 shows an example sequence of ball grid array packaging of singulated GaAs integrated circuit dies, according to one embodiment.
Figures 10A-10 H show examples of structures at various stages of the processing sequence of
Figure 11 shows an example shows an example sequence of land grid array packaging of singulated GaAs integrated circuit dies, according to one embodiment.
Figures 12A-12G show examples of structures at various stages of the processing sequence of
Figure 13 shows an example shows an example sequence of leadframe packaging of singulated GaAs integrated circuit dies, according to one embodiment.
Figures 14A-14D show examples of structures at various stages of the processing sequence of
Figures 15A-15E show examples of structures at various stages of the processing sequence of
Figure 16 illustrates a GaAs integrated circuit device made according to various methods of the present invention, mounted onto a printed circuit board.
Figure 17 illustrates an electronic device incorporating a GaAs integrated circuit device made according to various methods of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Application No.: 14/530533 Filing Date: AMENDMENTS TO THE CLAIMS 1. canceled
A GaAs wafer assembly comprising: a GaAs substrate layer, the GaAs substrate layer having a thickness [[s]]; a contact layer, the contact layer configured to apply a tensile stress to the GaAs substrate layer; and a compensating layer, the compensating layer configured to apply a compressive stress onto the GaAs substrate layer that substantially offsets the tensile stress; and a seed layer located between the compensating layer and the contact layer.
The GaAs wafer assembly of Claim 2 wherein the GaAs wafer assembly is substantially free of warpage.
The GaAs wafer assembly of Claim 2 wherein the thickness of the GaAs substrate layer is approximately 675 p m or less.
The GaAs wafer assembly of Claim 2 wherein the thickness of the GaAs substrate layer is approximately 100 pm.
The GaAs wafer assembly of Claim 2 wherein the contact layer comprises includes copper.
The GaAs wafer assembly of Claim 2 wherein the contact layer is selected from the group consisting of nickel, palladium, and gold.
The GaAs wafer assembly of Claim 2 wherein the tensile stress and compressive stress are approximately equal.
The GaAs wafer assembly of Claim 2 wherein the compensating layer is a metal layer.
The GaAs wafer assembly of Claim 2 wherein the compensating layer is located between the GaAs substrate layer and the conductive contact layer.
canceled
The GaAs wafer assembly of Claim [[11]] 2 wherein the seed layer is selected from the group consisting of copper, gold, and palladium.
An integrated circuit comprising: at least one stress-balanced GaAs wafer assembly, the stress-balanced GaAs wafer assembly having a substrate formed from GaAs, the substrate and having a thickness [[s]], a contact layer, the contact layer configured to apply a tensile stress to the GaAs substrate, and a compensating layer selected from the group consisting of nickel vanadium, copper, nickel, and palladium, the compensating layer configured to apply a compressive stress onto the GaAs substrate that substantially offsets the tensile stress.
The integrated circuit of Claim 15 wherein the contact layer is selected from the group consisting of copper, nickel, palladium, and gold.
The integrated circuit of Claim 15 wherein the compensating layer is located between the GaAs substrate and the conductive contact layer.
canceled
An electronic device comprising: a plurality of dies arranged into an array; and at least one stress-balanced GaAs wafer assembly incorporated into at least one of the plurality of dies, the stress-balanced GaAs wafer assembly having a substrate formed from GaAs, the substrate and having a thickness [[s]], a contact layer, the contact layer configured to apply a tensile stress to the GaAs substrate, and a compensating layer located between the substrate and the contact layer, the compensating layer configured to apply a compressive stress onto the GaAs substrate that substantially offsets the tensile stress.
The electronic device of Claim 19 wherein the contact layer is selected from the group consisting of copper, nickel, palladium, and gold and the compensating layer is selected from the group consisting of nickel vanadium, copper, nickel, and palladium.
-3- canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaAs wafer assembly
GaAs integrated circuit
Materials described outside the worked examples.
GaAs substrate
GaAs
contact layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–900 Å | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,231,068Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 shows an example sequence of wafer processing for forming through-wafer features such as vias.
Figures 2A-2V show examples of structures at various stages of the processing sequence of
Figure 3 is a block diagram representing the via metallization process according to various aspects of the present invention.
Figures 4A-4D show examples of structures at various stages of the processing sequence of
Figures 5A-5 C show examples of a GaAs wafer assembly at various stages of processing.
Figure 6 shows an example sequence of stress balancing in a GaAs wafer assembly.
Figure 7 shows an example sequence of manufacturing a GaAs wafer assembly.
Figures 8A-8D show an example sequence of singulating a GaAs integrated circuit die from a wafer.
Figure 9 shows an example sequence of ball grid array packaging of singulated GaAs integrated circuit dies, according to one embodiment.
Figures 10A-10 H show examples of structures at various stages of the processing sequence of
Figure 11 shows an example shows an example sequence of land grid array packaging of singulated GaAs integrated circuit dies, according to one embodiment.
Figures 12A-12G show examples of structures at various stages of the processing sequence of
Figure 13 shows an example shows an example sequence of leadframe packaging of singulated GaAs integrated circuit dies, according to one embodiment.
Figures 14A-14D show examples of structures at various stages of the processing sequence of
Figures 15A-15E show examples of structures at various stages of the processing sequence of
Figure 16 illustrates a GaAs integrated circuit device made according to various methods of the present invention, mounted onto a printed circuit board.
Figure 17 illustrates an electronic device incorporating a GaAs integrated circuit device made according to various methods of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Application No.: 14/530533 Filing Date: AMENDMENTS TO THE CLAIMS 1. canceled
A GaAs wafer assembly comprising: a GaAs substrate layer, the GaAs substrate layer having a thickness [[s]]; a contact layer, the contact layer configured to apply a tensile stress to the GaAs substrate layer; and a compensating layer, the compensating layer configured to apply a compressive stress onto the GaAs substrate layer that substantially offsets the tensile stress; and a seed layer located between the compensating layer and the contact layer.
The GaAs wafer assembly of Claim 2 wherein the GaAs wafer assembly is substantially free of warpage.
The GaAs wafer assembly of Claim 2 wherein the thickness of the GaAs substrate layer is approximately 675 p m or less.
The GaAs wafer assembly of Claim 2 wherein the thickness of the GaAs substrate layer is approximately 100 pm.
The GaAs wafer assembly of Claim 2 wherein the contact layer comprises includes copper.
The GaAs wafer assembly of Claim 2 wherein the contact layer is selected from the group consisting of nickel, palladium, and gold.
The GaAs wafer assembly of Claim 2 wherein the tensile stress and compressive stress are approximately equal.
The GaAs wafer assembly of Claim 2 wherein the compensating layer is a metal layer.
The GaAs wafer assembly of Claim 2 wherein the compensating layer is located between the GaAs substrate layer and the conductive contact layer.
canceled
The GaAs wafer assembly of Claim [[11]] 2 wherein the seed layer is selected from the group consisting of copper, gold, and palladium.
An integrated circuit comprising: at least one stress-balanced GaAs wafer assembly, the stress-balanced GaAs wafer assembly having a substrate formed from GaAs, the substrate and having a thickness [[s]], a contact layer, the contact layer configured to apply a tensile stress to the GaAs substrate, and a compensating layer selected from the group consisting of nickel vanadium, copper, nickel, and palladium, the compensating layer configured to apply a compressive stress onto the GaAs substrate that substantially offsets the tensile stress.
The integrated circuit of Claim 15 wherein the contact layer is selected from the group consisting of copper, nickel, palladium, and gold.
The integrated circuit of Claim 15 wherein the compensating layer is located between the GaAs substrate and the conductive contact layer.
canceled
An electronic device comprising: a plurality of dies arranged into an array; and at least one stress-balanced GaAs wafer assembly incorporated into at least one of the plurality of dies, the stress-balanced GaAs wafer assembly having a substrate formed from GaAs, the substrate and having a thickness [[s]], a contact layer, the contact layer configured to apply a tensile stress to the GaAs substrate, and a compensating layer located between the substrate and the contact layer, the compensating layer configured to apply a compressive stress onto the GaAs substrate that substantially offsets the tensile stress.
The electronic device of Claim 19 wherein the contact layer is selected from the group consisting of copper, nickel, palladium, and gold and the compensating layer is selected from the group consisting of nickel vanadium, copper, nickel, and palladium.
-3- canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaAs wafer assembly
GaAs integrated circuit
Materials described outside the worked examples.
GaAs substrate
GaAs
contact layer
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–900 Å | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
electronic device with stress-balanced GaAs wafer assembly
compensating layer
seed layer
copper
Cu
nickel
Ni
palladium
Pd
gold
Au
nickel vanadium
NiV
| — |
Thickness | 500–1500 um | — |
Thickness | 150–170 mm | — |
Thickness | 200–220 mm | — |
Thickness | 500–2000 um | — |
Thickness | 300–320 mm | — |
Thickness | 500–3000 um | — |
electronic device with stress-balanced GaAs wafer assembly
compensating layer
seed layer
copper
Cu
nickel
Ni
palladium
Pd
gold
Au
nickel vanadium
NiV
| — |
Thickness | 500–1500 um | — |
Thickness | 150–170 mm | — |
Thickness | 200–220 mm | — |
Thickness | 500–2000 um | — |
Thickness | 300–320 mm | — |
Thickness | 500–3000 um | — |
electronic device with stress-balanced GaAs wafer assembly
compensating layer
seed layer
copper
Cu
nickel
Ni
palladium
Pd
gold
Au
nickel vanadium
NiV
| — |
Thickness | 500–1500 um | — |
Thickness | 150–170 mm | — |
Thickness | 200–220 mm | — |
Thickness | 500–2000 um | — |
Thickness | 300–320 mm | — |
Thickness | 500–3000 um | — |
electronic device with stress-balanced GaAs wafer assembly
compensating layer
seed layer
copper
Cu
nickel
Ni
palladium
Pd
gold
Au
nickel vanadium
NiV
| — |
Thickness | 500–1500 um | — |
Thickness | 150–170 mm | — |
Thickness | 200–220 mm | — |
Thickness | 500–2000 um | — |
Thickness | 300–320 mm | — |
Thickness | 500–3000 um | — |