Figure 1 is a block diagram representing an example of a sequence of wafer processing for integrating copper aspects of embodiments of the -4- present invention into fabrication processes in GaAs integrated circuit manufacturing.

Figure 2 shows a wafer carrier designated for both copper-contact and gold-contact GaAs wafers prior to metallization processes.

Figures 3A-3N show examples of structures at various stages of the processing sequence of

Figure 4 shows wafer carriers having identifying labels affixed thereto.

Figure 5 is a partial block diagram of copper wafer processing directed to metal plating showing where certain protocols according to embodiments of the present invention are implemented to prevent cross-contamination.

Figure 6 is a partial block diagram of copper wafer processing directed to street formation showing where certain protocols according to embodiments of the present invention are implemented to prevent cross- contamination.

Figure 7 is a partial block diagram of copper wafer processing directed to carrier debonding showing where certain protocols according to embodiments of the present invention are implemented to prevent cross contamination.

Figure 8 is a partial block diagram of copper wafer processing directed to testing showing where certain protocols according to embodiments of the present invention are implemented to prevent cross contamination.

Figures 9A-9D show an example sequence of singulating a GaAs integrated circuit die from a wafer.

Figure 10 shows an example sequence of ball grid array packaging of singulated GaAs integrated circuit dies, according to one embodiment.

Figure 12 illustrates a GaAs integrated circuit device made according to various methods of the present invention, mounted onto a printed circuit board.

Figure 13 illustrates an electronic device incorporating a GaAs integrated circuit device made according to various methods of the present invention.

Figure 1 is a block diagram representing an example of a sequence of wafer processing for integrating copper aspects of embodiments of the -4- present invention into fabrication processes in GaAs integrated circuit manufacturing.

Figure 2 shows a wafer carrier designated for both copper-contact and gold-contact GaAs wafers prior to metallization processes.

Figures 3A-3N show examples of structures at various stages of the processing sequence of

Figure 4 shows wafer carriers having identifying labels affixed thereto.

Figure 5 is a partial block diagram of copper wafer processing directed to metal plating showing where certain protocols according to embodiments of the present invention are implemented to prevent cross-contamination.

Figure 6 is a partial block diagram of copper wafer processing directed to street formation showing where certain protocols according to embodiments of the present invention are implemented to prevent cross- contamination.

Figure 7 is a partial block diagram of copper wafer processing directed to carrier debonding showing where certain protocols according to embodiments of the present invention are implemented to prevent cross contamination.

Figure 8 is a partial block diagram of copper wafer processing directed to testing showing where certain protocols according to embodiments of the present invention are implemented to prevent cross contamination.

Figures 9A-9D show an example sequence of singulating a GaAs integrated circuit die from a wafer.

Figure 10 shows an example sequence of ball grid array packaging of singulated GaAs integrated circuit dies, according to one embodiment.

Figure 12 illustrates a GaAs integrated circuit device made according to various methods of the present invention, mounted onto a printed circuit board.

Figure 13 illustrates an electronic device incorporating a GaAs integrated circuit device made according to various methods of the present invention.

Figure 1 is a block diagram representing an example of a sequence of wafer processing for integrating copper aspects of embodiments of the -4- present invention into fabrication processes in GaAs integrated circuit manufacturing.

Figure 2 shows a wafer carrier designated for both copper-contact and gold-contact GaAs wafers prior to metallization processes.

Figures 3A-3N show examples of structures at various stages of the processing sequence of

Figure 4 shows wafer carriers having identifying labels affixed thereto.

Figure 5 is a partial block diagram of copper wafer processing directed to metal plating showing where certain protocols according to embodiments of the present invention are implemented to prevent cross-contamination.

Figure 6 is a partial block diagram of copper wafer processing directed to street formation showing where certain protocols according to embodiments of the present invention are implemented to prevent cross- contamination.

Figure 7 is a partial block diagram of copper wafer processing directed to carrier debonding showing where certain protocols according to embodiments of the present invention are implemented to prevent cross contamination.

Figure 8 is a partial block diagram of copper wafer processing directed to testing showing where certain protocols according to embodiments of the present invention are implemented to prevent cross contamination.

Figures 9A-9D show an example sequence of singulating a GaAs integrated circuit die from a wafer.

Figure 10 shows an example sequence of ball grid array packaging of singulated GaAs integrated circuit dies, according to one embodiment.

Figure 12 illustrates a GaAs integrated circuit device made according to various methods of the present invention, mounted onto a printed circuit board.

Figure 13 illustrates an electronic device incorporating a GaAs integrated circuit device made according to various methods of the present invention.

Figure 1 is a block diagram representing an example of a sequence of wafer processing for integrating copper aspects of embodiments of the -4- present invention into fabrication processes in GaAs integrated circuit manufacturing.

Figure 2 shows a wafer carrier designated for both copper-contact and gold-contact GaAs wafers prior to metallization processes.

Figures 3A-3N show examples of structures at various stages of the processing sequence of

Figure 4 shows wafer carriers having identifying labels affixed thereto.

Figure 5 is a partial block diagram of copper wafer processing directed to metal plating showing where certain protocols according to embodiments of the present invention are implemented to prevent cross-contamination.

Figure 6 is a partial block diagram of copper wafer processing directed to street formation showing where certain protocols according to embodiments of the present invention are implemented to prevent cross- contamination.

Figure 7 is a partial block diagram of copper wafer processing directed to carrier debonding showing where certain protocols according to embodiments of the present invention are implemented to prevent cross contamination.

Figure 8 is a partial block diagram of copper wafer processing directed to testing showing where certain protocols according to embodiments of the present invention are implemented to prevent cross contamination.

Figures 9A-9D show an example sequence of singulating a GaAs integrated circuit die from a wafer.

Figure 10 shows an example sequence of ball grid array packaging of singulated GaAs integrated circuit dies, according to one embodiment.

Figure 12 illustrates a GaAs integrated circuit device made according to various methods of the present invention, mounted onto a printed circuit board.

Figure 13 illustrates an electronic device incorporating a GaAs integrated circuit device made according to various methods of the present invention.