Patent
US 9,000,485ELECTRODE STRUCTURES, GALLIUM NITRIDE BASED SEMICONDUCTOR DEVICES INCLUDING THE SAME AND METHODS OF MANUFACTURING THE SAME
Jeong-yub Lee
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,000,485Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 0 A and 1 0 B are views respectively illustrating 3D and 2D crystal structures of a region of a first semiconductor layer contacting a source electrode …
FIG. 2 are etched (or, removed), and then the first semiconductor layer 100 under the second semiconductor layer 200a may be etched (or, recessed) to a desired …
FIG. 3 43 Description ELECTRODE STRUCTURES, GALLIUM NITRIDE BASED SEMICONDUCTOR DEVICES INCLUDING THE SAME AND METHODS OF MANUFACTURING THE SAME C …
FIG. 4.
FIGS. 5A to 5E are cross-sectional views illustrating a method of manufacturing a GaN- based semiconductor device including an electrode structure, according …
FIGS. 6A and 6B are views respectively illustrating three-dimensional (3D) and two- dimensional (2D) crystal structures of a region of a second semiconductor …
FIGS. 7A and 7B are views respectively illustrating 3D and 2D crystal structures of the region of the second semiconductor layer contacting the source 6 Atty. …
FIGS. 8A to 8 D are cross-sectional views illustrating a method of manufacturing a GaN- based semiconductor device including an electrode structure, according …
FIGS. 9A to 9 C are cross-sectional views illustrating a method of manufacturing a GaN- based semiconductor device including an electrode structure, according …
FIGS. 10 A and 10 B are views respectively illustrating 3D and 2D crystal structures of a region of the first semiconductor layer contacting the source …
FIGS. 11 A and 11 B are views respectively illustrating 3D and 2D crystal structures of the region of the first semiconductor layer contacting the source …
FIG. 12 is a cross-sectional view illustrating a GaN-based semiconductor device according to a comparative example; [0061]
FIGS. 13A and 13B are views respectively illustrating 3D and 2D crystal structures of a region of a second semiconductor layer contacting an electrode element …
FIG. 14 is a graph showing changes in contact resistance according to annealing temperatures of electrode structures of a comparative example and Samples 1 and …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A G aN-based semiconductor device, comprising: a G aN-based semiconductor layer including a first regiorn, a second region and a third region between the firstregion and the second region; an electrode structure on a-at least one of the first region and the second region of the G aN-based semiconductor layer, the electrode structure including, an electrode element including a conductive material, and a diffusion layer between the electrode element and the G aN-based semiconductor layer, the diffusion layer including a material which is an n-type dopant with respect to the G aN-based semiconductor layer, and the diffusion layer contacting at least one of the first region and the second region of the G aN-based semiconductor layer; a gate electrode over the G aN-based semiconductor layer; and a gate insulation layer between the gate electrode and the G aN-based semiconductor layer r; and an etching barrier layer on the gate insulation layer, the etching barrier layer over only the third region of the GaN-based semiconductor laver, U.S. Application No. 13/489,733 Atty. D kt. No. 2557 S₁-00 1742-US Page 3 of 15 wherein at least one of the first region and the second region of the G aN- based semiconductor layer has a first recess and is doped with the n-type dopant, and an upper surface of the at least one of the first region and the second region of the G aN-based semiconductor layer is etched.
The G aN-based semiconductor device of claim 1, wherein the material of the diffusion layer comprises a Group 4 element.
The G aN-based semiconductor device of claim 1, wherein the material of the diffusion layer comprises at least one selected from Ge, Si, Sn, Pb, G eSi and a combination thereof.
The G aN-based semiconductor device of claim 1, wherein the diffusion layer has a thickness of about 2 nm to about 20 nm.
5. The G aN-based semiconductor device of claim 1, wherein the electrode element has a multi-layered structure.
The GaN-based semiconductor device of claim 1, wherein at least a portion of the electrode element comprises the n-type dopant.
The GaN-based semiconductor device of claim 1, wherein the GaN-based semiconductor layer has a multi-layered structure comprising a G aN layer, and an A I GaN layer, the G aN layer contacts the diffusion layer, and the G aN layer is doped with the n-type dopant.
The G aN-based semiconductor device of claim 1, wherein the at least one of the first region and the second region of the G aN-based semiconductor layer contacting the diffusion layer comprises nitrogen (N) vacancies.
The G aN-based semiconductor device of claim 1, wherein a contact resistance between the electrode structure and the G aN-based semiconductor layer is equal to or less than about lx 10-4 Q-cu.
The G aN-based semiconductor device of claim 1, wherein the G aN-based semiconductor device is a high electron mobility transistor (HEMT).
The GaN-based semiconductor device of claim 1, wherein the G aN-based semiconductor device is a power device.
The G aN-based semiconductor device of claim 1, wherein the GaN-based semiconductor device further comprises: a source electrode on one of the first region and a-the second region of the aN- based semiconductor layer; and a drain electrode on one of the first region and the second region of the G aN- based semiconductor layer, at least one of the source electrode and the drain electrode being the electrode structure, wherein the gate electrode on the GaN-based semiconductor layer is between the source electrode and the drain electrode.
The GaN-based semiconductor device of claim 1 [[19]], wherein the etching barrier layer comprises at least one selected from silicon nitride, silicon oxide, aluminum nitride, aluminum oxide and a combination thereof.
. canceled
. canceled
(Withdrawn-Currently Amended) A method of manufacturing a G aN-based semiconductor device, the method comprising: preparing a G aN-based semiconductor layer including a first region, a second region and a third rerion between the first region and the second region; forming an electrode structure on at least one of a t he first region and the second region of the G aN-based semiconductor layer, the forming an electrode structure comprising, U.S. Application No. 13/489,733 Atty. Dkt. No. 2557 51 -001742-US Page 7 of 15 forming a diffusion layer on the G aN-based semiconductor layer, the diffusion layer including a material which is an n-type dopant with respect to the G aN-based semiconductor layer, and the di ffu sion layer contacting the at least one of the first region and the second region of the G aN-based semiconductor layer, forming an electrode element including a conductive material on the diffusion layer, and etching an upper surface of the at least one of the first region and the second region of the G aN-based semiconductor layer to form a first recess; forming a gate electrode on the G aN-based semiconductor layer; forming a gate insulation layer between the G aN-based semiconductor layer and the gate electrode; forming an etching barrier layer on the gate insulation layer, the etching barrier layer over only the third region of the GaN-based semiconductor layer; and annealing the diffusion layer and the G aN-based semiconductor layer so as to diffuse the n-type dopant of the diffusion layer into the at least one of the first region and the second region of the G aN-based semiconductor layer.
The method of claim 23, wherein the material of the diffusion layer comprises a Group 4 element. withdrawn
The method of claim 23, wherein the material of the diffusion layer comprises at least one selected from Ge, Si, Sn, Pb, GeSi and a combination thereof. withdrawn
The method of claim 23, wherein the electrode element is formed to have a Ti/Al-based multi-layered structure. withdrawn
The method of claim 23, wherein the annealing is performed at a temperature of about 600 * C to about 800 *C. withdrawn
The method of claim 23, wherein the G aN-based semiconductor layer has a multi-layered structure comprising a G aN layer and an AlGaN layer. withdrawn
The method of claim 23, wherein the G aN-based semiconductor device is an HEM T. withdrawn
(Withdrawn-Currently Amended) The method of claim 23, further comprising: fo rming a source electrode on one of the first region and a-the second region of the G aN-based semiconductor layer at one side of the gate electrode; and forming a drain electrode on one of the first region and the second region of the G aN-based semiconductor layer at another side of the gate electrode, at least one of the source electrode and the drain electrode being the electrode structure.
. canceled
(Withdrawn-Currently Amended) The method of claim 423, wherein, U.S. Application No. 13/489,733 Atty. Dkt. No. 2557 SI -001742-US Page 9 of 15 a-the third region of the semiconductor layer has a second recess, and a portion of the gate insulation layer is formed conformal with the second recess of the GaN-based semiconductor layer.
The method of claim 32, wherein the second recess of the G aN-based semiconductor layer corresponds to a channel region. withdrawn
. canceled
(Withdrawn-Currently Amended) The method of claim 3523, wherein, the G aN-based semiconductor layer has a multi-layered structure comprising a G aN layer and an A lG aN layer, and the method further comprises e tching the-an upper surface of at least one of the first region and an upper surface of the second region to form s the first recess and a third recess, respectively, i n one selected from the G aN layer and the A I GaN layer.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based semiconductor device (HEMT/power device)
Materials described outside the worked examples.
GaN
diffusion layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 are etched (or, removed), and then the first semiconductor layer 100 under the second semiconductor layer 200a may be etched (or, recessed) to a desired …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Contact Resistance | ≤ 0.0001 Ω·cm² | GaN |
Layer Thickness | 2–20 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,000,485Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 0 A and 1 0 B are views respectively illustrating 3D and 2D crystal structures of a region of a first semiconductor layer contacting a source electrode …
FIG. 2 are etched (or, removed), and then the first semiconductor layer 100 under the second semiconductor layer 200a may be etched (or, recessed) to a desired …
FIG. 3 43 Description ELECTRODE STRUCTURES, GALLIUM NITRIDE BASED SEMICONDUCTOR DEVICES INCLUDING THE SAME AND METHODS OF MANUFACTURING THE SAME C …
FIG. 4.
FIGS. 5A to 5E are cross-sectional views illustrating a method of manufacturing a GaN- based semiconductor device including an electrode structure, according …
FIGS. 6A and 6B are views respectively illustrating three-dimensional (3D) and two- dimensional (2D) crystal structures of a region of a second semiconductor …
FIGS. 7A and 7B are views respectively illustrating 3D and 2D crystal structures of the region of the second semiconductor layer contacting the source 6 Atty. …
FIGS. 8A to 8 D are cross-sectional views illustrating a method of manufacturing a GaN- based semiconductor device including an electrode structure, according …
FIGS. 9A to 9 C are cross-sectional views illustrating a method of manufacturing a GaN- based semiconductor device including an electrode structure, according …
FIGS. 10 A and 10 B are views respectively illustrating 3D and 2D crystal structures of a region of the first semiconductor layer contacting the source …
FIGS. 11 A and 11 B are views respectively illustrating 3D and 2D crystal structures of the region of the first semiconductor layer contacting the source …
FIG. 12 is a cross-sectional view illustrating a GaN-based semiconductor device according to a comparative example; [0061]
FIGS. 13A and 13B are views respectively illustrating 3D and 2D crystal structures of a region of a second semiconductor layer contacting an electrode element …
FIG. 14 is a graph showing changes in contact resistance according to annealing temperatures of electrode structures of a comparative example and Samples 1 and …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A G aN-based semiconductor device, comprising: a G aN-based semiconductor layer including a first regiorn, a second region and a third region between the firstregion and the second region; an electrode structure on a-at least one of the first region and the second region of the G aN-based semiconductor layer, the electrode structure including, an electrode element including a conductive material, and a diffusion layer between the electrode element and the G aN-based semiconductor layer, the diffusion layer including a material which is an n-type dopant with respect to the G aN-based semiconductor layer, and the diffusion layer contacting at least one of the first region and the second region of the G aN-based semiconductor layer; a gate electrode over the G aN-based semiconductor layer; and a gate insulation layer between the gate electrode and the G aN-based semiconductor layer r; and an etching barrier layer on the gate insulation layer, the etching barrier layer over only the third region of the GaN-based semiconductor laver, U.S. Application No. 13/489,733 Atty. D kt. No. 2557 S₁-00 1742-US Page 3 of 15 wherein at least one of the first region and the second region of the G aN- based semiconductor layer has a first recess and is doped with the n-type dopant, and an upper surface of the at least one of the first region and the second region of the G aN-based semiconductor layer is etched.
The G aN-based semiconductor device of claim 1, wherein the material of the diffusion layer comprises a Group 4 element.
The G aN-based semiconductor device of claim 1, wherein the material of the diffusion layer comprises at least one selected from Ge, Si, Sn, Pb, G eSi and a combination thereof.
The G aN-based semiconductor device of claim 1, wherein the diffusion layer has a thickness of about 2 nm to about 20 nm.
5. The G aN-based semiconductor device of claim 1, wherein the electrode element has a multi-layered structure.
The GaN-based semiconductor device of claim 1, wherein at least a portion of the electrode element comprises the n-type dopant.
The GaN-based semiconductor device of claim 1, wherein the GaN-based semiconductor layer has a multi-layered structure comprising a G aN layer, and an A I GaN layer, the G aN layer contacts the diffusion layer, and the G aN layer is doped with the n-type dopant.
The G aN-based semiconductor device of claim 1, wherein the at least one of the first region and the second region of the G aN-based semiconductor layer contacting the diffusion layer comprises nitrogen (N) vacancies.
The G aN-based semiconductor device of claim 1, wherein a contact resistance between the electrode structure and the G aN-based semiconductor layer is equal to or less than about lx 10-4 Q-cu.
The G aN-based semiconductor device of claim 1, wherein the G aN-based semiconductor device is a high electron mobility transistor (HEMT).
The GaN-based semiconductor device of claim 1, wherein the G aN-based semiconductor device is a power device.
The G aN-based semiconductor device of claim 1, wherein the GaN-based semiconductor device further comprises: a source electrode on one of the first region and a-the second region of the aN- based semiconductor layer; and a drain electrode on one of the first region and the second region of the G aN- based semiconductor layer, at least one of the source electrode and the drain electrode being the electrode structure, wherein the gate electrode on the GaN-based semiconductor layer is between the source electrode and the drain electrode.
The GaN-based semiconductor device of claim 1 [[19]], wherein the etching barrier layer comprises at least one selected from silicon nitride, silicon oxide, aluminum nitride, aluminum oxide and a combination thereof.
. canceled
. canceled
(Withdrawn-Currently Amended) A method of manufacturing a G aN-based semiconductor device, the method comprising: preparing a G aN-based semiconductor layer including a first region, a second region and a third rerion between the first region and the second region; forming an electrode structure on at least one of a t he first region and the second region of the G aN-based semiconductor layer, the forming an electrode structure comprising, U.S. Application No. 13/489,733 Atty. Dkt. No. 2557 51 -001742-US Page 7 of 15 forming a diffusion layer on the G aN-based semiconductor layer, the diffusion layer including a material which is an n-type dopant with respect to the G aN-based semiconductor layer, and the di ffu sion layer contacting the at least one of the first region and the second region of the G aN-based semiconductor layer, forming an electrode element including a conductive material on the diffusion layer, and etching an upper surface of the at least one of the first region and the second region of the G aN-based semiconductor layer to form a first recess; forming a gate electrode on the G aN-based semiconductor layer; forming a gate insulation layer between the G aN-based semiconductor layer and the gate electrode; forming an etching barrier layer on the gate insulation layer, the etching barrier layer over only the third region of the GaN-based semiconductor layer; and annealing the diffusion layer and the G aN-based semiconductor layer so as to diffuse the n-type dopant of the diffusion layer into the at least one of the first region and the second region of the G aN-based semiconductor layer.
The method of claim 23, wherein the material of the diffusion layer comprises a Group 4 element. withdrawn
The method of claim 23, wherein the material of the diffusion layer comprises at least one selected from Ge, Si, Sn, Pb, GeSi and a combination thereof. withdrawn
The method of claim 23, wherein the electrode element is formed to have a Ti/Al-based multi-layered structure. withdrawn
The method of claim 23, wherein the annealing is performed at a temperature of about 600 * C to about 800 *C. withdrawn
The method of claim 23, wherein the G aN-based semiconductor layer has a multi-layered structure comprising a G aN layer and an AlGaN layer. withdrawn
The method of claim 23, wherein the G aN-based semiconductor device is an HEM T. withdrawn
(Withdrawn-Currently Amended) The method of claim 23, further comprising: fo rming a source electrode on one of the first region and a-the second region of the G aN-based semiconductor layer at one side of the gate electrode; and forming a drain electrode on one of the first region and the second region of the G aN-based semiconductor layer at another side of the gate electrode, at least one of the source electrode and the drain electrode being the electrode structure.
. canceled
(Withdrawn-Currently Amended) The method of claim 423, wherein, U.S. Application No. 13/489,733 Atty. Dkt. No. 2557 SI -001742-US Page 9 of 15 a-the third region of the semiconductor layer has a second recess, and a portion of the gate insulation layer is formed conformal with the second recess of the GaN-based semiconductor layer.
The method of claim 32, wherein the second recess of the G aN-based semiconductor layer corresponds to a channel region. withdrawn
. canceled
(Withdrawn-Currently Amended) The method of claim 3523, wherein, the G aN-based semiconductor layer has a multi-layered structure comprising a G aN layer and an A lG aN layer, and the method further comprises e tching the-an upper surface of at least one of the first region and an upper surface of the second region to form s the first recess and a third recess, respectively, i n one selected from the G aN layer and the A I GaN layer.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based semiconductor device (HEMT/power device)
Materials described outside the worked examples.
GaN
diffusion layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 are etched (or, removed), and then the first semiconductor layer 100 under the second semiconductor layer 200a may be etched (or, recessed) to a desired …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Contact Resistance | ≤ 0.0001 Ω·cm² | GaN |
Layer Thickness | 2–20 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
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US 9,000,485Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 0 A and 1 0 B are views respectively illustrating 3D and 2D crystal structures of a region of a first semiconductor layer contacting a source electrode …
FIG. 2 are etched (or, removed), and then the first semiconductor layer 100 under the second semiconductor layer 200a may be etched (or, recessed) to a desired …
FIG. 3 43 Description ELECTRODE STRUCTURES, GALLIUM NITRIDE BASED SEMICONDUCTOR DEVICES INCLUDING THE SAME AND METHODS OF MANUFACTURING THE SAME C …
FIG. 4.
FIGS. 5A to 5E are cross-sectional views illustrating a method of manufacturing a GaN- based semiconductor device including an electrode structure, according …
FIGS. 6A and 6B are views respectively illustrating three-dimensional (3D) and two- dimensional (2D) crystal structures of a region of a second semiconductor …
FIGS. 7A and 7B are views respectively illustrating 3D and 2D crystal structures of the region of the second semiconductor layer contacting the source 6 Atty. …
FIGS. 8A to 8 D are cross-sectional views illustrating a method of manufacturing a GaN- based semiconductor device including an electrode structure, according …
FIGS. 9A to 9 C are cross-sectional views illustrating a method of manufacturing a GaN- based semiconductor device including an electrode structure, according …
FIGS. 10 A and 10 B are views respectively illustrating 3D and 2D crystal structures of a region of the first semiconductor layer contacting the source …
FIGS. 11 A and 11 B are views respectively illustrating 3D and 2D crystal structures of the region of the first semiconductor layer contacting the source …
FIG. 12 is a cross-sectional view illustrating a GaN-based semiconductor device according to a comparative example; [0061]
FIGS. 13A and 13B are views respectively illustrating 3D and 2D crystal structures of a region of a second semiconductor layer contacting an electrode element …
FIG. 14 is a graph showing changes in contact resistance according to annealing temperatures of electrode structures of a comparative example and Samples 1 and …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A G aN-based semiconductor device, comprising: a G aN-based semiconductor layer including a first regiorn, a second region and a third region between the firstregion and the second region; an electrode structure on a-at least one of the first region and the second region of the G aN-based semiconductor layer, the electrode structure including, an electrode element including a conductive material, and a diffusion layer between the electrode element and the G aN-based semiconductor layer, the diffusion layer including a material which is an n-type dopant with respect to the G aN-based semiconductor layer, and the diffusion layer contacting at least one of the first region and the second region of the G aN-based semiconductor layer; a gate electrode over the G aN-based semiconductor layer; and a gate insulation layer between the gate electrode and the G aN-based semiconductor layer r; and an etching barrier layer on the gate insulation layer, the etching barrier layer over only the third region of the GaN-based semiconductor laver, U.S. Application No. 13/489,733 Atty. D kt. No. 2557 S₁-00 1742-US Page 3 of 15 wherein at least one of the first region and the second region of the G aN- based semiconductor layer has a first recess and is doped with the n-type dopant, and an upper surface of the at least one of the first region and the second region of the G aN-based semiconductor layer is etched.
The G aN-based semiconductor device of claim 1, wherein the material of the diffusion layer comprises a Group 4 element.
The G aN-based semiconductor device of claim 1, wherein the material of the diffusion layer comprises at least one selected from Ge, Si, Sn, Pb, G eSi and a combination thereof.
The G aN-based semiconductor device of claim 1, wherein the diffusion layer has a thickness of about 2 nm to about 20 nm.
5. The G aN-based semiconductor device of claim 1, wherein the electrode element has a multi-layered structure.
The GaN-based semiconductor device of claim 1, wherein at least a portion of the electrode element comprises the n-type dopant.
The GaN-based semiconductor device of claim 1, wherein the GaN-based semiconductor layer has a multi-layered structure comprising a G aN layer, and an A I GaN layer, the G aN layer contacts the diffusion layer, and the G aN layer is doped with the n-type dopant.
The G aN-based semiconductor device of claim 1, wherein the at least one of the first region and the second region of the G aN-based semiconductor layer contacting the diffusion layer comprises nitrogen (N) vacancies.
The G aN-based semiconductor device of claim 1, wherein a contact resistance between the electrode structure and the G aN-based semiconductor layer is equal to or less than about lx 10-4 Q-cu.
The G aN-based semiconductor device of claim 1, wherein the G aN-based semiconductor device is a high electron mobility transistor (HEMT).
The GaN-based semiconductor device of claim 1, wherein the G aN-based semiconductor device is a power device.
The G aN-based semiconductor device of claim 1, wherein the GaN-based semiconductor device further comprises: a source electrode on one of the first region and a-the second region of the aN- based semiconductor layer; and a drain electrode on one of the first region and the second region of the G aN- based semiconductor layer, at least one of the source electrode and the drain electrode being the electrode structure, wherein the gate electrode on the GaN-based semiconductor layer is between the source electrode and the drain electrode.
The GaN-based semiconductor device of claim 1 [[19]], wherein the etching barrier layer comprises at least one selected from silicon nitride, silicon oxide, aluminum nitride, aluminum oxide and a combination thereof.
. canceled
. canceled
(Withdrawn-Currently Amended) A method of manufacturing a G aN-based semiconductor device, the method comprising: preparing a G aN-based semiconductor layer including a first region, a second region and a third rerion between the first region and the second region; forming an electrode structure on at least one of a t he first region and the second region of the G aN-based semiconductor layer, the forming an electrode structure comprising, U.S. Application No. 13/489,733 Atty. Dkt. No. 2557 51 -001742-US Page 7 of 15 forming a diffusion layer on the G aN-based semiconductor layer, the diffusion layer including a material which is an n-type dopant with respect to the G aN-based semiconductor layer, and the di ffu sion layer contacting the at least one of the first region and the second region of the G aN-based semiconductor layer, forming an electrode element including a conductive material on the diffusion layer, and etching an upper surface of the at least one of the first region and the second region of the G aN-based semiconductor layer to form a first recess; forming a gate electrode on the G aN-based semiconductor layer; forming a gate insulation layer between the G aN-based semiconductor layer and the gate electrode; forming an etching barrier layer on the gate insulation layer, the etching barrier layer over only the third region of the GaN-based semiconductor layer; and annealing the diffusion layer and the G aN-based semiconductor layer so as to diffuse the n-type dopant of the diffusion layer into the at least one of the first region and the second region of the G aN-based semiconductor layer.
The method of claim 23, wherein the material of the diffusion layer comprises a Group 4 element. withdrawn
The method of claim 23, wherein the material of the diffusion layer comprises at least one selected from Ge, Si, Sn, Pb, GeSi and a combination thereof. withdrawn
The method of claim 23, wherein the electrode element is formed to have a Ti/Al-based multi-layered structure. withdrawn
The method of claim 23, wherein the annealing is performed at a temperature of about 600 * C to about 800 *C. withdrawn
The method of claim 23, wherein the G aN-based semiconductor layer has a multi-layered structure comprising a G aN layer and an AlGaN layer. withdrawn
The method of claim 23, wherein the G aN-based semiconductor device is an HEM T. withdrawn
(Withdrawn-Currently Amended) The method of claim 23, further comprising: fo rming a source electrode on one of the first region and a-the second region of the G aN-based semiconductor layer at one side of the gate electrode; and forming a drain electrode on one of the first region and the second region of the G aN-based semiconductor layer at another side of the gate electrode, at least one of the source electrode and the drain electrode being the electrode structure.
. canceled
(Withdrawn-Currently Amended) The method of claim 423, wherein, U.S. Application No. 13/489,733 Atty. Dkt. No. 2557 SI -001742-US Page 9 of 15 a-the third region of the semiconductor layer has a second recess, and a portion of the gate insulation layer is formed conformal with the second recess of the GaN-based semiconductor layer.
The method of claim 32, wherein the second recess of the G aN-based semiconductor layer corresponds to a channel region. withdrawn
. canceled
(Withdrawn-Currently Amended) The method of claim 3523, wherein, the G aN-based semiconductor layer has a multi-layered structure comprising a G aN layer and an A lG aN layer, and the method further comprises e tching the-an upper surface of at least one of the first region and an upper surface of the second region to form s the first recess and a third recess, respectively, i n one selected from the G aN layer and the A I GaN layer.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based semiconductor device (HEMT/power device)
Materials described outside the worked examples.
GaN
diffusion layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 are etched (or, removed), and then the first semiconductor layer 100 under the second semiconductor layer 200a may be etched (or, recessed) to a desired …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Contact Resistance | ≤ 0.0001 Ω·cm² | GaN |
Layer Thickness | 2–20 nm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,000,485Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1 0 A and 1 0 B are views respectively illustrating 3D and 2D crystal structures of a region of a first semiconductor layer contacting a source electrode …
FIG. 2 are etched (or, removed), and then the first semiconductor layer 100 under the second semiconductor layer 200a may be etched (or, recessed) to a desired …
FIG. 3 43 Description ELECTRODE STRUCTURES, GALLIUM NITRIDE BASED SEMICONDUCTOR DEVICES INCLUDING THE SAME AND METHODS OF MANUFACTURING THE SAME C …
FIG. 4.
FIGS. 5A to 5E are cross-sectional views illustrating a method of manufacturing a GaN- based semiconductor device including an electrode structure, according …
FIGS. 6A and 6B are views respectively illustrating three-dimensional (3D) and two- dimensional (2D) crystal structures of a region of a second semiconductor …
FIGS. 7A and 7B are views respectively illustrating 3D and 2D crystal structures of the region of the second semiconductor layer contacting the source 6 Atty. …
FIGS. 8A to 8 D are cross-sectional views illustrating a method of manufacturing a GaN- based semiconductor device including an electrode structure, according …
FIGS. 9A to 9 C are cross-sectional views illustrating a method of manufacturing a GaN- based semiconductor device including an electrode structure, according …
FIGS. 10 A and 10 B are views respectively illustrating 3D and 2D crystal structures of a region of the first semiconductor layer contacting the source …
FIGS. 11 A and 11 B are views respectively illustrating 3D and 2D crystal structures of the region of the first semiconductor layer contacting the source …
FIG. 12 is a cross-sectional view illustrating a GaN-based semiconductor device according to a comparative example; [0061]
FIGS. 13A and 13B are views respectively illustrating 3D and 2D crystal structures of a region of a second semiconductor layer contacting an electrode element …
FIG. 14 is a graph showing changes in contact resistance according to annealing temperatures of electrode structures of a comparative example and Samples 1 and …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A G aN-based semiconductor device, comprising: a G aN-based semiconductor layer including a first regiorn, a second region and a third region between the firstregion and the second region; an electrode structure on a-at least one of the first region and the second region of the G aN-based semiconductor layer, the electrode structure including, an electrode element including a conductive material, and a diffusion layer between the electrode element and the G aN-based semiconductor layer, the diffusion layer including a material which is an n-type dopant with respect to the G aN-based semiconductor layer, and the diffusion layer contacting at least one of the first region and the second region of the G aN-based semiconductor layer; a gate electrode over the G aN-based semiconductor layer; and a gate insulation layer between the gate electrode and the G aN-based semiconductor layer r; and an etching barrier layer on the gate insulation layer, the etching barrier layer over only the third region of the GaN-based semiconductor laver, U.S. Application No. 13/489,733 Atty. D kt. No. 2557 S₁-00 1742-US Page 3 of 15 wherein at least one of the first region and the second region of the G aN- based semiconductor layer has a first recess and is doped with the n-type dopant, and an upper surface of the at least one of the first region and the second region of the G aN-based semiconductor layer is etched.
The G aN-based semiconductor device of claim 1, wherein the material of the diffusion layer comprises a Group 4 element.
The G aN-based semiconductor device of claim 1, wherein the material of the diffusion layer comprises at least one selected from Ge, Si, Sn, Pb, G eSi and a combination thereof.
The G aN-based semiconductor device of claim 1, wherein the diffusion layer has a thickness of about 2 nm to about 20 nm.
5. The G aN-based semiconductor device of claim 1, wherein the electrode element has a multi-layered structure.
The GaN-based semiconductor device of claim 1, wherein at least a portion of the electrode element comprises the n-type dopant.
The GaN-based semiconductor device of claim 1, wherein the GaN-based semiconductor layer has a multi-layered structure comprising a G aN layer, and an A I GaN layer, the G aN layer contacts the diffusion layer, and the G aN layer is doped with the n-type dopant.
The G aN-based semiconductor device of claim 1, wherein the at least one of the first region and the second region of the G aN-based semiconductor layer contacting the diffusion layer comprises nitrogen (N) vacancies.
The G aN-based semiconductor device of claim 1, wherein a contact resistance between the electrode structure and the G aN-based semiconductor layer is equal to or less than about lx 10-4 Q-cu.
The G aN-based semiconductor device of claim 1, wherein the G aN-based semiconductor device is a high electron mobility transistor (HEMT).
The GaN-based semiconductor device of claim 1, wherein the G aN-based semiconductor device is a power device.
The G aN-based semiconductor device of claim 1, wherein the GaN-based semiconductor device further comprises: a source electrode on one of the first region and a-the second region of the aN- based semiconductor layer; and a drain electrode on one of the first region and the second region of the G aN- based semiconductor layer, at least one of the source electrode and the drain electrode being the electrode structure, wherein the gate electrode on the GaN-based semiconductor layer is between the source electrode and the drain electrode.
The GaN-based semiconductor device of claim 1 [[19]], wherein the etching barrier layer comprises at least one selected from silicon nitride, silicon oxide, aluminum nitride, aluminum oxide and a combination thereof.
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(Withdrawn-Currently Amended) A method of manufacturing a G aN-based semiconductor device, the method comprising: preparing a G aN-based semiconductor layer including a first region, a second region and a third rerion between the first region and the second region; forming an electrode structure on at least one of a t he first region and the second region of the G aN-based semiconductor layer, the forming an electrode structure comprising, U.S. Application No. 13/489,733 Atty. Dkt. No. 2557 51 -001742-US Page 7 of 15 forming a diffusion layer on the G aN-based semiconductor layer, the diffusion layer including a material which is an n-type dopant with respect to the G aN-based semiconductor layer, and the di ffu sion layer contacting the at least one of the first region and the second region of the G aN-based semiconductor layer, forming an electrode element including a conductive material on the diffusion layer, and etching an upper surface of the at least one of the first region and the second region of the G aN-based semiconductor layer to form a first recess; forming a gate electrode on the G aN-based semiconductor layer; forming a gate insulation layer between the G aN-based semiconductor layer and the gate electrode; forming an etching barrier layer on the gate insulation layer, the etching barrier layer over only the third region of the GaN-based semiconductor layer; and annealing the diffusion layer and the G aN-based semiconductor layer so as to diffuse the n-type dopant of the diffusion layer into the at least one of the first region and the second region of the G aN-based semiconductor layer.
The method of claim 23, wherein the material of the diffusion layer comprises a Group 4 element. withdrawn
The method of claim 23, wherein the material of the diffusion layer comprises at least one selected from Ge, Si, Sn, Pb, GeSi and a combination thereof. withdrawn
The method of claim 23, wherein the electrode element is formed to have a Ti/Al-based multi-layered structure. withdrawn
The method of claim 23, wherein the annealing is performed at a temperature of about 600 * C to about 800 *C. withdrawn
The method of claim 23, wherein the G aN-based semiconductor layer has a multi-layered structure comprising a G aN layer and an AlGaN layer. withdrawn
The method of claim 23, wherein the G aN-based semiconductor device is an HEM T. withdrawn
(Withdrawn-Currently Amended) The method of claim 23, further comprising: fo rming a source electrode on one of the first region and a-the second region of the G aN-based semiconductor layer at one side of the gate electrode; and forming a drain electrode on one of the first region and the second region of the G aN-based semiconductor layer at another side of the gate electrode, at least one of the source electrode and the drain electrode being the electrode structure.
. canceled
(Withdrawn-Currently Amended) The method of claim 423, wherein, U.S. Application No. 13/489,733 Atty. Dkt. No. 2557 SI -001742-US Page 9 of 15 a-the third region of the semiconductor layer has a second recess, and a portion of the gate insulation layer is formed conformal with the second recess of the GaN-based semiconductor layer.
The method of claim 32, wherein the second recess of the G aN-based semiconductor layer corresponds to a channel region. withdrawn
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(Withdrawn-Currently Amended) The method of claim 3523, wherein, the G aN-based semiconductor layer has a multi-layered structure comprising a G aN layer and an A lG aN layer, and the method further comprises e tching the-an upper surface of at least one of the first region and an upper surface of the second region to form s the first recess and a third recess, respectively, i n one selected from the G aN layer and the A I GaN layer.
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based semiconductor device (HEMT/power device)
Materials described outside the worked examples.
GaN
diffusion layer
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 2 are etched (or, removed), and then the first semiconductor layer 100 under the second semiconductor layer 200a may be etched (or, recessed) to a desired …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Contact Resistance | ≤ 0.0001 Ω·cm² | GaN |
Layer Thickness | 2–20 nm |
Related documents with shared materials, methods, properties, or citations.
Group 4 element
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Ge
Si
Sn
Pb
GeSi
Ti/Al-based multilayer
Ti/Al
Ti/Al/Ni/Au
Ti/Al/TiN
Ti/Al/Mo
Ti/Al/W
silicon nitride
Si₃N₄
silicon oxide
SiO₂
aluminum nitride
AlN
aluminum oxide
Al₂O₃
FIG. 14 is a graph showing changes in contact resistance according to annealing temperatures of electrode structures of a comparative example and Samples 1 and …
Thickness | 1–120 nm | — |
Duration | 30–120 s | — |
Thickness | ≤ 2 nm | — |
Thickness | ≥ 20 nm | — |
Group 4 element
AlGaN
Ge
Si
Sn
Pb
GeSi
Ti/Al-based multilayer
Ti/Al
Ti/Al/Ni/Au
Ti/Al/TiN
Ti/Al/Mo
Ti/Al/W
silicon nitride
Si₃N₄
silicon oxide
SiO₂
aluminum nitride
AlN
aluminum oxide
Al₂O₃
FIG. 14 is a graph showing changes in contact resistance according to annealing temperatures of electrode structures of a comparative example and Samples 1 and …
Thickness | 1–120 nm | — |
Duration | 30–120 s | — |
Thickness | ≤ 2 nm | — |
Thickness | ≥ 20 nm | — |
Group 4 element
AlGaN
Ge
Si
Sn
Pb
GeSi
Ti/Al-based multilayer
Ti/Al
Ti/Al/Ni/Au
Ti/Al/TiN
Ti/Al/Mo
Ti/Al/W
silicon nitride
Si₃N₄
silicon oxide
SiO₂
aluminum nitride
AlN
aluminum oxide
Al₂O₃
FIG. 14 is a graph showing changes in contact resistance according to annealing temperatures of electrode structures of a comparative example and Samples 1 and …
Thickness | 1–120 nm | — |
Duration | 30–120 s | — |
Thickness | ≤ 2 nm | — |
Thickness | ≥ 20 nm | — |
Group 4 element
AlGaN
Ge
Si
Sn
Pb
GeSi
Ti/Al-based multilayer
Ti/Al
Ti/Al/Ni/Au
Ti/Al/TiN
Ti/Al/Mo
Ti/Al/W
silicon nitride
Si₃N₄
silicon oxide
SiO₂
aluminum nitride
AlN
aluminum oxide
Al₂O₃
FIG. 14 is a graph showing changes in contact resistance according to annealing temperatures of electrode structures of a comparative example and Samples 1 and …
Thickness | 1–120 nm | — |
Duration | 30–120 s | — |
Thickness | ≤ 2 nm | — |
Thickness | ≥ 20 nm | — |