A GaN heter [[e] ojunction semiconductor device comprising: a substrate; a layer structure having a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between the substrate and the second layer; and a Schottky gate electrode and a first further electrode each conductively coupled to a different area of the e j 4 the Ga N hetero j unction semiconductor device, said Schottky gate electrode comprising a central region and an edge region, wherein the Schottky gate electrode comprises: a lowermost portion which is co-planar with a first dielectric layer portion over the second layer; a middle portion which is co-planar with a second dielectric layer, the middle portion overlapping the lowermost portion; and an upper portion which is co-planar with a third dielectric layer, the upper portion overlapping the middle portion.
A-dee e 4 IiA₄ The GaN hetero i unction semiconductor device as claimed in claim 1, wherein the first dielectric layer is over the second dielectric layer, and the second dielectric layer has a well in the region of the gate and in which the first dielectric layeris formed such that the first dielectric layer portion is the only one of the first, second and third dielectric layers beneath the overlap of the middle portion over the lowermost portion.
Ae e-The G aN heter oj unction semiconductor device as claimed in claim 1, wherein the first dielectric layer comprises an LPCVD layer, and the second and third dielectric layers comprise PEC V D layers.
(Current ly Amended) A-4 The GaNhh etero junction semiconductor device as claimed in claim 1, wherein the length of the overlap of the middle portion over the lowermost portion is at least twice the thickness of the first dielectric layer.
Aev A-lain zk4unis4 The GaN hetero i unc t ion semiconductor device as claimed in claim 1, wherein the thickness of the first dielectric layer is in the range 5 to 50 nm.
A e l4 4 -a 4 The GaN hetero j unction semiconductor device as claimed in claim 1, wherein the first layer comprises GaN and the second layer comprises AlGaN.
A method of manufacturing a semiconductor device comprising: providing a substrate carrying a layer structure having a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between the substrate and the second layer, the interface between the first layer and second layer defining a heterojunction; forming a dielectric layer structure over the second layer; forming a Schottky gate electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky gate electrode comprising a central region and an edge region, wherein the Schottky gate electrode comprises: a lowermost portion which is co-planar with a first dielectric layer portion over the second layer; a middle portion which is co-planar with a second dielectric layer, the middle portion overlapping the lowermost portion; and an upper portion which is co-planar with a third dielectric layer, the upper portion overlapping the middle portion. Page 4 of 6 Application No. 14/108,042; Docket No.: 81531809US03; Conf. No. 1050 Office Action dated: Office Action Response dated
Ae d-t-eksime-in-aim- The m et hod as claimed in claim 8, wherein forming the dielectric layer structure comprises: forming the second dielectric layer; forming a well in the second dielectric layer in the region of the gate; forming the first dielectric layer over the second dielectric layer and into the well; removing a region of the first dielectric layer in the well; forming the third dielectric layer over the first dielectric layer, wherein the first dielectric layer portion is the only one of the first, second and third dielectric layers beneath the overlap of the middle portion over the lowermost portion.
Ak+4hebsk 4atdtsim- The method as claimed in claim 8, wherein the length of the overlap of the middle portion over the lowermost portion is at least twice the thickness of the first dielectric layer.
A GaN heter [[e] ojunction semiconductor device comprising: a substrate; a layer structure having a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between the substrate and the second layer; and a Schottky gate electrode and a first further electrode each conductively coupled to a different area of the e j 4 the Ga N hetero j unction semiconductor device, said Schottky gate electrode comprising a central region and an edge region, wherein the Schottky gate electrode comprises: a lowermost portion which is co-planar with a first dielectric layer portion over the second layer; a middle portion which is co-planar with a second dielectric layer, the middle portion overlapping the lowermost portion; and an upper portion which is co-planar with a third dielectric layer, the upper portion overlapping the middle portion.
A-dee e 4 IiA₄ The GaN hetero i unction semiconductor device as claimed in claim 1, wherein the first dielectric layer is over the second dielectric layer, and the second dielectric layer has a well in the region of the gate and in which the first dielectric layeris formed such that the first dielectric layer portion is the only one of the first, second and third dielectric layers beneath the overlap of the middle portion over the lowermost portion.
Ae e-The G aN heter oj unction semiconductor device as claimed in claim 1, wherein the first dielectric layer comprises an LPCVD layer, and the second and third dielectric layers comprise PEC V D layers.
(Current ly Amended) A-4 The GaNhh etero junction semiconductor device as claimed in claim 1, wherein the length of the overlap of the middle portion over the lowermost portion is at least twice the thickness of the first dielectric layer.
Aev A-lain zk4unis4 The GaN hetero i unc t ion semiconductor device as claimed in claim 1, wherein the thickness of the first dielectric layer is in the range 5 to 50 nm.
A e l4 4 -a 4 The GaN hetero j unction semiconductor device as claimed in claim 1, wherein the first layer comprises GaN and the second layer comprises AlGaN.
A method of manufacturing a semiconductor device comprising: providing a substrate carrying a layer structure having a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between the substrate and the second layer, the interface between the first layer and second layer defining a heterojunction; forming a dielectric layer structure over the second layer; forming a Schottky gate electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky gate electrode comprising a central region and an edge region, wherein the Schottky gate electrode comprises: a lowermost portion which is co-planar with a first dielectric layer portion over the second layer; a middle portion which is co-planar with a second dielectric layer, the middle portion overlapping the lowermost portion; and an upper portion which is co-planar with a third dielectric layer, the upper portion overlapping the middle portion. Page 4 of 6 Application No. 14/108,042; Docket No.: 81531809US03; Conf. No. 1050 Office Action dated: Office Action Response dated
Ae d-t-eksime-in-aim- The m et hod as claimed in claim 8, wherein forming the dielectric layer structure comprises: forming the second dielectric layer; forming a well in the second dielectric layer in the region of the gate; forming the first dielectric layer over the second dielectric layer and into the well; removing a region of the first dielectric layer in the well; forming the third dielectric layer over the first dielectric layer, wherein the first dielectric layer portion is the only one of the first, second and third dielectric layers beneath the overlap of the middle portion over the lowermost portion.
Ak+4hebsk 4atdtsim- The method as claimed in claim 8, wherein the length of the overlap of the middle portion over the lowermost portion is at least twice the thickness of the first dielectric layer.
A GaN heter [[e] ojunction semiconductor device comprising: a substrate; a layer structure having a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between the substrate and the second layer; and a Schottky gate electrode and a first further electrode each conductively coupled to a different area of the e j 4 the Ga N hetero j unction semiconductor device, said Schottky gate electrode comprising a central region and an edge region, wherein the Schottky gate electrode comprises: a lowermost portion which is co-planar with a first dielectric layer portion over the second layer; a middle portion which is co-planar with a second dielectric layer, the middle portion overlapping the lowermost portion; and an upper portion which is co-planar with a third dielectric layer, the upper portion overlapping the middle portion.
A-dee e 4 IiA₄ The GaN hetero i unction semiconductor device as claimed in claim 1, wherein the first dielectric layer is over the second dielectric layer, and the second dielectric layer has a well in the region of the gate and in which the first dielectric layeris formed such that the first dielectric layer portion is the only one of the first, second and third dielectric layers beneath the overlap of the middle portion over the lowermost portion.
Ae e-The G aN heter oj unction semiconductor device as claimed in claim 1, wherein the first dielectric layer comprises an LPCVD layer, and the second and third dielectric layers comprise PEC V D layers.
(Current ly Amended) A-4 The GaNhh etero junction semiconductor device as claimed in claim 1, wherein the length of the overlap of the middle portion over the lowermost portion is at least twice the thickness of the first dielectric layer.
Aev A-lain zk4unis4 The GaN hetero i unc t ion semiconductor device as claimed in claim 1, wherein the thickness of the first dielectric layer is in the range 5 to 50 nm.
A e l4 4 -a 4 The GaN hetero j unction semiconductor device as claimed in claim 1, wherein the first layer comprises GaN and the second layer comprises AlGaN.
A method of manufacturing a semiconductor device comprising: providing a substrate carrying a layer structure having a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between the substrate and the second layer, the interface between the first layer and second layer defining a heterojunction; forming a dielectric layer structure over the second layer; forming a Schottky gate electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky gate electrode comprising a central region and an edge region, wherein the Schottky gate electrode comprises: a lowermost portion which is co-planar with a first dielectric layer portion over the second layer; a middle portion which is co-planar with a second dielectric layer, the middle portion overlapping the lowermost portion; and an upper portion which is co-planar with a third dielectric layer, the upper portion overlapping the middle portion. Page 4 of 6 Application No. 14/108,042; Docket No.: 81531809US03; Conf. No. 1050 Office Action dated: Office Action Response dated
Ae d-t-eksime-in-aim- The m et hod as claimed in claim 8, wherein forming the dielectric layer structure comprises: forming the second dielectric layer; forming a well in the second dielectric layer in the region of the gate; forming the first dielectric layer over the second dielectric layer and into the well; removing a region of the first dielectric layer in the well; forming the third dielectric layer over the first dielectric layer, wherein the first dielectric layer portion is the only one of the first, second and third dielectric layers beneath the overlap of the middle portion over the lowermost portion.
Ak+4hebsk 4atdtsim- The method as claimed in claim 8, wherein the length of the overlap of the middle portion over the lowermost portion is at least twice the thickness of the first dielectric layer.
A GaN heter [[e] ojunction semiconductor device comprising: a substrate; a layer structure having a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between the substrate and the second layer; and a Schottky gate electrode and a first further electrode each conductively coupled to a different area of the e j 4 the Ga N hetero j unction semiconductor device, said Schottky gate electrode comprising a central region and an edge region, wherein the Schottky gate electrode comprises: a lowermost portion which is co-planar with a first dielectric layer portion over the second layer; a middle portion which is co-planar with a second dielectric layer, the middle portion overlapping the lowermost portion; and an upper portion which is co-planar with a third dielectric layer, the upper portion overlapping the middle portion.
A-dee e 4 IiA₄ The GaN hetero i unction semiconductor device as claimed in claim 1, wherein the first dielectric layer is over the second dielectric layer, and the second dielectric layer has a well in the region of the gate and in which the first dielectric layeris formed such that the first dielectric layer portion is the only one of the first, second and third dielectric layers beneath the overlap of the middle portion over the lowermost portion.
Ae e-The G aN heter oj unction semiconductor device as claimed in claim 1, wherein the first dielectric layer comprises an LPCVD layer, and the second and third dielectric layers comprise PEC V D layers.
(Current ly Amended) A-4 The GaNhh etero junction semiconductor device as claimed in claim 1, wherein the length of the overlap of the middle portion over the lowermost portion is at least twice the thickness of the first dielectric layer.
Aev A-lain zk4unis4 The GaN hetero i unc t ion semiconductor device as claimed in claim 1, wherein the thickness of the first dielectric layer is in the range 5 to 50 nm.
A e l4 4 -a 4 The GaN hetero j unction semiconductor device as claimed in claim 1, wherein the first layer comprises GaN and the second layer comprises AlGaN.
A method of manufacturing a semiconductor device comprising: providing a substrate carrying a layer structure having a first layer having a first bandgap and a second layer having a second bandgap, wherein the first layer is located between the substrate and the second layer, the interface between the first layer and second layer defining a heterojunction; forming a dielectric layer structure over the second layer; forming a Schottky gate electrode and a first further electrode each conductively coupled to a different area of the heterojunction, said Schottky gate electrode comprising a central region and an edge region, wherein the Schottky gate electrode comprises: a lowermost portion which is co-planar with a first dielectric layer portion over the second layer; a middle portion which is co-planar with a second dielectric layer, the middle portion overlapping the lowermost portion; and an upper portion which is co-planar with a third dielectric layer, the upper portion overlapping the middle portion. Page 4 of 6 Application No. 14/108,042; Docket No.: 81531809US03; Conf. No. 1050 Office Action dated: Office Action Response dated
Ae d-t-eksime-in-aim- The m et hod as claimed in claim 8, wherein forming the dielectric layer structure comprises: forming the second dielectric layer; forming a well in the second dielectric layer in the region of the gate; forming the first dielectric layer over the second dielectric layer and into the well; removing a region of the first dielectric layer in the well; forming the third dielectric layer over the first dielectric layer, wherein the first dielectric layer portion is the only one of the first, second and third dielectric layers beneath the overlap of the middle portion over the lowermost portion.
Ak+4hebsk 4atdtsim- The method as claimed in claim 8, wherein the length of the overlap of the middle portion over the lowermost portion is at least twice the thickness of the first dielectric layer.
