Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1
Figure 1: Structure of prior art HEMTs showing monolithic gates. 15
Figure 2
Figure 2 Structure illustrating an embodiment of the present invention showing numerous subgates comprising the gate of the device.
Figure 3
process tool top view
Figure 3 Example of subgate profiles (a-d) and top views (e-g).
Figure 4
process tool top view
Figure 4: Top view of a HEMT using numerous subgates and the section A-A shown in figure 5.
Figure 5
Figure 5: Section A-A view of HEMT device showing a subgate. 20 [0008] The following papers are incorporated by reference as though fully set forth herein:
Claims
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
3 independent · 11 dependent
1
IndependentGaNbarrier layerHEMT (High Electron Mobility Transistor) with stitched subgate array
A HEM T device comprising: a channel layer and a barrier layer; a source, gate and drain disposed on the barrier layer; wherein the gate comprises a plurality of physically distinct subgates arranged in a plurality of rows, each row having a plurality of subgates; wherein the subgates are electrically connected into at least one group; and wherein the subgates in each row are staggered relative to an adjacent row of subgates such that there is at least one subgate in cash row that when the sub ate is projected tivataTd permendicula] y relative to the adjace=t row projection of the subgate wou kd overlap with at least one subgate and an opening beiween subg ates in the adjacent row.
2
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1 wherein the subgates are in rows separated by approximately 0.1 micrometer and each subgate has an area, when viewed from above, that is at least the area of a 0.05 micrometer radius circle.
4
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1 wherein the subgates are electrically connected with a field plate.
5
Dependent← claim 1Group III-V materialHEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1 wherein the channel layer comprises a Group I II-V material.
6
Dependent← claim 1GaNHEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1 wherein the channel layer comprises GaN.
8
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein each row defines a first gap between subgates in the row, the gap being misaligned with a second gap in the adjacent row.
9
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein each row includes at least three subgates.
10
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein each row includes at least four subgates.
11
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein each row extends along a direction, and each subgate extends along the direction beyond an adjacent subgate in an adjacent row.
12
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein the projection of the subgate would overlap with at least two subgates and an opening between subgates in the adjacent row.
13
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein the subgates in each row are staggered relative to an adjacent row of subgates such that there are least two subgates in each row that when the two subgates are projected toward and perpendicularly relative to the adjacent row, the projection of the two subgates would overlap with at least three subgates and two openings between subgates in the adjacent row.
14
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein the subgates in each row are staggered relative to an adjacent row of subgates such that there are least three subgates in each row that when the three subgates are projected toward and perpendicularly relative to the adjacent row, the projection of the three subgates would overlap with at least five subgates and three openings between subgates in the adjacent row. -4-
3
Independent
canceled
7
IndependentGaNbarrier layerHEMT (High Electron Mobility Transistor) with stitched subgate array
A H E MT device comprising: a channel layer and a barrier layer; a source, gate and drain disposed on the barrier layer; wherein the source has a length and the source is spaced apart from the drain by a -2- width; wherein the gate comprises a plurality of physically distinct subgates arranged in a plurality of rows, each row having a plurality of subgates; wherein the subgates in each row are staggered relative to an adjacent row of subgates such that there is at least one subgate in each row that when tie subgate is projected toward and perpendicularly relative to the adjacent row, the projection of the subgate wouldoverlap xwi i at least one su bgate and an oenig b etween subgates iin the adjacent row; wherein the plurality of rows are disposed between the source and the drain.
Device structures
Layer stacks claimed or described, ordered top of device to substrate.
HEMT (High Electron Mobility Transistor) with stitched subgate array
barrier layerbarrier
GaNchannel
bufferlayerbuffer layer
nucleationlayernucleation layer
substratesubstrate
Materials
Materials described outside the worked examples.
GaN
Channel Layer
barrier layer
Barrier Layer
Why these are connected
Related documents with shared materials, methods, properties, or citations.
Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1
Figure 1: Structure of prior art HEMTs showing monolithic gates. 15
Figure 2
Figure 2 Structure illustrating an embodiment of the present invention showing numerous subgates comprising the gate of the device.
Figure 3
process tool top view
Figure 3 Example of subgate profiles (a-d) and top views (e-g).
Figure 4
process tool top view
Figure 4: Top view of a HEMT using numerous subgates and the section A-A shown in figure 5.
Figure 5
Figure 5: Section A-A view of HEMT device showing a subgate. 20 [0008] The following papers are incorporated by reference as though fully set forth herein:
Claims
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
3 independent · 11 dependent
1
IndependentGaNbarrier layerHEMT (High Electron Mobility Transistor) with stitched subgate array
A HEM T device comprising: a channel layer and a barrier layer; a source, gate and drain disposed on the barrier layer; wherein the gate comprises a plurality of physically distinct subgates arranged in a plurality of rows, each row having a plurality of subgates; wherein the subgates are electrically connected into at least one group; and wherein the subgates in each row are staggered relative to an adjacent row of subgates such that there is at least one subgate in cash row that when the sub ate is projected tivataTd permendicula] y relative to the adjace=t row projection of the subgate wou kd overlap with at least one subgate and an opening beiween subg ates in the adjacent row.
2
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1 wherein the subgates are in rows separated by approximately 0.1 micrometer and each subgate has an area, when viewed from above, that is at least the area of a 0.05 micrometer radius circle.
4
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1 wherein the subgates are electrically connected with a field plate.
5
Dependent← claim 1Group III-V materialHEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1 wherein the channel layer comprises a Group I II-V material.
6
Dependent← claim 1GaNHEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1 wherein the channel layer comprises GaN.
8
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein each row defines a first gap between subgates in the row, the gap being misaligned with a second gap in the adjacent row.
9
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein each row includes at least three subgates.
10
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein each row includes at least four subgates.
11
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein each row extends along a direction, and each subgate extends along the direction beyond an adjacent subgate in an adjacent row.
12
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein the projection of the subgate would overlap with at least two subgates and an opening between subgates in the adjacent row.
13
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein the subgates in each row are staggered relative to an adjacent row of subgates such that there are least two subgates in each row that when the two subgates are projected toward and perpendicularly relative to the adjacent row, the projection of the two subgates would overlap with at least three subgates and two openings between subgates in the adjacent row.
14
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein the subgates in each row are staggered relative to an adjacent row of subgates such that there are least three subgates in each row that when the three subgates are projected toward and perpendicularly relative to the adjacent row, the projection of the three subgates would overlap with at least five subgates and three openings between subgates in the adjacent row. -4-
3
Independent
canceled
7
IndependentGaNbarrier layerHEMT (High Electron Mobility Transistor) with stitched subgate array
A H E MT device comprising: a channel layer and a barrier layer; a source, gate and drain disposed on the barrier layer; wherein the source has a length and the source is spaced apart from the drain by a -2- width; wherein the gate comprises a plurality of physically distinct subgates arranged in a plurality of rows, each row having a plurality of subgates; wherein the subgates in each row are staggered relative to an adjacent row of subgates such that there is at least one subgate in each row that when tie subgate is projected toward and perpendicularly relative to the adjacent row, the projection of the subgate wouldoverlap xwi i at least one su bgate and an oenig b etween subgates iin the adjacent row; wherein the plurality of rows are disposed between the source and the drain.
Device structures
Layer stacks claimed or described, ordered top of device to substrate.
HEMT (High Electron Mobility Transistor) with stitched subgate array
barrier layerbarrier
GaNchannel
bufferlayerbuffer layer
nucleationlayernucleation layer
substratesubstrate
Materials
Materials described outside the worked examples.
GaN
Channel Layer
barrier layer
Barrier Layer
Why these are connected
Related documents with shared materials, methods, properties, or citations.
Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1
Figure 1: Structure of prior art HEMTs showing monolithic gates. 15
Figure 2
Figure 2 Structure illustrating an embodiment of the present invention showing numerous subgates comprising the gate of the device.
Figure 3
process tool top view
Figure 3 Example of subgate profiles (a-d) and top views (e-g).
Figure 4
process tool top view
Figure 4: Top view of a HEMT using numerous subgates and the section A-A shown in figure 5.
Figure 5
Figure 5: Section A-A view of HEMT device showing a subgate. 20 [0008] The following papers are incorporated by reference as though fully set forth herein:
Claims
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
3 independent · 11 dependent
1
IndependentGaNbarrier layerHEMT (High Electron Mobility Transistor) with stitched subgate array
A HEM T device comprising: a channel layer and a barrier layer; a source, gate and drain disposed on the barrier layer; wherein the gate comprises a plurality of physically distinct subgates arranged in a plurality of rows, each row having a plurality of subgates; wherein the subgates are electrically connected into at least one group; and wherein the subgates in each row are staggered relative to an adjacent row of subgates such that there is at least one subgate in cash row that when the sub ate is projected tivataTd permendicula] y relative to the adjace=t row projection of the subgate wou kd overlap with at least one subgate and an opening beiween subg ates in the adjacent row.
2
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1 wherein the subgates are in rows separated by approximately 0.1 micrometer and each subgate has an area, when viewed from above, that is at least the area of a 0.05 micrometer radius circle.
4
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1 wherein the subgates are electrically connected with a field plate.
5
Dependent← claim 1Group III-V materialHEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1 wherein the channel layer comprises a Group I II-V material.
6
Dependent← claim 1GaNHEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1 wherein the channel layer comprises GaN.
8
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein each row defines a first gap between subgates in the row, the gap being misaligned with a second gap in the adjacent row.
9
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein each row includes at least three subgates.
10
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein each row includes at least four subgates.
11
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein each row extends along a direction, and each subgate extends along the direction beyond an adjacent subgate in an adjacent row.
12
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein the projection of the subgate would overlap with at least two subgates and an opening between subgates in the adjacent row.
13
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein the subgates in each row are staggered relative to an adjacent row of subgates such that there are least two subgates in each row that when the two subgates are projected toward and perpendicularly relative to the adjacent row, the projection of the two subgates would overlap with at least three subgates and two openings between subgates in the adjacent row.
14
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein the subgates in each row are staggered relative to an adjacent row of subgates such that there are least three subgates in each row that when the three subgates are projected toward and perpendicularly relative to the adjacent row, the projection of the three subgates would overlap with at least five subgates and three openings between subgates in the adjacent row. -4-
3
Independent
canceled
7
IndependentGaNbarrier layerHEMT (High Electron Mobility Transistor) with stitched subgate array
A H E MT device comprising: a channel layer and a barrier layer; a source, gate and drain disposed on the barrier layer; wherein the source has a length and the source is spaced apart from the drain by a -2- width; wherein the gate comprises a plurality of physically distinct subgates arranged in a plurality of rows, each row having a plurality of subgates; wherein the subgates in each row are staggered relative to an adjacent row of subgates such that there is at least one subgate in each row that when tie subgate is projected toward and perpendicularly relative to the adjacent row, the projection of the subgate wouldoverlap xwi i at least one su bgate and an oenig b etween subgates iin the adjacent row; wherein the plurality of rows are disposed between the source and the drain.
Device structures
Layer stacks claimed or described, ordered top of device to substrate.
HEMT (High Electron Mobility Transistor) with stitched subgate array
barrier layerbarrier
GaNchannel
bufferlayerbuffer layer
nucleationlayernucleation layer
substratesubstrate
Materials
Materials described outside the worked examples.
GaN
Channel Layer
barrier layer
Barrier Layer
Why these are connected
Related documents with shared materials, methods, properties, or citations.
Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1
Figure 1: Structure of prior art HEMTs showing monolithic gates. 15
Figure 2
Figure 2 Structure illustrating an embodiment of the present invention showing numerous subgates comprising the gate of the device.
Figure 3
process tool top view
Figure 3 Example of subgate profiles (a-d) and top views (e-g).
Figure 4
process tool top view
Figure 4: Top view of a HEMT using numerous subgates and the section A-A shown in figure 5.
Figure 5
Figure 5: Section A-A view of HEMT device showing a subgate. 20 [0008] The following papers are incorporated by reference as though fully set forth herein:
Claims
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
3 independent · 11 dependent
1
IndependentGaNbarrier layerHEMT (High Electron Mobility Transistor) with stitched subgate array
A HEM T device comprising: a channel layer and a barrier layer; a source, gate and drain disposed on the barrier layer; wherein the gate comprises a plurality of physically distinct subgates arranged in a plurality of rows, each row having a plurality of subgates; wherein the subgates are electrically connected into at least one group; and wherein the subgates in each row are staggered relative to an adjacent row of subgates such that there is at least one subgate in cash row that when the sub ate is projected tivataTd permendicula] y relative to the adjace=t row projection of the subgate wou kd overlap with at least one subgate and an opening beiween subg ates in the adjacent row.
2
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1 wherein the subgates are in rows separated by approximately 0.1 micrometer and each subgate has an area, when viewed from above, that is at least the area of a 0.05 micrometer radius circle.
4
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1 wherein the subgates are electrically connected with a field plate.
5
Dependent← claim 1Group III-V materialHEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1 wherein the channel layer comprises a Group I II-V material.
6
Dependent← claim 1GaNHEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1 wherein the channel layer comprises GaN.
8
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein each row defines a first gap between subgates in the row, the gap being misaligned with a second gap in the adjacent row.
9
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein each row includes at least three subgates.
10
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein each row includes at least four subgates.
11
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein each row extends along a direction, and each subgate extends along the direction beyond an adjacent subgate in an adjacent row.
12
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein the projection of the subgate would overlap with at least two subgates and an opening between subgates in the adjacent row.
13
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein the subgates in each row are staggered relative to an adjacent row of subgates such that there are least two subgates in each row that when the two subgates are projected toward and perpendicularly relative to the adjacent row, the projection of the two subgates would overlap with at least three subgates and two openings between subgates in the adjacent row.
14
Dependent← claim 1HEMT (High Electron Mobility Transistor) with stitched subgate array
The device of claim 1, wherein the subgates in each row are staggered relative to an adjacent row of subgates such that there are least three subgates in each row that when the three subgates are projected toward and perpendicularly relative to the adjacent row, the projection of the three subgates would overlap with at least five subgates and three openings between subgates in the adjacent row. -4-
3
Independent
canceled
7
IndependentGaNbarrier layerHEMT (High Electron Mobility Transistor) with stitched subgate array
A H E MT device comprising: a channel layer and a barrier layer; a source, gate and drain disposed on the barrier layer; wherein the source has a length and the source is spaced apart from the drain by a -2- width; wherein the gate comprises a plurality of physically distinct subgates arranged in a plurality of rows, each row having a plurality of subgates; wherein the subgates in each row are staggered relative to an adjacent row of subgates such that there is at least one subgate in each row that when tie subgate is projected toward and perpendicularly relative to the adjacent row, the projection of the subgate wouldoverlap xwi i at least one su bgate and an oenig b etween subgates iin the adjacent row; wherein the plurality of rows are disposed between the source and the drain.
Device structures
Layer stacks claimed or described, ordered top of device to substrate.
HEMT (High Electron Mobility Transistor) with stitched subgate array
barrier layerbarrier
GaNchannel
bufferlayerbuffer layer
nucleationlayernucleation layer
substratesubstrate
Materials
Materials described outside the worked examples.
GaN
Channel Layer
barrier layer
Barrier Layer
Why these are connected
Related documents with shared materials, methods, properties, or citations.