Patent
US 9,466,686GRAPHENE DEVICES WITH LOCAL DUAL GATES
Zhihong Chen
US
Copyright © 2026 Matter42. All rights reserved.
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US 9,466,686Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows an exemplary tunable band gap electronic device 100, such as a FET device, in accordance with an illustrative embodiment of the present invention. …
FIGS. 2-20 illustrate various fabrication steps that are employed in the present invention in fabricating the electronic device 100. As will be described …
FIG. 3. Although
FIG. 4 shows a third top-down view of an electronic device in accordance with an SVG …
FIG. 5. A trench length (labeled as "L") formed in at least one of the bottom gates 196 i s approximately one (1) nm to a pproximately one (1) pm. A film of …
FIG. 6. The film of polycrystalline silicon 195 has a t hickness of approximately two hundred (200) nm to a pproximately seven hundred (700) nm. The polysilicon …
FIG. 7. CMP is a process that is used for the planarization of semiconductor wafers. CMP takes advantages of the synergetic effect of both physical and chemical …
FIG. 8. After etching, the device 100 is subjected to ion implantation to form source and drain regions 150 as shown in
FIG. 9. An ion implantation process is performed to implant electrical dopants into the exposed portions of the bottom gates 196, that is, the 25 portions that …
FIG. 10. The next step is to create an n-type poly in the first transistor 175. In order to create the first transistor 175 with the n-type poly, the device 100 …
FIG. 11. The lithography process further includes exposing the photoresist 190 to a pattern of radiation, and developing the pattern into the photoresist 190 …
FIG. 12. In one embodiment, an n-type material such as phosphorus (P) or arsenic (As) is implanted to the local first bottom gate 115 of the first transistor …
FIG. 13. Following the implantation step, the device 100 is subjected to a rapid thermal anneal (RTA) process at, for example, a pproximately one thousand …
FIG. 14 shows a thirteenth top-down view of an electronic device in accordance 10 with an illustrative embodiment of the present invention.
FIG. 15 shows a fourteenth top-down view of an electronic device in accordance with an illustrative embodiment of the present invention.
FIG. 16. The photolithography process includes lift-off to pattern the top local gates 135, 160, 170. 10 A photoresist layer 190 is then deposited to cover the …
FIG. 17. However, the dopant ion can either be an n-type or p-type dopant. The photoresist layer 190 is then removed utilizing a conventional stripping 15 …
FIG. 18. The lithography process further includes exposing the photoresist 190 to a pattern of radiation, and developing the pattern into the photoresist 190 …
FIG. 19. After the formation of the source and drain regions 150, contacts 145 are formed for each source/drain region 150 as shown in
FIG. 20.
FIG. 21 illustrates another embodiment of a device 200. Device 200 is similar to device 100 with the exception that all the gates are doped with n-type or …
FIG. 22 illustrates another embodiment of a device 300. Device 300 is similar to device 100 with the exception that all of the local gates 315, 340, 355, 360, …
FIG. 23 shows yet another alternative electronic device in accordance with an illustrative embodiment of the present invention. YO R₉₂₀₁₀₀₄₁₂US₄ 5 Detailed …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming an electronic device comprising: forming an insulator; embedding a local first gate in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator; depositing a first dielectric layer over the first gate and insulator; forming a channel comprising a bilayer graphene layer formed on the first dielectric layer, wherein the first dielectric layer provides a substantially flat surface on which the channel is formed; depositing a second dielectric layer over the bilayer graphene layer, wherein the bilaver graphene la y er provides a substantially flat surface on which the second dielectric la y er is deposited; and forming a local second gate over the second dielectric layer, each of the local first and second gates configured to be capacitively coupled to the channel of the bilayer graphene layer; wherein the local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer; and wherein the local first gate is controllable independent of the local second gate.
The method of claim 1, wherein the first pair of gates operates as gates of a first transistor.
The method of claim 1, wherein at least one of the first and second dielectric layers comprises one or more of aluminum oxide and hafnium oxide. 3 Attorney Docket No. Y O R₉₂₀₁₀₀₄₁₂US₄
The method of claim 1, wherein the insulator is a first material type and the first dielectric layer is a second material type different than the first material type.
The method of claim 1, wherein the local first gate and the local second gate are formed of a same material type.
The method of claim 1, further comprising forming source and drain regions connected by the channel.
The method of claim 1, wherein forming the channel comprises growing the bilayer graphene layer using solid state graphitization.
A method of forming an electronic device comprising: forming an insulator; embedding a local first gate in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator; depositing a first dielectric layer over the first gate and insulator; forming a channel comprising a bilayer graphene layer formed on the first dielectric layer; depositing a second dielectric layer over the bilayer graphene layer; and forming a local second gate over the second dielectric layer, each of the local first and second gates configured to be capacitively coupled to the channel of the bilayer graphene layer; 4 Attorney Docket No. Y O R₉₂₀₁₀₀₄₁₂US₄ wherein the local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer; and wherein the local first gate is controllable independent of the local second gate.
The method of claim 19, wherein the electronic device comprises an integrated circuit. 5
Layer stacks claimed or described, ordered top of device to substrate.
dual-gate bilayer graphene field-effect transistor (first transistor)
Materials described outside the worked examples.
bilayer graphene
metal
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 shows an exemplary tunable band gap electronic device 100, such as a FET device, in accordance with an illustrative embodiment of the present invention. …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0–300 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,466,686Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows an exemplary tunable band gap electronic device 100, such as a FET device, in accordance with an illustrative embodiment of the present invention. …
FIGS. 2-20 illustrate various fabrication steps that are employed in the present invention in fabricating the electronic device 100. As will be described …
FIG. 3. Although
FIG. 4 shows a third top-down view of an electronic device in accordance with an SVG …
FIG. 5. A trench length (labeled as "L") formed in at least one of the bottom gates 196 i s approximately one (1) nm to a pproximately one (1) pm. A film of …
FIG. 6. The film of polycrystalline silicon 195 has a t hickness of approximately two hundred (200) nm to a pproximately seven hundred (700) nm. The polysilicon …
FIG. 7. CMP is a process that is used for the planarization of semiconductor wafers. CMP takes advantages of the synergetic effect of both physical and chemical …
FIG. 8. After etching, the device 100 is subjected to ion implantation to form source and drain regions 150 as shown in
FIG. 9. An ion implantation process is performed to implant electrical dopants into the exposed portions of the bottom gates 196, that is, the 25 portions that …
FIG. 10. The next step is to create an n-type poly in the first transistor 175. In order to create the first transistor 175 with the n-type poly, the device 100 …
FIG. 11. The lithography process further includes exposing the photoresist 190 to a pattern of radiation, and developing the pattern into the photoresist 190 …
FIG. 12. In one embodiment, an n-type material such as phosphorus (P) or arsenic (As) is implanted to the local first bottom gate 115 of the first transistor …
FIG. 13. Following the implantation step, the device 100 is subjected to a rapid thermal anneal (RTA) process at, for example, a pproximately one thousand …
FIG. 14 shows a thirteenth top-down view of an electronic device in accordance 10 with an illustrative embodiment of the present invention.
FIG. 15 shows a fourteenth top-down view of an electronic device in accordance with an illustrative embodiment of the present invention.
FIG. 16. The photolithography process includes lift-off to pattern the top local gates 135, 160, 170. 10 A photoresist layer 190 is then deposited to cover the …
FIG. 17. However, the dopant ion can either be an n-type or p-type dopant. The photoresist layer 190 is then removed utilizing a conventional stripping 15 …
FIG. 18. The lithography process further includes exposing the photoresist 190 to a pattern of radiation, and developing the pattern into the photoresist 190 …
FIG. 19. After the formation of the source and drain regions 150, contacts 145 are formed for each source/drain region 150 as shown in
FIG. 20.
FIG. 21 illustrates another embodiment of a device 200. Device 200 is similar to device 100 with the exception that all the gates are doped with n-type or …
FIG. 22 illustrates another embodiment of a device 300. Device 300 is similar to device 100 with the exception that all of the local gates 315, 340, 355, 360, …
FIG. 23 shows yet another alternative electronic device in accordance with an illustrative embodiment of the present invention. YO R₉₂₀₁₀₀₄₁₂US₄ 5 Detailed …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming an electronic device comprising: forming an insulator; embedding a local first gate in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator; depositing a first dielectric layer over the first gate and insulator; forming a channel comprising a bilayer graphene layer formed on the first dielectric layer, wherein the first dielectric layer provides a substantially flat surface on which the channel is formed; depositing a second dielectric layer over the bilayer graphene layer, wherein the bilaver graphene la y er provides a substantially flat surface on which the second dielectric la y er is deposited; and forming a local second gate over the second dielectric layer, each of the local first and second gates configured to be capacitively coupled to the channel of the bilayer graphene layer; wherein the local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer; and wherein the local first gate is controllable independent of the local second gate.
The method of claim 1, wherein the first pair of gates operates as gates of a first transistor.
The method of claim 1, wherein at least one of the first and second dielectric layers comprises one or more of aluminum oxide and hafnium oxide. 3 Attorney Docket No. Y O R₉₂₀₁₀₀₄₁₂US₄
The method of claim 1, wherein the insulator is a first material type and the first dielectric layer is a second material type different than the first material type.
The method of claim 1, wherein the local first gate and the local second gate are formed of a same material type.
The method of claim 1, further comprising forming source and drain regions connected by the channel.
The method of claim 1, wherein forming the channel comprises growing the bilayer graphene layer using solid state graphitization.
A method of forming an electronic device comprising: forming an insulator; embedding a local first gate in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator; depositing a first dielectric layer over the first gate and insulator; forming a channel comprising a bilayer graphene layer formed on the first dielectric layer; depositing a second dielectric layer over the bilayer graphene layer; and forming a local second gate over the second dielectric layer, each of the local first and second gates configured to be capacitively coupled to the channel of the bilayer graphene layer; 4 Attorney Docket No. Y O R₉₂₀₁₀₀₄₁₂US₄ wherein the local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer; and wherein the local first gate is controllable independent of the local second gate.
The method of claim 19, wherein the electronic device comprises an integrated circuit. 5
Layer stacks claimed or described, ordered top of device to substrate.
dual-gate bilayer graphene field-effect transistor (first transistor)
Materials described outside the worked examples.
bilayer graphene
metal
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 shows an exemplary tunable band gap electronic device 100, such as a FET device, in accordance with an illustrative embodiment of the present invention. …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0–300 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,466,686Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows an exemplary tunable band gap electronic device 100, such as a FET device, in accordance with an illustrative embodiment of the present invention. …
FIGS. 2-20 illustrate various fabrication steps that are employed in the present invention in fabricating the electronic device 100. As will be described …
FIG. 3. Although
FIG. 4 shows a third top-down view of an electronic device in accordance with an SVG …
FIG. 5. A trench length (labeled as "L") formed in at least one of the bottom gates 196 i s approximately one (1) nm to a pproximately one (1) pm. A film of …
FIG. 6. The film of polycrystalline silicon 195 has a t hickness of approximately two hundred (200) nm to a pproximately seven hundred (700) nm. The polysilicon …
FIG. 7. CMP is a process that is used for the planarization of semiconductor wafers. CMP takes advantages of the synergetic effect of both physical and chemical …
FIG. 8. After etching, the device 100 is subjected to ion implantation to form source and drain regions 150 as shown in
FIG. 9. An ion implantation process is performed to implant electrical dopants into the exposed portions of the bottom gates 196, that is, the 25 portions that …
FIG. 10. The next step is to create an n-type poly in the first transistor 175. In order to create the first transistor 175 with the n-type poly, the device 100 …
FIG. 11. The lithography process further includes exposing the photoresist 190 to a pattern of radiation, and developing the pattern into the photoresist 190 …
FIG. 12. In one embodiment, an n-type material such as phosphorus (P) or arsenic (As) is implanted to the local first bottom gate 115 of the first transistor …
FIG. 13. Following the implantation step, the device 100 is subjected to a rapid thermal anneal (RTA) process at, for example, a pproximately one thousand …
FIG. 14 shows a thirteenth top-down view of an electronic device in accordance 10 with an illustrative embodiment of the present invention.
FIG. 15 shows a fourteenth top-down view of an electronic device in accordance with an illustrative embodiment of the present invention.
FIG. 16. The photolithography process includes lift-off to pattern the top local gates 135, 160, 170. 10 A photoresist layer 190 is then deposited to cover the …
FIG. 17. However, the dopant ion can either be an n-type or p-type dopant. The photoresist layer 190 is then removed utilizing a conventional stripping 15 …
FIG. 18. The lithography process further includes exposing the photoresist 190 to a pattern of radiation, and developing the pattern into the photoresist 190 …
FIG. 19. After the formation of the source and drain regions 150, contacts 145 are formed for each source/drain region 150 as shown in
FIG. 20.
FIG. 21 illustrates another embodiment of a device 200. Device 200 is similar to device 100 with the exception that all the gates are doped with n-type or …
FIG. 22 illustrates another embodiment of a device 300. Device 300 is similar to device 100 with the exception that all of the local gates 315, 340, 355, 360, …
FIG. 23 shows yet another alternative electronic device in accordance with an illustrative embodiment of the present invention. YO R₉₂₀₁₀₀₄₁₂US₄ 5 Detailed …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming an electronic device comprising: forming an insulator; embedding a local first gate in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator; depositing a first dielectric layer over the first gate and insulator; forming a channel comprising a bilayer graphene layer formed on the first dielectric layer, wherein the first dielectric layer provides a substantially flat surface on which the channel is formed; depositing a second dielectric layer over the bilayer graphene layer, wherein the bilaver graphene la y er provides a substantially flat surface on which the second dielectric la y er is deposited; and forming a local second gate over the second dielectric layer, each of the local first and second gates configured to be capacitively coupled to the channel of the bilayer graphene layer; wherein the local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer; and wherein the local first gate is controllable independent of the local second gate.
The method of claim 1, wherein the first pair of gates operates as gates of a first transistor.
The method of claim 1, wherein at least one of the first and second dielectric layers comprises one or more of aluminum oxide and hafnium oxide. 3 Attorney Docket No. Y O R₉₂₀₁₀₀₄₁₂US₄
The method of claim 1, wherein the insulator is a first material type and the first dielectric layer is a second material type different than the first material type.
The method of claim 1, wherein the local first gate and the local second gate are formed of a same material type.
The method of claim 1, further comprising forming source and drain regions connected by the channel.
The method of claim 1, wherein forming the channel comprises growing the bilayer graphene layer using solid state graphitization.
A method of forming an electronic device comprising: forming an insulator; embedding a local first gate in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator; depositing a first dielectric layer over the first gate and insulator; forming a channel comprising a bilayer graphene layer formed on the first dielectric layer; depositing a second dielectric layer over the bilayer graphene layer; and forming a local second gate over the second dielectric layer, each of the local first and second gates configured to be capacitively coupled to the channel of the bilayer graphene layer; 4 Attorney Docket No. Y O R₉₂₀₁₀₀₄₁₂US₄ wherein the local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer; and wherein the local first gate is controllable independent of the local second gate.
The method of claim 19, wherein the electronic device comprises an integrated circuit. 5
Layer stacks claimed or described, ordered top of device to substrate.
dual-gate bilayer graphene field-effect transistor (first transistor)
Materials described outside the worked examples.
bilayer graphene
metal
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 shows an exemplary tunable band gap electronic device 100, such as a FET device, in accordance with an illustrative embodiment of the present invention. …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0–300 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,466,686Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows an exemplary tunable band gap electronic device 100, such as a FET device, in accordance with an illustrative embodiment of the present invention. …
FIGS. 2-20 illustrate various fabrication steps that are employed in the present invention in fabricating the electronic device 100. As will be described …
FIG. 3. Although
FIG. 4 shows a third top-down view of an electronic device in accordance with an SVG …
FIG. 5. A trench length (labeled as "L") formed in at least one of the bottom gates 196 i s approximately one (1) nm to a pproximately one (1) pm. A film of …
FIG. 6. The film of polycrystalline silicon 195 has a t hickness of approximately two hundred (200) nm to a pproximately seven hundred (700) nm. The polysilicon …
FIG. 7. CMP is a process that is used for the planarization of semiconductor wafers. CMP takes advantages of the synergetic effect of both physical and chemical …
FIG. 8. After etching, the device 100 is subjected to ion implantation to form source and drain regions 150 as shown in
FIG. 9. An ion implantation process is performed to implant electrical dopants into the exposed portions of the bottom gates 196, that is, the 25 portions that …
FIG. 10. The next step is to create an n-type poly in the first transistor 175. In order to create the first transistor 175 with the n-type poly, the device 100 …
FIG. 11. The lithography process further includes exposing the photoresist 190 to a pattern of radiation, and developing the pattern into the photoresist 190 …
FIG. 12. In one embodiment, an n-type material such as phosphorus (P) or arsenic (As) is implanted to the local first bottom gate 115 of the first transistor …
FIG. 13. Following the implantation step, the device 100 is subjected to a rapid thermal anneal (RTA) process at, for example, a pproximately one thousand …
FIG. 14 shows a thirteenth top-down view of an electronic device in accordance 10 with an illustrative embodiment of the present invention.
FIG. 15 shows a fourteenth top-down view of an electronic device in accordance with an illustrative embodiment of the present invention.
FIG. 16. The photolithography process includes lift-off to pattern the top local gates 135, 160, 170. 10 A photoresist layer 190 is then deposited to cover the …
FIG. 17. However, the dopant ion can either be an n-type or p-type dopant. The photoresist layer 190 is then removed utilizing a conventional stripping 15 …
FIG. 18. The lithography process further includes exposing the photoresist 190 to a pattern of radiation, and developing the pattern into the photoresist 190 …
FIG. 19. After the formation of the source and drain regions 150, contacts 145 are formed for each source/drain region 150 as shown in
FIG. 20.
FIG. 21 illustrates another embodiment of a device 200. Device 200 is similar to device 100 with the exception that all the gates are doped with n-type or …
FIG. 22 illustrates another embodiment of a device 300. Device 300 is similar to device 100 with the exception that all of the local gates 315, 340, 355, 360, …
FIG. 23 shows yet another alternative electronic device in accordance with an illustrative embodiment of the present invention. YO R₉₂₀₁₀₀₄₁₂US₄ 5 Detailed …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming an electronic device comprising: forming an insulator; embedding a local first gate in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator; depositing a first dielectric layer over the first gate and insulator; forming a channel comprising a bilayer graphene layer formed on the first dielectric layer, wherein the first dielectric layer provides a substantially flat surface on which the channel is formed; depositing a second dielectric layer over the bilayer graphene layer, wherein the bilaver graphene la y er provides a substantially flat surface on which the second dielectric la y er is deposited; and forming a local second gate over the second dielectric layer, each of the local first and second gates configured to be capacitively coupled to the channel of the bilayer graphene layer; wherein the local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer; and wherein the local first gate is controllable independent of the local second gate.
The method of claim 1, wherein the first pair of gates operates as gates of a first transistor.
The method of claim 1, wherein at least one of the first and second dielectric layers comprises one or more of aluminum oxide and hafnium oxide. 3 Attorney Docket No. Y O R₉₂₀₁₀₀₄₁₂US₄
The method of claim 1, wherein the insulator is a first material type and the first dielectric layer is a second material type different than the first material type.
The method of claim 1, wherein the local first gate and the local second gate are formed of a same material type.
The method of claim 1, further comprising forming source and drain regions connected by the channel.
The method of claim 1, wherein forming the channel comprises growing the bilayer graphene layer using solid state graphitization.
A method of forming an electronic device comprising: forming an insulator; embedding a local first gate in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator; depositing a first dielectric layer over the first gate and insulator; forming a channel comprising a bilayer graphene layer formed on the first dielectric layer; depositing a second dielectric layer over the bilayer graphene layer; and forming a local second gate over the second dielectric layer, each of the local first and second gates configured to be capacitively coupled to the channel of the bilayer graphene layer; 4 Attorney Docket No. Y O R₉₂₀₁₀₀₄₁₂US₄ wherein the local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer; and wherein the local first gate is controllable independent of the local second gate.
The method of claim 19, wherein the electronic device comprises an integrated circuit. 5
Layer stacks claimed or described, ordered top of device to substrate.
dual-gate bilayer graphene field-effect transistor (first transistor)
Materials described outside the worked examples.
bilayer graphene
metal
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 shows an exemplary tunable band gap electronic device 100, such as a FET device, in accordance with an illustrative embodiment of the present invention. …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0–300 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
dual-gate bilayer graphene field-effect transistor (second transistor)
poly-silicon
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
FIG. 1 shows an exemplary tunable band gap electronic device 100, such as a FET device, in accordance with an illustrative embodiment of the present invention. …
FIGS. 2-20 illustrate various fabrication steps that are employed in the present invention in fabricating the electronic device 100. As will be described …
FIG. 9. An ion implantation process is performed to implant electrical dopants into the exposed portions of the bottom gates 196, that is, the 25 portions that …
FIG. 10. The next step is to create an n-type poly in the first transistor 175. In order to create the first transistor 175 with the n-type poly, the device 100 …
FIG. 12. In one embodiment, an n-type material such as phosphorus (P) or arsenic (As) is implanted to the local first bottom gate 115 of the first transistor …
FIG. 20.
| 0.5–30 nm |
| — |
dual-gate bilayer graphene field-effect transistor (second transistor)
poly-silicon
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
FIG. 1 shows an exemplary tunable band gap electronic device 100, such as a FET device, in accordance with an illustrative embodiment of the present invention. …
FIGS. 2-20 illustrate various fabrication steps that are employed in the present invention in fabricating the electronic device 100. As will be described …
FIG. 9. An ion implantation process is performed to implant electrical dopants into the exposed portions of the bottom gates 196, that is, the 25 portions that …
FIG. 10. The next step is to create an n-type poly in the first transistor 175. In order to create the first transistor 175 with the n-type poly, the device 100 …
FIG. 12. In one embodiment, an n-type material such as phosphorus (P) or arsenic (As) is implanted to the local first bottom gate 115 of the first transistor …
FIG. 20.
| 0.5–30 nm |
| — |
dual-gate bilayer graphene field-effect transistor (second transistor)
poly-silicon
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
FIG. 1 shows an exemplary tunable band gap electronic device 100, such as a FET device, in accordance with an illustrative embodiment of the present invention. …
FIGS. 2-20 illustrate various fabrication steps that are employed in the present invention in fabricating the electronic device 100. As will be described …
FIG. 9. An ion implantation process is performed to implant electrical dopants into the exposed portions of the bottom gates 196, that is, the 25 portions that …
FIG. 10. The next step is to create an n-type poly in the first transistor 175. In order to create the first transistor 175 with the n-type poly, the device 100 …
FIG. 12. In one embodiment, an n-type material such as phosphorus (P) or arsenic (As) is implanted to the local first bottom gate 115 of the first transistor …
FIG. 20.
| 0.5–30 nm |
| — |
dual-gate bilayer graphene field-effect transistor (second transistor)
poly-silicon
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
FIG. 1 shows an exemplary tunable band gap electronic device 100, such as a FET device, in accordance with an illustrative embodiment of the present invention. …
FIGS. 2-20 illustrate various fabrication steps that are employed in the present invention in fabricating the electronic device 100. As will be described …
FIG. 9. An ion implantation process is performed to implant electrical dopants into the exposed portions of the bottom gates 196, that is, the 25 portions that …
FIG. 10. The next step is to create an n-type poly in the first transistor 175. In order to create the first transistor 175 with the n-type poly, the device 100 …
FIG. 12. In one embodiment, an n-type material such as phosphorus (P) or arsenic (As) is implanted to the local first bottom gate 115 of the first transistor …
FIG. 20.
| 0.5–30 nm |
| — |