Patent
US 9,306,021GRAPHENE DEVICES AND METHODS OF FABRICATING THE SAME
Hyun-jong CHUNG
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,306,021Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a view illustrating a graphene transistor according to an example embodiment; [0030]
FIGS. 2A and 2B are energy band diagrams for explaining example operation of the graphene transistor illustrated in
FIG. 3 is a view illustrating a graphene transistor according to another example embodiment; [0032]
FIGS. 4A through 4G illustrate a method of fabricating a graphene transistor according to an example embodiment; and [0033]
FIGS. 5A through 5F illustrate a method of fabricating a graphene transistor according to another example embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene device comprising: a semiconductor substrate having a first region and a second region, the first and second regions of the semiconductor substrate being semiconductor regions having semiconductive properties; a graphene layer on the first region, but not on the second region of the semiconductor substrate; a first electrode on a first portion of the graphene layer; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode directly on the semiconductor substrate, and entirely within the second region of the semiconductor substrate; wherein the semiconductor substrate has a tunable Schottky barrier formed by junction of the graphene layer and the semiconductor substrate, the first portion of the graphene layer is on the first region of the semiconductor substrate, and the first and second regions of the semiconductor substrate are semiconductor regions having semiconductive properties.
The graphene device of claim 1, wherein the graphene layer directly contacts the semiconductor substrate.
The graphene device of claim 1, wherein the first electrode directly contacts the graphene layer.
The graphene device of claim 1, wherein a surface of the first region of the semiconductor substrate is flat.
The graphene device of claim 1, wherein the first electrode is a source electrode, the second electrode is a gate electrode, and the third electrode is a drain electrode.
The graphene device of claim 1, wherein the semiconductor substrate has a carrier concentration of between about 1015 and about 10 17 cm- 1, inclusive.
The graphene device of claim 1, further comprising: a high-concentration doped region in the semiconductor substrate, the high- concentration doped region being doped with impurities at a higher carrier concentration than a carrier concentration of the semiconductor substrate.
The graphene device of claim 1, wherein the first electrode includes at least one of gold, nickel, platinum, aluminum, and chromium.
The graphene device of claim 1, wherein the second and third electrodes include metal or polysilicon.
The graphene device of claim 1, wherein the semiconductor substrate is formed of one of silicon, germanium, silicon-germanium, I II -V-group semiconductor, and I I -VI-group semiconductor.
The graphene device of claim 1, wherein the tunable Schottky barrier varies according to a voltage applied to the second electrode.
The graphene device of claim 1, wherein the tunable Schottky barrier decreases in response to a voltage applied to the second electrode.
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A graphene device comprising: a semiconductor substrate; a graphene layer directly on a first region of the semiconductor substrate; a first electrode on a first portion of the graphene layer, a junction between the graphene layer and the semiconductor substrate forming a Schottky barrier of the semiconductor substrate; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on a second region of the semiconductor substrate, wherein an entirety of the third electrode is directly on the semiconductor substrate, and the first and second regions of the semiconductor substrate are semiconductor regions having semiconductive properties, and 5 Atty. Dkt. No. 2557 SI -002041-US U.S. Application No. 14/244,223 the first portion of the graphene layer is on the first region of the semiconductor substrate.
The graphene device of claim 24, wherein the first electrode directly contacts the graphene layer.
The graphene device of claim 24, wherein a surface of the first region of the semiconductor substrate is flat.
The graphene device of claim 24, wherein the Schottky barrier is a tunable Schottky barrier.
The graphene device of claim 24, wherein the Schottky barrier varies according to a voltage applied to the second electrode.
The graphene device of claim 24, further comprising: a high-concentration doped region in the semiconductor substrate, the high- concentration doped region being doped with impurities at a higher carrier concentration than a carrier concentration of the semiconductor substrate.
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A graphene device comprising: a semiconductor substrate; 6 Atty. Dkt. No. 2557 SI -002041-US U.S. Application No. 14/244,223 a graphene layer on a flat surface of a first region of the semiconductor substrate; a first electrode on a first portion of the graphene layer, a junction between the graphene layer and the semiconductor substrate forming a Schottky barrier of the semiconductor substrate; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on a second region of the semiconductor substrate, wherein an entirety of the third electrode is on the semiconductor substrate without an intervening layer, and the first and second regions of the semiconductor substrate are semiconductor regions having semiconductive properties, and the first portion of the graphene layer is on the first region of the semiconductor substrate.
The graphene device of claim 31, the Schottky barrier varies according to a voltage applied to the second electrode.
The graphene device of claim 31, wherein the Schottky barrier is a tunable Schottky barrier.
The graphene device of claim 31, further comprising: 7 Atty. Dkt. No. 2557S I -002041-US U.S. Application No. 14/244,223 a high-concentration doped region in the semiconductor substrate, the high- concentration doped region being doped with impurities at a higher carrier concentration than a carrier concentration of the semiconductor substrate. 8
. canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene Schottky barrier transistor (claim 1)
graphene Schottky barrier transistor (claim 24)
Materials described outside the worked examples.
graphene
semiconductor substrate
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a view illustrating a graphene transistor according to an example embodiment; [0030]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1015–1017 cm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,306,021Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a view illustrating a graphene transistor according to an example embodiment; [0030]
FIGS. 2A and 2B are energy band diagrams for explaining example operation of the graphene transistor illustrated in
FIG. 3 is a view illustrating a graphene transistor according to another example embodiment; [0032]
FIGS. 4A through 4G illustrate a method of fabricating a graphene transistor according to an example embodiment; and [0033]
FIGS. 5A through 5F illustrate a method of fabricating a graphene transistor according to another example embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene device comprising: a semiconductor substrate having a first region and a second region, the first and second regions of the semiconductor substrate being semiconductor regions having semiconductive properties; a graphene layer on the first region, but not on the second region of the semiconductor substrate; a first electrode on a first portion of the graphene layer; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode directly on the semiconductor substrate, and entirely within the second region of the semiconductor substrate; wherein the semiconductor substrate has a tunable Schottky barrier formed by junction of the graphene layer and the semiconductor substrate, the first portion of the graphene layer is on the first region of the semiconductor substrate, and the first and second regions of the semiconductor substrate are semiconductor regions having semiconductive properties.
The graphene device of claim 1, wherein the graphene layer directly contacts the semiconductor substrate.
The graphene device of claim 1, wherein the first electrode directly contacts the graphene layer.
The graphene device of claim 1, wherein a surface of the first region of the semiconductor substrate is flat.
The graphene device of claim 1, wherein the first electrode is a source electrode, the second electrode is a gate electrode, and the third electrode is a drain electrode.
The graphene device of claim 1, wherein the semiconductor substrate has a carrier concentration of between about 1015 and about 10 17 cm- 1, inclusive.
The graphene device of claim 1, further comprising: a high-concentration doped region in the semiconductor substrate, the high- concentration doped region being doped with impurities at a higher carrier concentration than a carrier concentration of the semiconductor substrate.
The graphene device of claim 1, wherein the first electrode includes at least one of gold, nickel, platinum, aluminum, and chromium.
The graphene device of claim 1, wherein the second and third electrodes include metal or polysilicon.
The graphene device of claim 1, wherein the semiconductor substrate is formed of one of silicon, germanium, silicon-germanium, I II -V-group semiconductor, and I I -VI-group semiconductor.
The graphene device of claim 1, wherein the tunable Schottky barrier varies according to a voltage applied to the second electrode.
The graphene device of claim 1, wherein the tunable Schottky barrier decreases in response to a voltage applied to the second electrode.
18-23. canceled
canceled
canceled
canceled
canceled
canceled
A graphene device comprising: a semiconductor substrate; a graphene layer directly on a first region of the semiconductor substrate; a first electrode on a first portion of the graphene layer, a junction between the graphene layer and the semiconductor substrate forming a Schottky barrier of the semiconductor substrate; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on a second region of the semiconductor substrate, wherein an entirety of the third electrode is directly on the semiconductor substrate, and the first and second regions of the semiconductor substrate are semiconductor regions having semiconductive properties, and 5 Atty. Dkt. No. 2557 SI -002041-US U.S. Application No. 14/244,223 the first portion of the graphene layer is on the first region of the semiconductor substrate.
The graphene device of claim 24, wherein the first electrode directly contacts the graphene layer.
The graphene device of claim 24, wherein a surface of the first region of the semiconductor substrate is flat.
The graphene device of claim 24, wherein the Schottky barrier is a tunable Schottky barrier.
The graphene device of claim 24, wherein the Schottky barrier varies according to a voltage applied to the second electrode.
The graphene device of claim 24, further comprising: a high-concentration doped region in the semiconductor substrate, the high- concentration doped region being doped with impurities at a higher carrier concentration than a carrier concentration of the semiconductor substrate.
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A graphene device comprising: a semiconductor substrate; 6 Atty. Dkt. No. 2557 SI -002041-US U.S. Application No. 14/244,223 a graphene layer on a flat surface of a first region of the semiconductor substrate; a first electrode on a first portion of the graphene layer, a junction between the graphene layer and the semiconductor substrate forming a Schottky barrier of the semiconductor substrate; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on a second region of the semiconductor substrate, wherein an entirety of the third electrode is on the semiconductor substrate without an intervening layer, and the first and second regions of the semiconductor substrate are semiconductor regions having semiconductive properties, and the first portion of the graphene layer is on the first region of the semiconductor substrate.
The graphene device of claim 31, the Schottky barrier varies according to a voltage applied to the second electrode.
The graphene device of claim 31, wherein the Schottky barrier is a tunable Schottky barrier.
The graphene device of claim 31, further comprising: 7 Atty. Dkt. No. 2557S I -002041-US U.S. Application No. 14/244,223 a high-concentration doped region in the semiconductor substrate, the high- concentration doped region being doped with impurities at a higher carrier concentration than a carrier concentration of the semiconductor substrate. 8
. canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene Schottky barrier transistor (claim 1)
graphene Schottky barrier transistor (claim 24)
Materials described outside the worked examples.
graphene
semiconductor substrate
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a view illustrating a graphene transistor according to an example embodiment; [0030]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1015–1017 cm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,306,021Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a view illustrating a graphene transistor according to an example embodiment; [0030]
FIGS. 2A and 2B are energy band diagrams for explaining example operation of the graphene transistor illustrated in
FIG. 3 is a view illustrating a graphene transistor according to another example embodiment; [0032]
FIGS. 4A through 4G illustrate a method of fabricating a graphene transistor according to an example embodiment; and [0033]
FIGS. 5A through 5F illustrate a method of fabricating a graphene transistor according to another example embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene device comprising: a semiconductor substrate having a first region and a second region, the first and second regions of the semiconductor substrate being semiconductor regions having semiconductive properties; a graphene layer on the first region, but not on the second region of the semiconductor substrate; a first electrode on a first portion of the graphene layer; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode directly on the semiconductor substrate, and entirely within the second region of the semiconductor substrate; wherein the semiconductor substrate has a tunable Schottky barrier formed by junction of the graphene layer and the semiconductor substrate, the first portion of the graphene layer is on the first region of the semiconductor substrate, and the first and second regions of the semiconductor substrate are semiconductor regions having semiconductive properties.
The graphene device of claim 1, wherein the graphene layer directly contacts the semiconductor substrate.
The graphene device of claim 1, wherein the first electrode directly contacts the graphene layer.
The graphene device of claim 1, wherein a surface of the first region of the semiconductor substrate is flat.
The graphene device of claim 1, wherein the first electrode is a source electrode, the second electrode is a gate electrode, and the third electrode is a drain electrode.
The graphene device of claim 1, wherein the semiconductor substrate has a carrier concentration of between about 1015 and about 10 17 cm- 1, inclusive.
The graphene device of claim 1, further comprising: a high-concentration doped region in the semiconductor substrate, the high- concentration doped region being doped with impurities at a higher carrier concentration than a carrier concentration of the semiconductor substrate.
The graphene device of claim 1, wherein the first electrode includes at least one of gold, nickel, platinum, aluminum, and chromium.
The graphene device of claim 1, wherein the second and third electrodes include metal or polysilicon.
The graphene device of claim 1, wherein the semiconductor substrate is formed of one of silicon, germanium, silicon-germanium, I II -V-group semiconductor, and I I -VI-group semiconductor.
The graphene device of claim 1, wherein the tunable Schottky barrier varies according to a voltage applied to the second electrode.
The graphene device of claim 1, wherein the tunable Schottky barrier decreases in response to a voltage applied to the second electrode.
18-23. canceled
canceled
canceled
canceled
canceled
canceled
A graphene device comprising: a semiconductor substrate; a graphene layer directly on a first region of the semiconductor substrate; a first electrode on a first portion of the graphene layer, a junction between the graphene layer and the semiconductor substrate forming a Schottky barrier of the semiconductor substrate; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on a second region of the semiconductor substrate, wherein an entirety of the third electrode is directly on the semiconductor substrate, and the first and second regions of the semiconductor substrate are semiconductor regions having semiconductive properties, and 5 Atty. Dkt. No. 2557 SI -002041-US U.S. Application No. 14/244,223 the first portion of the graphene layer is on the first region of the semiconductor substrate.
The graphene device of claim 24, wherein the first electrode directly contacts the graphene layer.
The graphene device of claim 24, wherein a surface of the first region of the semiconductor substrate is flat.
The graphene device of claim 24, wherein the Schottky barrier is a tunable Schottky barrier.
The graphene device of claim 24, wherein the Schottky barrier varies according to a voltage applied to the second electrode.
The graphene device of claim 24, further comprising: a high-concentration doped region in the semiconductor substrate, the high- concentration doped region being doped with impurities at a higher carrier concentration than a carrier concentration of the semiconductor substrate.
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A graphene device comprising: a semiconductor substrate; 6 Atty. Dkt. No. 2557 SI -002041-US U.S. Application No. 14/244,223 a graphene layer on a flat surface of a first region of the semiconductor substrate; a first electrode on a first portion of the graphene layer, a junction between the graphene layer and the semiconductor substrate forming a Schottky barrier of the semiconductor substrate; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on a second region of the semiconductor substrate, wherein an entirety of the third electrode is on the semiconductor substrate without an intervening layer, and the first and second regions of the semiconductor substrate are semiconductor regions having semiconductive properties, and the first portion of the graphene layer is on the first region of the semiconductor substrate.
The graphene device of claim 31, the Schottky barrier varies according to a voltage applied to the second electrode.
The graphene device of claim 31, wherein the Schottky barrier is a tunable Schottky barrier.
The graphene device of claim 31, further comprising: 7 Atty. Dkt. No. 2557S I -002041-US U.S. Application No. 14/244,223 a high-concentration doped region in the semiconductor substrate, the high- concentration doped region being doped with impurities at a higher carrier concentration than a carrier concentration of the semiconductor substrate. 8
. canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene Schottky barrier transistor (claim 1)
graphene Schottky barrier transistor (claim 24)
Materials described outside the worked examples.
graphene
semiconductor substrate
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a view illustrating a graphene transistor according to an example embodiment; [0030]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1015–1017 cm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,306,021Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a view illustrating a graphene transistor according to an example embodiment; [0030]
FIGS. 2A and 2B are energy band diagrams for explaining example operation of the graphene transistor illustrated in
FIG. 3 is a view illustrating a graphene transistor according to another example embodiment; [0032]
FIGS. 4A through 4G illustrate a method of fabricating a graphene transistor according to an example embodiment; and [0033]
FIGS. 5A through 5F illustrate a method of fabricating a graphene transistor according to another example embodiment.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene device comprising: a semiconductor substrate having a first region and a second region, the first and second regions of the semiconductor substrate being semiconductor regions having semiconductive properties; a graphene layer on the first region, but not on the second region of the semiconductor substrate; a first electrode on a first portion of the graphene layer; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode directly on the semiconductor substrate, and entirely within the second region of the semiconductor substrate; wherein the semiconductor substrate has a tunable Schottky barrier formed by junction of the graphene layer and the semiconductor substrate, the first portion of the graphene layer is on the first region of the semiconductor substrate, and the first and second regions of the semiconductor substrate are semiconductor regions having semiconductive properties.
The graphene device of claim 1, wherein the graphene layer directly contacts the semiconductor substrate.
The graphene device of claim 1, wherein the first electrode directly contacts the graphene layer.
The graphene device of claim 1, wherein a surface of the first region of the semiconductor substrate is flat.
The graphene device of claim 1, wherein the first electrode is a source electrode, the second electrode is a gate electrode, and the third electrode is a drain electrode.
The graphene device of claim 1, wherein the semiconductor substrate has a carrier concentration of between about 1015 and about 10 17 cm- 1, inclusive.
The graphene device of claim 1, further comprising: a high-concentration doped region in the semiconductor substrate, the high- concentration doped region being doped with impurities at a higher carrier concentration than a carrier concentration of the semiconductor substrate.
The graphene device of claim 1, wherein the first electrode includes at least one of gold, nickel, platinum, aluminum, and chromium.
The graphene device of claim 1, wherein the second and third electrodes include metal or polysilicon.
The graphene device of claim 1, wherein the semiconductor substrate is formed of one of silicon, germanium, silicon-germanium, I II -V-group semiconductor, and I I -VI-group semiconductor.
The graphene device of claim 1, wherein the tunable Schottky barrier varies according to a voltage applied to the second electrode.
The graphene device of claim 1, wherein the tunable Schottky barrier decreases in response to a voltage applied to the second electrode.
18-23. canceled
canceled
canceled
canceled
canceled
canceled
A graphene device comprising: a semiconductor substrate; a graphene layer directly on a first region of the semiconductor substrate; a first electrode on a first portion of the graphene layer, a junction between the graphene layer and the semiconductor substrate forming a Schottky barrier of the semiconductor substrate; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on a second region of the semiconductor substrate, wherein an entirety of the third electrode is directly on the semiconductor substrate, and the first and second regions of the semiconductor substrate are semiconductor regions having semiconductive properties, and 5 Atty. Dkt. No. 2557 SI -002041-US U.S. Application No. 14/244,223 the first portion of the graphene layer is on the first region of the semiconductor substrate.
The graphene device of claim 24, wherein the first electrode directly contacts the graphene layer.
The graphene device of claim 24, wherein a surface of the first region of the semiconductor substrate is flat.
The graphene device of claim 24, wherein the Schottky barrier is a tunable Schottky barrier.
The graphene device of claim 24, wherein the Schottky barrier varies according to a voltage applied to the second electrode.
The graphene device of claim 24, further comprising: a high-concentration doped region in the semiconductor substrate, the high- concentration doped region being doped with impurities at a higher carrier concentration than a carrier concentration of the semiconductor substrate.
. canceled
A graphene device comprising: a semiconductor substrate; 6 Atty. Dkt. No. 2557 SI -002041-US U.S. Application No. 14/244,223 a graphene layer on a flat surface of a first region of the semiconductor substrate; a first electrode on a first portion of the graphene layer, a junction between the graphene layer and the semiconductor substrate forming a Schottky barrier of the semiconductor substrate; a second electrode on a second portion of the graphene layer; an insulating layer between the graphene layer and the second electrode; and a third electrode on a second region of the semiconductor substrate, wherein an entirety of the third electrode is on the semiconductor substrate without an intervening layer, and the first and second regions of the semiconductor substrate are semiconductor regions having semiconductive properties, and the first portion of the graphene layer is on the first region of the semiconductor substrate.
The graphene device of claim 31, the Schottky barrier varies according to a voltage applied to the second electrode.
The graphene device of claim 31, wherein the Schottky barrier is a tunable Schottky barrier.
The graphene device of claim 31, further comprising: 7 Atty. Dkt. No. 2557S I -002041-US U.S. Application No. 14/244,223 a high-concentration doped region in the semiconductor substrate, the high- concentration doped region being doped with impurities at a higher carrier concentration than a carrier concentration of the semiconductor substrate. 8
. canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene Schottky barrier transistor (claim 1)
graphene Schottky barrier transistor (claim 24)
Materials described outside the worked examples.
graphene
semiconductor substrate
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a view illustrating a graphene transistor according to an example embodiment; [0030]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 1015–1017 cm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
graphene Schottky barrier transistor (claim 31)
first electrode metal
high-concentration doped region
insulating layer (gate dielectric)
FIGS. 2A and 2B are energy band diagrams for explaining example operation of the graphene transistor illustrated in
FIG. 3 is a view illustrating a graphene transistor according to another example embodiment; [0032]
FIGS. 4A through 4G illustrate a method of fabricating a graphene transistor according to an example embodiment; and [0033]
FIGS. 5A through 5F illustrate a method of fabricating a graphene transistor according to another example embodiment.
| — |
graphene Schottky barrier transistor (claim 31)
first electrode metal
high-concentration doped region
insulating layer (gate dielectric)
FIGS. 2A and 2B are energy band diagrams for explaining example operation of the graphene transistor illustrated in
FIG. 3 is a view illustrating a graphene transistor according to another example embodiment; [0032]
FIGS. 4A through 4G illustrate a method of fabricating a graphene transistor according to an example embodiment; and [0033]
FIGS. 5A through 5F illustrate a method of fabricating a graphene transistor according to another example embodiment.
| — |
graphene Schottky barrier transistor (claim 31)
first electrode metal
high-concentration doped region
insulating layer (gate dielectric)
FIGS. 2A and 2B are energy band diagrams for explaining example operation of the graphene transistor illustrated in
FIG. 3 is a view illustrating a graphene transistor according to another example embodiment; [0032]
FIGS. 4A through 4G illustrate a method of fabricating a graphene transistor according to an example embodiment; and [0033]
FIGS. 5A through 5F illustrate a method of fabricating a graphene transistor according to another example embodiment.
| — |
graphene Schottky barrier transistor (claim 31)
first electrode metal
high-concentration doped region
insulating layer (gate dielectric)
FIGS. 2A and 2B are energy band diagrams for explaining example operation of the graphene transistor illustrated in
FIG. 3 is a view illustrating a graphene transistor according to another example embodiment; [0032]
FIGS. 4A through 4G illustrate a method of fabricating a graphene transistor according to an example embodiment; and [0033]
FIGS. 5A through 5F illustrate a method of fabricating a graphene transistor according to another example embodiment.
| — |