Patent
US 9,306,005ELECTRONIC DEVICE INCLUDING GRAPHENE
Kyung-eun BYUN
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
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US 9,306,005Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG 1 is a band diagram illustrating an energy bar ri er between a metal and a semiconductor,
FIGS 2 and 3 are cross-sectional views of an electronic device according to example embodiments,
FIG 4 is a band diagram illustrating an energy bar ri er of metal-graphene- semiconductor,
FIG 5 is a cross-sectional view of a field effect transistor (FET) according to example embodiments,
FIG 6 is a cross-sectional view of a j unctionless device used in a simulation,
FIG 7 is a cross-sectional view of a general metal oxide silicon field effect transistor (MOSFET) used in the simulation,
FIG 8 is a graph showing a change in a drain current along a change in a gate voltage in each of the j unctionless device and the general MOSFET, which is obtained by the simulation,
FIG 9 is a band diagram illustrating an energy bar ri er between a metal and a semiconductor, 5 Atty Dkt No 2557 S₁ -002057/US
FIG 10 is a band diagram illustrating an energy bar ri er of metal-graphene- semiconductor,
FIGS 11 A and 11 B are cross-sectional views of field effect transistors (FETs) according to example embodiments,
FIG 12 is a cross-sectional view of a field effect transistor (FET) according to example embodiments, and
FIGS 13A and 13B are cross-sectional views of inverters according to example embodiments
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device comprising: a semiconductor layer including an area, wherein the area includes a depletion width of less than or equal to 3 nm; a graphene directly contacting the area of the semiconductor layer; and a metal layer on the graphene.
The electronic d evice of claim 1, wherein the semiconductor layer includes a constant doping density in overall; or the area includes a doping density that is less than or equal to 10 19 cm⁻³.
The electronic device of claim 1, wherein the semiconductor layer is a semiconductor substrate. Application No.: 14/103,079 Attorney Docket No.: 2557S I -002057-US Page 3 of 8
The electronic device of claim 1, wherein the semiconductor layer includes at least one of silicon, ger m anium, si li con-germanium, a II-VI group semiconductor, and a III -V group semiconductor.
The electronic device of claim 1, wherein a width of the graphene is less than a width of the semiconductor layer.
. canceled
A field effect transistor (FET) comprising: the electronic device of claim 16; first and second graphenes separated from each other; source and drain electrodes; and a gate electrode, wherein the semiconductor layer of the electronic device includes a channel area, a source area, and a drain area, the area of the semiconductor layer is one of the source area and the drain area, the source and drain areas are separated from each other, the first and second graphenes directly contact the source and drain areas of the semiconductor layer, respectively, the source and drain electrodes are on the first and second graphenes, respectively, and the gate electrode faces the channel area.
The FET of claim 7, wherein a doping density in the source and drain areas that- is one of: Application No.: 14/103,079 Attorney Docket No.: 2557S I -002057-US Page 4 of 8 equal to the doping density in the channel area, and less than or equal to 1019 c m-3.
The FET of claim 7, further comprising: a gate insulation layer between the channel area and the gate electrode.
The FET of claim 7, wherein the semiconductor layer is a semiconductor substrate.
The FET of claim 7, wherein the depletion width of the source area and the drain area in the semiconductor layer is less than or equal to 3 nm.
The FET of claim 7, wherein the semiconductor layer is a semiconductor substrate, and at least one part of the semiconductor substrate below the first and second graphenes includes a depletion width that is less than or equal to 3 n m. Application No.: 14/103,079 Attorney Docket No.: 2557S I- 002057-US Page 5 of 8
. canceled
canceled
An electronic device, comprising: a semiconductor layer including an area, the area of the semiconductor layer including one of a depletion width of less than or equal to 3 nm and a constant doping density in overall; a metal layer connected to the area of the semiconductor layer; and a graphene between the metal layer and the area of the semiconductor layer, the graphene directly contacting the area of the semiconductor layer, the graphene is configured to reduce an energy barrier between the metal layer and the area of the semiconductor layer.
The electronic device of claim 16, wherein the graphene is one of a single layer and two layers.
The electronic device of claim 16, wherein the graphene does not have a bandgap so a Fe rm i level between the metal layer and the graphene does not vary, and the depletion width between the area of the semiconductor layer and the graphene is less than or equal to 3 nm.
The electronic device of claim 16, wherein the semiconductor layer is a substrate, and the substrate includes at least one of silicon, germanium, silicon-ger m anium, a II-VI group semiconductor, and a III -V group semiconductor. Application No.: 14/103,079 Attorney Docket No.: 2557S I -002057-US Page 6 of 8
(Previously Presented) The electronic device of claim 16, further comprising: a gate insulating layer connected to a portion of the semiconductor layer that is adjacent to the area of the semiconductor layer; and a gate electrode connected to the gate insulating layer, wherein the gate insulating layer is between the gate electrode and the portion of the semiconductor layer.
The electronic device of claim 16, wherein the area of the semiconductor layer is a first area of the semiconductor layer; the semiconductor layer includes a second area spaced apart from the first area; the electronic device further includes: a second metal layer connected to the second area, and a second graphene between the second metal layer and the second area; and the second graphene is configured to reduce an energy barrier between the second metal layer and the second area of the semiconductor layer.
The electronic device of claim 16, wherein a width of the graphene is less than a width of the
. canceled
Layer stacks claimed or described, ordered top of device to substrate.
electronic device (graphene-semiconductor-metal contact)
field effect transistor (FET) with graphene source/drain contacts
Materials described outside the worked examples.
semiconductor layer
graphene
Measurements and analyses referenced in the patent, with their drawing references.
FIG 5 is a cross-sectional view of a field effect transistor (FET) according to example embodiments,
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 2–3 V | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,306,005Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG 1 is a band diagram illustrating an energy bar ri er between a metal and a semiconductor,
FIGS 2 and 3 are cross-sectional views of an electronic device according to example embodiments,
FIG 4 is a band diagram illustrating an energy bar ri er of metal-graphene- semiconductor,
FIG 5 is a cross-sectional view of a field effect transistor (FET) according to example embodiments,
FIG 6 is a cross-sectional view of a j unctionless device used in a simulation,
FIG 7 is a cross-sectional view of a general metal oxide silicon field effect transistor (MOSFET) used in the simulation,
FIG 8 is a graph showing a change in a drain current along a change in a gate voltage in each of the j unctionless device and the general MOSFET, which is obtained by the simulation,
FIG 9 is a band diagram illustrating an energy bar ri er between a metal and a semiconductor, 5 Atty Dkt No 2557 S₁ -002057/US
FIG 10 is a band diagram illustrating an energy bar ri er of metal-graphene- semiconductor,
FIGS 11 A and 11 B are cross-sectional views of field effect transistors (FETs) according to example embodiments,
FIG 12 is a cross-sectional view of a field effect transistor (FET) according to example embodiments, and
FIGS 13A and 13B are cross-sectional views of inverters according to example embodiments
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device comprising: a semiconductor layer including an area, wherein the area includes a depletion width of less than or equal to 3 nm; a graphene directly contacting the area of the semiconductor layer; and a metal layer on the graphene.
The electronic d evice of claim 1, wherein the semiconductor layer includes a constant doping density in overall; or the area includes a doping density that is less than or equal to 10 19 cm⁻³.
The electronic device of claim 1, wherein the semiconductor layer is a semiconductor substrate. Application No.: 14/103,079 Attorney Docket No.: 2557S I -002057-US Page 3 of 8
The electronic device of claim 1, wherein the semiconductor layer includes at least one of silicon, ger m anium, si li con-germanium, a II-VI group semiconductor, and a III -V group semiconductor.
The electronic device of claim 1, wherein a width of the graphene is less than a width of the semiconductor layer.
. canceled
A field effect transistor (FET) comprising: the electronic device of claim 16; first and second graphenes separated from each other; source and drain electrodes; and a gate electrode, wherein the semiconductor layer of the electronic device includes a channel area, a source area, and a drain area, the area of the semiconductor layer is one of the source area and the drain area, the source and drain areas are separated from each other, the first and second graphenes directly contact the source and drain areas of the semiconductor layer, respectively, the source and drain electrodes are on the first and second graphenes, respectively, and the gate electrode faces the channel area.
The FET of claim 7, wherein a doping density in the source and drain areas that- is one of: Application No.: 14/103,079 Attorney Docket No.: 2557S I -002057-US Page 4 of 8 equal to the doping density in the channel area, and less than or equal to 1019 c m-3.
The FET of claim 7, further comprising: a gate insulation layer between the channel area and the gate electrode.
The FET of claim 7, wherein the semiconductor layer is a semiconductor substrate.
The FET of claim 7, wherein the depletion width of the source area and the drain area in the semiconductor layer is less than or equal to 3 nm.
The FET of claim 7, wherein the semiconductor layer is a semiconductor substrate, and at least one part of the semiconductor substrate below the first and second graphenes includes a depletion width that is less than or equal to 3 n m. Application No.: 14/103,079 Attorney Docket No.: 2557S I- 002057-US Page 5 of 8
. canceled
canceled
An electronic device, comprising: a semiconductor layer including an area, the area of the semiconductor layer including one of a depletion width of less than or equal to 3 nm and a constant doping density in overall; a metal layer connected to the area of the semiconductor layer; and a graphene between the metal layer and the area of the semiconductor layer, the graphene directly contacting the area of the semiconductor layer, the graphene is configured to reduce an energy barrier between the metal layer and the area of the semiconductor layer.
The electronic device of claim 16, wherein the graphene is one of a single layer and two layers.
The electronic device of claim 16, wherein the graphene does not have a bandgap so a Fe rm i level between the metal layer and the graphene does not vary, and the depletion width between the area of the semiconductor layer and the graphene is less than or equal to 3 nm.
The electronic device of claim 16, wherein the semiconductor layer is a substrate, and the substrate includes at least one of silicon, germanium, silicon-ger m anium, a II-VI group semiconductor, and a III -V group semiconductor. Application No.: 14/103,079 Attorney Docket No.: 2557S I -002057-US Page 6 of 8
(Previously Presented) The electronic device of claim 16, further comprising: a gate insulating layer connected to a portion of the semiconductor layer that is adjacent to the area of the semiconductor layer; and a gate electrode connected to the gate insulating layer, wherein the gate insulating layer is between the gate electrode and the portion of the semiconductor layer.
The electronic device of claim 16, wherein the area of the semiconductor layer is a first area of the semiconductor layer; the semiconductor layer includes a second area spaced apart from the first area; the electronic device further includes: a second metal layer connected to the second area, and a second graphene between the second metal layer and the second area; and the second graphene is configured to reduce an energy barrier between the second metal layer and the second area of the semiconductor layer.
The electronic device of claim 16, wherein a width of the graphene is less than a width of the
. canceled
Layer stacks claimed or described, ordered top of device to substrate.
electronic device (graphene-semiconductor-metal contact)
field effect transistor (FET) with graphene source/drain contacts
Materials described outside the worked examples.
semiconductor layer
graphene
Measurements and analyses referenced in the patent, with their drawing references.
FIG 5 is a cross-sectional view of a field effect transistor (FET) according to example embodiments,
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 2–3 V | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,306,005Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG 1 is a band diagram illustrating an energy bar ri er between a metal and a semiconductor,
FIGS 2 and 3 are cross-sectional views of an electronic device according to example embodiments,
FIG 4 is a band diagram illustrating an energy bar ri er of metal-graphene- semiconductor,
FIG 5 is a cross-sectional view of a field effect transistor (FET) according to example embodiments,
FIG 6 is a cross-sectional view of a j unctionless device used in a simulation,
FIG 7 is a cross-sectional view of a general metal oxide silicon field effect transistor (MOSFET) used in the simulation,
FIG 8 is a graph showing a change in a drain current along a change in a gate voltage in each of the j unctionless device and the general MOSFET, which is obtained by the simulation,
FIG 9 is a band diagram illustrating an energy bar ri er between a metal and a semiconductor, 5 Atty Dkt No 2557 S₁ -002057/US
FIG 10 is a band diagram illustrating an energy bar ri er of metal-graphene- semiconductor,
FIGS 11 A and 11 B are cross-sectional views of field effect transistors (FETs) according to example embodiments,
FIG 12 is a cross-sectional view of a field effect transistor (FET) according to example embodiments, and
FIGS 13A and 13B are cross-sectional views of inverters according to example embodiments
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device comprising: a semiconductor layer including an area, wherein the area includes a depletion width of less than or equal to 3 nm; a graphene directly contacting the area of the semiconductor layer; and a metal layer on the graphene.
The electronic d evice of claim 1, wherein the semiconductor layer includes a constant doping density in overall; or the area includes a doping density that is less than or equal to 10 19 cm⁻³.
The electronic device of claim 1, wherein the semiconductor layer is a semiconductor substrate. Application No.: 14/103,079 Attorney Docket No.: 2557S I -002057-US Page 3 of 8
The electronic device of claim 1, wherein the semiconductor layer includes at least one of silicon, ger m anium, si li con-germanium, a II-VI group semiconductor, and a III -V group semiconductor.
The electronic device of claim 1, wherein a width of the graphene is less than a width of the semiconductor layer.
. canceled
A field effect transistor (FET) comprising: the electronic device of claim 16; first and second graphenes separated from each other; source and drain electrodes; and a gate electrode, wherein the semiconductor layer of the electronic device includes a channel area, a source area, and a drain area, the area of the semiconductor layer is one of the source area and the drain area, the source and drain areas are separated from each other, the first and second graphenes directly contact the source and drain areas of the semiconductor layer, respectively, the source and drain electrodes are on the first and second graphenes, respectively, and the gate electrode faces the channel area.
The FET of claim 7, wherein a doping density in the source and drain areas that- is one of: Application No.: 14/103,079 Attorney Docket No.: 2557S I -002057-US Page 4 of 8 equal to the doping density in the channel area, and less than or equal to 1019 c m-3.
The FET of claim 7, further comprising: a gate insulation layer between the channel area and the gate electrode.
The FET of claim 7, wherein the semiconductor layer is a semiconductor substrate.
The FET of claim 7, wherein the depletion width of the source area and the drain area in the semiconductor layer is less than or equal to 3 nm.
The FET of claim 7, wherein the semiconductor layer is a semiconductor substrate, and at least one part of the semiconductor substrate below the first and second graphenes includes a depletion width that is less than or equal to 3 n m. Application No.: 14/103,079 Attorney Docket No.: 2557S I- 002057-US Page 5 of 8
. canceled
canceled
An electronic device, comprising: a semiconductor layer including an area, the area of the semiconductor layer including one of a depletion width of less than or equal to 3 nm and a constant doping density in overall; a metal layer connected to the area of the semiconductor layer; and a graphene between the metal layer and the area of the semiconductor layer, the graphene directly contacting the area of the semiconductor layer, the graphene is configured to reduce an energy barrier between the metal layer and the area of the semiconductor layer.
The electronic device of claim 16, wherein the graphene is one of a single layer and two layers.
The electronic device of claim 16, wherein the graphene does not have a bandgap so a Fe rm i level between the metal layer and the graphene does not vary, and the depletion width between the area of the semiconductor layer and the graphene is less than or equal to 3 nm.
The electronic device of claim 16, wherein the semiconductor layer is a substrate, and the substrate includes at least one of silicon, germanium, silicon-ger m anium, a II-VI group semiconductor, and a III -V group semiconductor. Application No.: 14/103,079 Attorney Docket No.: 2557S I -002057-US Page 6 of 8
(Previously Presented) The electronic device of claim 16, further comprising: a gate insulating layer connected to a portion of the semiconductor layer that is adjacent to the area of the semiconductor layer; and a gate electrode connected to the gate insulating layer, wherein the gate insulating layer is between the gate electrode and the portion of the semiconductor layer.
The electronic device of claim 16, wherein the area of the semiconductor layer is a first area of the semiconductor layer; the semiconductor layer includes a second area spaced apart from the first area; the electronic device further includes: a second metal layer connected to the second area, and a second graphene between the second metal layer and the second area; and the second graphene is configured to reduce an energy barrier between the second metal layer and the second area of the semiconductor layer.
The electronic device of claim 16, wherein a width of the graphene is less than a width of the
. canceled
Layer stacks claimed or described, ordered top of device to substrate.
electronic device (graphene-semiconductor-metal contact)
field effect transistor (FET) with graphene source/drain contacts
Materials described outside the worked examples.
semiconductor layer
graphene
Measurements and analyses referenced in the patent, with their drawing references.
FIG 5 is a cross-sectional view of a field effect transistor (FET) according to example embodiments,
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 2–3 V | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,306,005Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG 1 is a band diagram illustrating an energy bar ri er between a metal and a semiconductor,
FIGS 2 and 3 are cross-sectional views of an electronic device according to example embodiments,
FIG 4 is a band diagram illustrating an energy bar ri er of metal-graphene- semiconductor,
FIG 5 is a cross-sectional view of a field effect transistor (FET) according to example embodiments,
FIG 6 is a cross-sectional view of a j unctionless device used in a simulation,
FIG 7 is a cross-sectional view of a general metal oxide silicon field effect transistor (MOSFET) used in the simulation,
FIG 8 is a graph showing a change in a drain current along a change in a gate voltage in each of the j unctionless device and the general MOSFET, which is obtained by the simulation,
FIG 9 is a band diagram illustrating an energy bar ri er between a metal and a semiconductor, 5 Atty Dkt No 2557 S₁ -002057/US
FIG 10 is a band diagram illustrating an energy bar ri er of metal-graphene- semiconductor,
FIGS 11 A and 11 B are cross-sectional views of field effect transistors (FETs) according to example embodiments,
FIG 12 is a cross-sectional view of a field effect transistor (FET) according to example embodiments, and
FIGS 13A and 13B are cross-sectional views of inverters according to example embodiments
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic device comprising: a semiconductor layer including an area, wherein the area includes a depletion width of less than or equal to 3 nm; a graphene directly contacting the area of the semiconductor layer; and a metal layer on the graphene.
The electronic d evice of claim 1, wherein the semiconductor layer includes a constant doping density in overall; or the area includes a doping density that is less than or equal to 10 19 cm⁻³.
The electronic device of claim 1, wherein the semiconductor layer is a semiconductor substrate. Application No.: 14/103,079 Attorney Docket No.: 2557S I -002057-US Page 3 of 8
The electronic device of claim 1, wherein the semiconductor layer includes at least one of silicon, ger m anium, si li con-germanium, a II-VI group semiconductor, and a III -V group semiconductor.
The electronic device of claim 1, wherein a width of the graphene is less than a width of the semiconductor layer.
. canceled
A field effect transistor (FET) comprising: the electronic device of claim 16; first and second graphenes separated from each other; source and drain electrodes; and a gate electrode, wherein the semiconductor layer of the electronic device includes a channel area, a source area, and a drain area, the area of the semiconductor layer is one of the source area and the drain area, the source and drain areas are separated from each other, the first and second graphenes directly contact the source and drain areas of the semiconductor layer, respectively, the source and drain electrodes are on the first and second graphenes, respectively, and the gate electrode faces the channel area.
The FET of claim 7, wherein a doping density in the source and drain areas that- is one of: Application No.: 14/103,079 Attorney Docket No.: 2557S I -002057-US Page 4 of 8 equal to the doping density in the channel area, and less than or equal to 1019 c m-3.
The FET of claim 7, further comprising: a gate insulation layer between the channel area and the gate electrode.
The FET of claim 7, wherein the semiconductor layer is a semiconductor substrate.
The FET of claim 7, wherein the depletion width of the source area and the drain area in the semiconductor layer is less than or equal to 3 nm.
The FET of claim 7, wherein the semiconductor layer is a semiconductor substrate, and at least one part of the semiconductor substrate below the first and second graphenes includes a depletion width that is less than or equal to 3 n m. Application No.: 14/103,079 Attorney Docket No.: 2557S I- 002057-US Page 5 of 8
. canceled
canceled
An electronic device, comprising: a semiconductor layer including an area, the area of the semiconductor layer including one of a depletion width of less than or equal to 3 nm and a constant doping density in overall; a metal layer connected to the area of the semiconductor layer; and a graphene between the metal layer and the area of the semiconductor layer, the graphene directly contacting the area of the semiconductor layer, the graphene is configured to reduce an energy barrier between the metal layer and the area of the semiconductor layer.
The electronic device of claim 16, wherein the graphene is one of a single layer and two layers.
The electronic device of claim 16, wherein the graphene does not have a bandgap so a Fe rm i level between the metal layer and the graphene does not vary, and the depletion width between the area of the semiconductor layer and the graphene is less than or equal to 3 nm.
The electronic device of claim 16, wherein the semiconductor layer is a substrate, and the substrate includes at least one of silicon, germanium, silicon-ger m anium, a II-VI group semiconductor, and a III -V group semiconductor. Application No.: 14/103,079 Attorney Docket No.: 2557S I -002057-US Page 6 of 8
(Previously Presented) The electronic device of claim 16, further comprising: a gate insulating layer connected to a portion of the semiconductor layer that is adjacent to the area of the semiconductor layer; and a gate electrode connected to the gate insulating layer, wherein the gate insulating layer is between the gate electrode and the portion of the semiconductor layer.
The electronic device of claim 16, wherein the area of the semiconductor layer is a first area of the semiconductor layer; the semiconductor layer includes a second area spaced apart from the first area; the electronic device further includes: a second metal layer connected to the second area, and a second graphene between the second metal layer and the second area; and the second graphene is configured to reduce an energy barrier between the second metal layer and the second area of the semiconductor layer.
The electronic device of claim 16, wherein a width of the graphene is less than a width of the
. canceled
Layer stacks claimed or described, ordered top of device to substrate.
electronic device (graphene-semiconductor-metal contact)
field effect transistor (FET) with graphene source/drain contacts
Materials described outside the worked examples.
semiconductor layer
graphene
Measurements and analyses referenced in the patent, with their drawing references.
FIG 5 is a cross-sectional view of a field effect transistor (FET) according to example embodiments,
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Voltage | 2–3 V | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
silicon
Si
germanium
Ge
silicon-germanium
SiGe
metal layer
FIG 7 is a cross-sectional view of a general metal oxide silicon field effect transistor (MOSFET) used in the simulation,
FIG 8 is a graph showing a change in a drain current along a change in a gate voltage in each of the j unctionless device and the general MOSFET, which is obtained by the simulation,
FIG 8 is a graph showing a change in a drain current along a change in a gate voltage in each of the j unctionless device and the general MOSFET, which is obtained by the simulation,
FIGS 11 A and 11 B are cross-sectional views of field effect transistors (FETs) according to example embodiments,
FIG 12 is a cross-sectional view of a field effect transistor (FET) according to example embodiments, and
| 1–10 nm |
| — |
Thickness | ≤ 3 nm | — |
Thickness | ≤ 10000000000000000000 cm | — |
silicon
Si
germanium
Ge
silicon-germanium
SiGe
metal layer
FIG 7 is a cross-sectional view of a general metal oxide silicon field effect transistor (MOSFET) used in the simulation,
FIG 8 is a graph showing a change in a drain current along a change in a gate voltage in each of the j unctionless device and the general MOSFET, which is obtained by the simulation,
FIG 8 is a graph showing a change in a drain current along a change in a gate voltage in each of the j unctionless device and the general MOSFET, which is obtained by the simulation,
FIGS 11 A and 11 B are cross-sectional views of field effect transistors (FETs) according to example embodiments,
FIG 12 is a cross-sectional view of a field effect transistor (FET) according to example embodiments, and
| 1–10 nm |
| — |
Thickness | ≤ 3 nm | — |
Thickness | ≤ 10000000000000000000 cm | — |
silicon
Si
germanium
Ge
silicon-germanium
SiGe
metal layer
FIG 7 is a cross-sectional view of a general metal oxide silicon field effect transistor (MOSFET) used in the simulation,
FIG 8 is a graph showing a change in a drain current along a change in a gate voltage in each of the j unctionless device and the general MOSFET, which is obtained by the simulation,
FIG 8 is a graph showing a change in a drain current along a change in a gate voltage in each of the j unctionless device and the general MOSFET, which is obtained by the simulation,
FIGS 11 A and 11 B are cross-sectional views of field effect transistors (FETs) according to example embodiments,
FIG 12 is a cross-sectional view of a field effect transistor (FET) according to example embodiments, and
| 1–10 nm |
| — |
Thickness | ≤ 3 nm | — |
Thickness | ≤ 10000000000000000000 cm | — |
silicon
Si
germanium
Ge
silicon-germanium
SiGe
metal layer
FIG 7 is a cross-sectional view of a general metal oxide silicon field effect transistor (MOSFET) used in the simulation,
FIG 8 is a graph showing a change in a drain current along a change in a gate voltage in each of the j unctionless device and the general MOSFET, which is obtained by the simulation,
FIG 8 is a graph showing a change in a drain current along a change in a gate voltage in each of the j unctionless device and the general MOSFET, which is obtained by the simulation,
FIGS 11 A and 11 B are cross-sectional views of field effect transistors (FETs) according to example embodiments,
FIG 12 is a cross-sectional view of a field effect transistor (FET) according to example embodiments, and
| 1–10 nm |
| — |
Thickness | ≤ 3 nm | — |
Thickness | ≤ 10000000000000000000 cm | — |