Patent
US 9,136,336INVERTER LOGIC DEVICES INCLUDING GRAPHENE FIELD EFFECT TRANSISTOR HAVING TUNABLE BARRIER
Jin-seong HEO
US
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Patent
Atlas literature
Patent
US 9,136,336Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view schematically illustrating a graphene switching device including a tunable barrier having a semiconductor barrier according to …
FIGS. 2A-2D are energy band diagrams for explaining an operation of the graphene switching device of
FIG. 3 is an I-V graph of an n-type graphene switching device according to example embodiments; [0028]
FIG. 4 is an I-V graph of a p-type graphene switching device according to example embodiments; [0029]
FIG. 5 is a cross-sectional view schematically illustrating a graphene switching device including a tunable barrier having a semiconductor barrier according to …
FIG. 6 is a cross-sectional view schematically illustrating a structure of an inverter logic device including two graphene field effect transistors according to …
FIG. 7, the first electrode 451 corresponds to a drain electrode of the n- FET and the second electrode 452 corresponds to a source electrode of the p-FET. An …
FIG. 8 is a cross-sectional view schematically illustrating a structure of an inverter logic device including two graphene field effect transistors according to …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An inverter logic device, comprising: a gate oxide on a back gate substrate; a first graphene layer and a second graphene layer physicall y separated from each other by a g ap on the gate oxide; a first electrode layer and a first semiconductor layer on a same surface of the first graphene layer and separated from each other; a second electrode layer and a second semiconductor layer on a same surface of the second graphene layer and separated from each other, wherein the first semiconductor layer is doped with a different type impurities selected from n-type impurities and p-type impurities than the second semiconductor layer; a third electrode on the first semiconductor layer te- fae eoverlapping the first graphene layer; a fourth electrode on the second semiconductor layer te- f aeeoverlappin g the second graphene layer; and an output electrode connected to the third electrode and the fourth electrode, wherein the first semiconductor layer faces the back gate substrate with the first graphene layer therebetween, and the second semiconductor layer faces the back gate substrate with the second graphene layer therebetween.
The inverter logic device of claim 1, wherein the first semiconductor layer and the second semiconductor layer are connected to each other or arranged close to each other, and Page 2 Application No. 13/593,708 Attorney Docket No. 2557 SI -001789-US the third electrode and the fourth electrode are integrally formed as a common electrode on the first semiconductor layer and the second semiconductor layer.
The inverter logic device of claim 1, wherein the first graphene layer and the second graphene layer are respectively separated from the third electrode and the fourth electrode.
(O R IGINAL) The inverter logic device of claim 1, wherein each of the first semiconductor layer and the second semiconductor layer includes one selected from the group consisting of silicon, germanium, silicon-germanium, I II -V group semiconductors, I I -VI group semiconductors and combinations thereof.
(O R IGINAL) The inverter logic device of claim 1, wherein each of the first semiconductor layer and the second semiconductor layer has a thickness of about 1 nm-about 10 nm.
The inverter logic device of claim 1, wherein energy gaps of the first semiconductor layer and the second semiconductor layer vary according to a gate voltage applied to the back gate substrate.
The inverter logic device of claim 1, wherein the inverter logic device includes n-type transistor having one of the first semiconductor and the second semiconductor having n-type impurities and p-type transistor having the other of the first semiconductor and the second semiconductor having p-type impurities.
. canceled
An inverter logic device, comprising: a first well on a conductive substrate and doped with first impurities; a second well doped with second impurities having a polarity different from a polarity of the first impurities; a first graphene layer covering the first well; a second graphene layer covering the second well and separated from the first graphene layer, wherein the first and second graphene layers are insulated from the conductive substrate; a first electrode on the first graphene layer to face the first insulation layer; a second electrode on the second graphene layer to face the second insulation layer; Page 3 App li cation No. 13/593,708 Attorney Docket No. 2557 SI -001789-US a gate oxide covering the first graphene layer and the second graphene layer; and a gate electrode on the gate oxide to face the first well and the second well. withdrawn
The inverter logic device of claim 9, further comprising: a first insulation layer on the conductive substrate to correspond to the first well, wherein the first graphene layer covers the first insulation layer; and a second insulation layer on the conductive substrate to correspond to the second well, wherein the second graphene layer covers the second insulation layer. withdrawn
The inverter logic device of claim 9, wherein each of the conductive substrate and the first and second wells includes one selected from the group consisting of silicon, germanium, silicon-germanium, I II -V group semiconductors, I I -VI group semiconductors and combinations thereof. withdrawn
The inverter logic device of claim 9, wherein the gate electrode is configured to receive an input signal, and the conductive substrate is configured to output an output signal. withdrawn
The inverter logic device of claim 9, wherein the conductive substrate is separated from the first graphene layer and the second graphene layer. withdrawn
The inverter logic device of claim 9, wherein energy gaps of the first well and the second well vary according to a voltage applied to the gate electrode. withdrawn
The inverter logic device of claim 9, wherein each of the first graphene layer and the second graphene layer includes a single layer to four layers of graphene. withdrawn
The inverter logic device of claim 9, wherein each of the first well and the second well has a thickness of about 1 nm-about 10 nm. withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
inverter logic device with back gate (first embodiment)
Materials described outside the worked examples.
graphene
n-type doped semiconductor layer
p-type doped semiconductor layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is an I-V graph of an n-type graphene switching device according to example embodiments; [0028]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
semiconductor layer thickness (claimed range) | 1–10 nm | n-type doped semiconductor layerp-type doped semiconductor layer |
doped well thickness (claimed range) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,136,336Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view schematically illustrating a graphene switching device including a tunable barrier having a semiconductor barrier according to …
FIGS. 2A-2D are energy band diagrams for explaining an operation of the graphene switching device of
FIG. 3 is an I-V graph of an n-type graphene switching device according to example embodiments; [0028]
FIG. 4 is an I-V graph of a p-type graphene switching device according to example embodiments; [0029]
FIG. 5 is a cross-sectional view schematically illustrating a graphene switching device including a tunable barrier having a semiconductor barrier according to …
FIG. 6 is a cross-sectional view schematically illustrating a structure of an inverter logic device including two graphene field effect transistors according to …
FIG. 7, the first electrode 451 corresponds to a drain electrode of the n- FET and the second electrode 452 corresponds to a source electrode of the p-FET. An …
FIG. 8 is a cross-sectional view schematically illustrating a structure of an inverter logic device including two graphene field effect transistors according to …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An inverter logic device, comprising: a gate oxide on a back gate substrate; a first graphene layer and a second graphene layer physicall y separated from each other by a g ap on the gate oxide; a first electrode layer and a first semiconductor layer on a same surface of the first graphene layer and separated from each other; a second electrode layer and a second semiconductor layer on a same surface of the second graphene layer and separated from each other, wherein the first semiconductor layer is doped with a different type impurities selected from n-type impurities and p-type impurities than the second semiconductor layer; a third electrode on the first semiconductor layer te- fae eoverlapping the first graphene layer; a fourth electrode on the second semiconductor layer te- f aeeoverlappin g the second graphene layer; and an output electrode connected to the third electrode and the fourth electrode, wherein the first semiconductor layer faces the back gate substrate with the first graphene layer therebetween, and the second semiconductor layer faces the back gate substrate with the second graphene layer therebetween.
The inverter logic device of claim 1, wherein the first semiconductor layer and the second semiconductor layer are connected to each other or arranged close to each other, and Page 2 Application No. 13/593,708 Attorney Docket No. 2557 SI -001789-US the third electrode and the fourth electrode are integrally formed as a common electrode on the first semiconductor layer and the second semiconductor layer.
The inverter logic device of claim 1, wherein the first graphene layer and the second graphene layer are respectively separated from the third electrode and the fourth electrode.
(O R IGINAL) The inverter logic device of claim 1, wherein each of the first semiconductor layer and the second semiconductor layer includes one selected from the group consisting of silicon, germanium, silicon-germanium, I II -V group semiconductors, I I -VI group semiconductors and combinations thereof.
(O R IGINAL) The inverter logic device of claim 1, wherein each of the first semiconductor layer and the second semiconductor layer has a thickness of about 1 nm-about 10 nm.
The inverter logic device of claim 1, wherein energy gaps of the first semiconductor layer and the second semiconductor layer vary according to a gate voltage applied to the back gate substrate.
The inverter logic device of claim 1, wherein the inverter logic device includes n-type transistor having one of the first semiconductor and the second semiconductor having n-type impurities and p-type transistor having the other of the first semiconductor and the second semiconductor having p-type impurities.
. canceled
An inverter logic device, comprising: a first well on a conductive substrate and doped with first impurities; a second well doped with second impurities having a polarity different from a polarity of the first impurities; a first graphene layer covering the first well; a second graphene layer covering the second well and separated from the first graphene layer, wherein the first and second graphene layers are insulated from the conductive substrate; a first electrode on the first graphene layer to face the first insulation layer; a second electrode on the second graphene layer to face the second insulation layer; Page 3 App li cation No. 13/593,708 Attorney Docket No. 2557 SI -001789-US a gate oxide covering the first graphene layer and the second graphene layer; and a gate electrode on the gate oxide to face the first well and the second well. withdrawn
The inverter logic device of claim 9, further comprising: a first insulation layer on the conductive substrate to correspond to the first well, wherein the first graphene layer covers the first insulation layer; and a second insulation layer on the conductive substrate to correspond to the second well, wherein the second graphene layer covers the second insulation layer. withdrawn
The inverter logic device of claim 9, wherein each of the conductive substrate and the first and second wells includes one selected from the group consisting of silicon, germanium, silicon-germanium, I II -V group semiconductors, I I -VI group semiconductors and combinations thereof. withdrawn
The inverter logic device of claim 9, wherein the gate electrode is configured to receive an input signal, and the conductive substrate is configured to output an output signal. withdrawn
The inverter logic device of claim 9, wherein the conductive substrate is separated from the first graphene layer and the second graphene layer. withdrawn
The inverter logic device of claim 9, wherein energy gaps of the first well and the second well vary according to a voltage applied to the gate electrode. withdrawn
The inverter logic device of claim 9, wherein each of the first graphene layer and the second graphene layer includes a single layer to four layers of graphene. withdrawn
The inverter logic device of claim 9, wherein each of the first well and the second well has a thickness of about 1 nm-about 10 nm. withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
inverter logic device with back gate (first embodiment)
Materials described outside the worked examples.
graphene
n-type doped semiconductor layer
p-type doped semiconductor layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is an I-V graph of an n-type graphene switching device according to example embodiments; [0028]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
semiconductor layer thickness (claimed range) | 1–10 nm | n-type doped semiconductor layerp-type doped semiconductor layer |
doped well thickness (claimed range) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,136,336Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view schematically illustrating a graphene switching device including a tunable barrier having a semiconductor barrier according to …
FIGS. 2A-2D are energy band diagrams for explaining an operation of the graphene switching device of
FIG. 3 is an I-V graph of an n-type graphene switching device according to example embodiments; [0028]
FIG. 4 is an I-V graph of a p-type graphene switching device according to example embodiments; [0029]
FIG. 5 is a cross-sectional view schematically illustrating a graphene switching device including a tunable barrier having a semiconductor barrier according to …
FIG. 6 is a cross-sectional view schematically illustrating a structure of an inverter logic device including two graphene field effect transistors according to …
FIG. 7, the first electrode 451 corresponds to a drain electrode of the n- FET and the second electrode 452 corresponds to a source electrode of the p-FET. An …
FIG. 8 is a cross-sectional view schematically illustrating a structure of an inverter logic device including two graphene field effect transistors according to …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An inverter logic device, comprising: a gate oxide on a back gate substrate; a first graphene layer and a second graphene layer physicall y separated from each other by a g ap on the gate oxide; a first electrode layer and a first semiconductor layer on a same surface of the first graphene layer and separated from each other; a second electrode layer and a second semiconductor layer on a same surface of the second graphene layer and separated from each other, wherein the first semiconductor layer is doped with a different type impurities selected from n-type impurities and p-type impurities than the second semiconductor layer; a third electrode on the first semiconductor layer te- fae eoverlapping the first graphene layer; a fourth electrode on the second semiconductor layer te- f aeeoverlappin g the second graphene layer; and an output electrode connected to the third electrode and the fourth electrode, wherein the first semiconductor layer faces the back gate substrate with the first graphene layer therebetween, and the second semiconductor layer faces the back gate substrate with the second graphene layer therebetween.
The inverter logic device of claim 1, wherein the first semiconductor layer and the second semiconductor layer are connected to each other or arranged close to each other, and Page 2 Application No. 13/593,708 Attorney Docket No. 2557 SI -001789-US the third electrode and the fourth electrode are integrally formed as a common electrode on the first semiconductor layer and the second semiconductor layer.
The inverter logic device of claim 1, wherein the first graphene layer and the second graphene layer are respectively separated from the third electrode and the fourth electrode.
(O R IGINAL) The inverter logic device of claim 1, wherein each of the first semiconductor layer and the second semiconductor layer includes one selected from the group consisting of silicon, germanium, silicon-germanium, I II -V group semiconductors, I I -VI group semiconductors and combinations thereof.
(O R IGINAL) The inverter logic device of claim 1, wherein each of the first semiconductor layer and the second semiconductor layer has a thickness of about 1 nm-about 10 nm.
The inverter logic device of claim 1, wherein energy gaps of the first semiconductor layer and the second semiconductor layer vary according to a gate voltage applied to the back gate substrate.
The inverter logic device of claim 1, wherein the inverter logic device includes n-type transistor having one of the first semiconductor and the second semiconductor having n-type impurities and p-type transistor having the other of the first semiconductor and the second semiconductor having p-type impurities.
. canceled
An inverter logic device, comprising: a first well on a conductive substrate and doped with first impurities; a second well doped with second impurities having a polarity different from a polarity of the first impurities; a first graphene layer covering the first well; a second graphene layer covering the second well and separated from the first graphene layer, wherein the first and second graphene layers are insulated from the conductive substrate; a first electrode on the first graphene layer to face the first insulation layer; a second electrode on the second graphene layer to face the second insulation layer; Page 3 App li cation No. 13/593,708 Attorney Docket No. 2557 SI -001789-US a gate oxide covering the first graphene layer and the second graphene layer; and a gate electrode on the gate oxide to face the first well and the second well. withdrawn
The inverter logic device of claim 9, further comprising: a first insulation layer on the conductive substrate to correspond to the first well, wherein the first graphene layer covers the first insulation layer; and a second insulation layer on the conductive substrate to correspond to the second well, wherein the second graphene layer covers the second insulation layer. withdrawn
The inverter logic device of claim 9, wherein each of the conductive substrate and the first and second wells includes one selected from the group consisting of silicon, germanium, silicon-germanium, I II -V group semiconductors, I I -VI group semiconductors and combinations thereof. withdrawn
The inverter logic device of claim 9, wherein the gate electrode is configured to receive an input signal, and the conductive substrate is configured to output an output signal. withdrawn
The inverter logic device of claim 9, wherein the conductive substrate is separated from the first graphene layer and the second graphene layer. withdrawn
The inverter logic device of claim 9, wherein energy gaps of the first well and the second well vary according to a voltage applied to the gate electrode. withdrawn
The inverter logic device of claim 9, wherein each of the first graphene layer and the second graphene layer includes a single layer to four layers of graphene. withdrawn
The inverter logic device of claim 9, wherein each of the first well and the second well has a thickness of about 1 nm-about 10 nm. withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
inverter logic device with back gate (first embodiment)
Materials described outside the worked examples.
graphene
n-type doped semiconductor layer
p-type doped semiconductor layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is an I-V graph of an n-type graphene switching device according to example embodiments; [0028]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
semiconductor layer thickness (claimed range) | 1–10 nm | n-type doped semiconductor layerp-type doped semiconductor layer |
doped well thickness (claimed range) |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,136,336Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view schematically illustrating a graphene switching device including a tunable barrier having a semiconductor barrier according to …
FIGS. 2A-2D are energy band diagrams for explaining an operation of the graphene switching device of
FIG. 3 is an I-V graph of an n-type graphene switching device according to example embodiments; [0028]
FIG. 4 is an I-V graph of a p-type graphene switching device according to example embodiments; [0029]
FIG. 5 is a cross-sectional view schematically illustrating a graphene switching device including a tunable barrier having a semiconductor barrier according to …
FIG. 6 is a cross-sectional view schematically illustrating a structure of an inverter logic device including two graphene field effect transistors according to …
FIG. 7, the first electrode 451 corresponds to a drain electrode of the n- FET and the second electrode 452 corresponds to a source electrode of the p-FET. An …
FIG. 8 is a cross-sectional view schematically illustrating a structure of an inverter logic device including two graphene field effect transistors according to …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An inverter logic device, comprising: a gate oxide on a back gate substrate; a first graphene layer and a second graphene layer physicall y separated from each other by a g ap on the gate oxide; a first electrode layer and a first semiconductor layer on a same surface of the first graphene layer and separated from each other; a second electrode layer and a second semiconductor layer on a same surface of the second graphene layer and separated from each other, wherein the first semiconductor layer is doped with a different type impurities selected from n-type impurities and p-type impurities than the second semiconductor layer; a third electrode on the first semiconductor layer te- fae eoverlapping the first graphene layer; a fourth electrode on the second semiconductor layer te- f aeeoverlappin g the second graphene layer; and an output electrode connected to the third electrode and the fourth electrode, wherein the first semiconductor layer faces the back gate substrate with the first graphene layer therebetween, and the second semiconductor layer faces the back gate substrate with the second graphene layer therebetween.
The inverter logic device of claim 1, wherein the first semiconductor layer and the second semiconductor layer are connected to each other or arranged close to each other, and Page 2 Application No. 13/593,708 Attorney Docket No. 2557 SI -001789-US the third electrode and the fourth electrode are integrally formed as a common electrode on the first semiconductor layer and the second semiconductor layer.
The inverter logic device of claim 1, wherein the first graphene layer and the second graphene layer are respectively separated from the third electrode and the fourth electrode.
(O R IGINAL) The inverter logic device of claim 1, wherein each of the first semiconductor layer and the second semiconductor layer includes one selected from the group consisting of silicon, germanium, silicon-germanium, I II -V group semiconductors, I I -VI group semiconductors and combinations thereof.
(O R IGINAL) The inverter logic device of claim 1, wherein each of the first semiconductor layer and the second semiconductor layer has a thickness of about 1 nm-about 10 nm.
The inverter logic device of claim 1, wherein energy gaps of the first semiconductor layer and the second semiconductor layer vary according to a gate voltage applied to the back gate substrate.
The inverter logic device of claim 1, wherein the inverter logic device includes n-type transistor having one of the first semiconductor and the second semiconductor having n-type impurities and p-type transistor having the other of the first semiconductor and the second semiconductor having p-type impurities.
. canceled
An inverter logic device, comprising: a first well on a conductive substrate and doped with first impurities; a second well doped with second impurities having a polarity different from a polarity of the first impurities; a first graphene layer covering the first well; a second graphene layer covering the second well and separated from the first graphene layer, wherein the first and second graphene layers are insulated from the conductive substrate; a first electrode on the first graphene layer to face the first insulation layer; a second electrode on the second graphene layer to face the second insulation layer; Page 3 App li cation No. 13/593,708 Attorney Docket No. 2557 SI -001789-US a gate oxide covering the first graphene layer and the second graphene layer; and a gate electrode on the gate oxide to face the first well and the second well. withdrawn
The inverter logic device of claim 9, further comprising: a first insulation layer on the conductive substrate to correspond to the first well, wherein the first graphene layer covers the first insulation layer; and a second insulation layer on the conductive substrate to correspond to the second well, wherein the second graphene layer covers the second insulation layer. withdrawn
The inverter logic device of claim 9, wherein each of the conductive substrate and the first and second wells includes one selected from the group consisting of silicon, germanium, silicon-germanium, I II -V group semiconductors, I I -VI group semiconductors and combinations thereof. withdrawn
The inverter logic device of claim 9, wherein the gate electrode is configured to receive an input signal, and the conductive substrate is configured to output an output signal. withdrawn
The inverter logic device of claim 9, wherein the conductive substrate is separated from the first graphene layer and the second graphene layer. withdrawn
The inverter logic device of claim 9, wherein energy gaps of the first well and the second well vary according to a voltage applied to the gate electrode. withdrawn
The inverter logic device of claim 9, wherein each of the first graphene layer and the second graphene layer includes a single layer to four layers of graphene. withdrawn
The inverter logic device of claim 9, wherein each of the first well and the second well has a thickness of about 1 nm-about 10 nm. withdrawn
Layer stacks claimed or described, ordered top of device to substrate.
inverter logic device with back gate (first embodiment)
Materials described outside the worked examples.
graphene
n-type doped semiconductor layer
p-type doped semiconductor layer
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3 is an I-V graph of an n-type graphene switching device according to example embodiments; [0028]
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
semiconductor layer thickness (claimed range) | 1–10 nm | n-type doped semiconductor layerp-type doped semiconductor layer |
doped well thickness (claimed range) |
Related documents with shared materials, methods, properties, or citations.
inverter logic device with conductive substrate and top gate (second embodiment, withdrawn)
doped semiconductor well
conductive substrate
gate oxide
silicon, germanium, silicon-germanium, III-V group semiconductors, II-VI group semiconductors
FIG. 3 is an I-V graph of an n-type graphene switching device according to example embodiments; [0028]
FIG. 4 is an I-V graph of a p-type graphene switching device according to example embodiments; [0029]
FIG. 4 is an I-V graph of a p-type graphene switching device according to example embodiments; [0029]
FIG. 6 is a cross-sectional view schematically illustrating a structure of an inverter logic device including two graphene field effect transistors according to …
FIG. 7, the first electrode 451 corresponds to a drain electrode of the n- FET and the second electrode 452 corresponds to a source electrode of the p-FET. An …
FIG. 8 is a cross-sectional view schematically illustrating a structure of an inverter logic device including two graphene field effect transistors according to …
| 1–10 nm |
doped semiconductor well |
inverter logic device with conductive substrate and top gate (second embodiment, withdrawn)
doped semiconductor well
conductive substrate
gate oxide
silicon, germanium, silicon-germanium, III-V group semiconductors, II-VI group semiconductors
FIG. 3 is an I-V graph of an n-type graphene switching device according to example embodiments; [0028]
FIG. 4 is an I-V graph of a p-type graphene switching device according to example embodiments; [0029]
FIG. 4 is an I-V graph of a p-type graphene switching device according to example embodiments; [0029]
FIG. 6 is a cross-sectional view schematically illustrating a structure of an inverter logic device including two graphene field effect transistors according to …
FIG. 7, the first electrode 451 corresponds to a drain electrode of the n- FET and the second electrode 452 corresponds to a source electrode of the p-FET. An …
FIG. 8 is a cross-sectional view schematically illustrating a structure of an inverter logic device including two graphene field effect transistors according to …
| 1–10 nm |
doped semiconductor well |
inverter logic device with conductive substrate and top gate (second embodiment, withdrawn)
doped semiconductor well
conductive substrate
gate oxide
silicon, germanium, silicon-germanium, III-V group semiconductors, II-VI group semiconductors
FIG. 3 is an I-V graph of an n-type graphene switching device according to example embodiments; [0028]
FIG. 4 is an I-V graph of a p-type graphene switching device according to example embodiments; [0029]
FIG. 4 is an I-V graph of a p-type graphene switching device according to example embodiments; [0029]
FIG. 6 is a cross-sectional view schematically illustrating a structure of an inverter logic device including two graphene field effect transistors according to …
FIG. 7, the first electrode 451 corresponds to a drain electrode of the n- FET and the second electrode 452 corresponds to a source electrode of the p-FET. An …
FIG. 8 is a cross-sectional view schematically illustrating a structure of an inverter logic device including two graphene field effect transistors according to …
| 1–10 nm |
doped semiconductor well |
inverter logic device with conductive substrate and top gate (second embodiment, withdrawn)
doped semiconductor well
conductive substrate
gate oxide
silicon, germanium, silicon-germanium, III-V group semiconductors, II-VI group semiconductors
FIG. 3 is an I-V graph of an n-type graphene switching device according to example embodiments; [0028]
FIG. 4 is an I-V graph of a p-type graphene switching device according to example embodiments; [0029]
FIG. 4 is an I-V graph of a p-type graphene switching device according to example embodiments; [0029]
FIG. 6 is a cross-sectional view schematically illustrating a structure of an inverter logic device including two graphene field effect transistors according to …
FIG. 7, the first electrode 451 corresponds to a drain electrode of the n- FET and the second electrode 452 corresponds to a source electrode of the p-FET. An …
FIG. 8 is a cross-sectional view schematically illustrating a structure of an inverter logic device including two graphene field effect transistors according to …
| 1–10 nm |
doped semiconductor well |