Patent
US 10,243,076TERNARY BARRISTOR WITH SCHOTTKY JUNCTION GRAPHENE SEMICONDUCTOR
Byoung Hun LEE
US
Copyright © 2026 Matter42. All rights reserved.
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US 10,243,076Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 8 is an Id-Vg graph of an N-type barrist o r of the graphene-based ternary barristor according to an embodiment o f the present invention. DESCR IPTI ON …
FIGS. 2 to 9 are diagrams illustrating a manufacturing process for a graphene-based CLEAN SUBSTITUTE SPECIFICATION ternary barristor according to an embodiment …
FIG. 3 according to an emb o diment of the present i nventi on. FI G. 5 is perspective view sh ow ing a source electr o de layer connected to patterned …
FIG. 4 is perspective view showing a graphene channel layer formed on the gate i nsulat io n layer of
FIG. 5 according to an embodiment of the present invention.
FIGS. 6 and 7, a PR c oa ting layer 5 5 0 may be f o rmed to co ver the source electrode layer 500 and the entire substrate in order to dope the graphene …
FIG. 7 is perspective view showing second graphene channel o f the patterned graphene channel layer of
FIG. 8 is perspective view sh ow ing the f irst graphene channel and the sec ond graphene channel according to an embodiment o f the present invention. FIG 9 …
FIG. 9, a drain electrode layer 600 is formed opposite to the source electr o de, and is electrically c o nnected to another p o rti o n of the fi rst graphene …
FIGS. 11 to 16 are band diagrams illustrating an operation of a barristor according to an embodiment of the present invention. The same reference numerals in …
FIG. 12 is diagram showing drain current with respect to gate voltage when bias is not appl i ed to gate electrode layer of the barr isto r according to an emb …
FIG. 13 is band diagram when negative bias is applied to gate electrode layer with respect to source electrode of the barr isto r according to an e mbo diment …
FIG. 14 is diagram showing drain current with respect to gate voltage when negative bias is applied to gate electrode layer with respect to source electrode of …
FIG. 15 is band diagram when positive bias is applied to gate electrode layer with respect to source electrode of the barr isto r according to an e mbo diment …
FIG. 16 is diagram showing drain current with respect to gate voltage when positive bias is applied to gate electrode l ayer with respect to source electrode …
FIGS. 17 and 1 8, Id-Vg graphs having 3-step signal o f a graphene-based ternary barrist o r according to an embodiment of the present invention are shown. …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) A graphene-based ternary barristor using a graphene channel having a region with two different Fermi levels, the graphene-based ternary barristor comprising: a substrate; a gate electrode layer formed on a center of the substrate; a gate insulation layer formed to electrically block the gate electrode layer; a graphene channel layer formed on the gate insulation layer, wherein the graphene channel layer comprises a first graphene channel and a second graphene channel; a source electrode layer electrically connected to one side of the graphene channel layer; and a drain electrode layer electrically connected to opposite sides of the source electrode layer, wherein the first graphene channel and the second graphene channel are complementarily doped with each other, and are connected in parallel to the source electrode layer and the drain electrode layer, so that the first graphene channel and the second graphene channel have two different Fermi levels from each other. Currently amended
The graphene-based ternary barristor of claim 1, wherein the graphene channel layer is doped or surface-modified with P-type and N-type dopants through a chemical or physical method. Original
The graphene-based ternary barristor of claim 1, wherein the graphene channel layer forms a Schottky barrier by using a heterogeneous junction with the drain electrode. Original
Canceled
The graphene-based ternary barristor of claim _, wherein when a voltage is applied to the gate electrode layer, the Fermi level is moved by the graphene channel layer to adj u st a barrier height. Original
The graphene-based ternary barristor of claim different Fermi levels and adjusts a height of an means of an external electric field. and thus the as a single device with three separate signals. 1, wherein the graphene channel layer has two energy b arrier by adjusting the Fermi levels by graphene-based ternary b arristor is implemented Original
Layer stacks claimed or described, ordered top of device to substrate.
graphene-based ternary barristor
Materials described outside the worked examples.
graphene
substrate
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 8 is an Id-Vg graph of an N-type barrist o r of the graphene-based ternary barristor according to an embodiment o f the present invention. DESCR IPTI ON …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,243,076Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 8 is an Id-Vg graph of an N-type barrist o r of the graphene-based ternary barristor according to an embodiment o f the present invention. DESCR IPTI ON …
FIGS. 2 to 9 are diagrams illustrating a manufacturing process for a graphene-based CLEAN SUBSTITUTE SPECIFICATION ternary barristor according to an embodiment …
FIG. 3 according to an emb o diment of the present i nventi on. FI G. 5 is perspective view sh ow ing a source electr o de layer connected to patterned …
FIG. 4 is perspective view showing a graphene channel layer formed on the gate i nsulat io n layer of
FIG. 5 according to an embodiment of the present invention.
FIGS. 6 and 7, a PR c oa ting layer 5 5 0 may be f o rmed to co ver the source electrode layer 500 and the entire substrate in order to dope the graphene …
FIG. 7 is perspective view showing second graphene channel o f the patterned graphene channel layer of
FIG. 8 is perspective view sh ow ing the f irst graphene channel and the sec ond graphene channel according to an embodiment o f the present invention. FIG 9 …
FIG. 9, a drain electrode layer 600 is formed opposite to the source electr o de, and is electrically c o nnected to another p o rti o n of the fi rst graphene …
FIGS. 11 to 16 are band diagrams illustrating an operation of a barristor according to an embodiment of the present invention. The same reference numerals in …
FIG. 12 is diagram showing drain current with respect to gate voltage when bias is not appl i ed to gate electrode layer of the barr isto r according to an emb …
FIG. 13 is band diagram when negative bias is applied to gate electrode layer with respect to source electrode of the barr isto r according to an e mbo diment …
FIG. 14 is diagram showing drain current with respect to gate voltage when negative bias is applied to gate electrode layer with respect to source electrode of …
FIG. 15 is band diagram when positive bias is applied to gate electrode layer with respect to source electrode of the barr isto r according to an e mbo diment …
FIG. 16 is diagram showing drain current with respect to gate voltage when positive bias is applied to gate electrode l ayer with respect to source electrode …
FIGS. 17 and 1 8, Id-Vg graphs having 3-step signal o f a graphene-based ternary barrist o r according to an embodiment of the present invention are shown. …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) A graphene-based ternary barristor using a graphene channel having a region with two different Fermi levels, the graphene-based ternary barristor comprising: a substrate; a gate electrode layer formed on a center of the substrate; a gate insulation layer formed to electrically block the gate electrode layer; a graphene channel layer formed on the gate insulation layer, wherein the graphene channel layer comprises a first graphene channel and a second graphene channel; a source electrode layer electrically connected to one side of the graphene channel layer; and a drain electrode layer electrically connected to opposite sides of the source electrode layer, wherein the first graphene channel and the second graphene channel are complementarily doped with each other, and are connected in parallel to the source electrode layer and the drain electrode layer, so that the first graphene channel and the second graphene channel have two different Fermi levels from each other. Currently amended
The graphene-based ternary barristor of claim 1, wherein the graphene channel layer is doped or surface-modified with P-type and N-type dopants through a chemical or physical method. Original
The graphene-based ternary barristor of claim 1, wherein the graphene channel layer forms a Schottky barrier by using a heterogeneous junction with the drain electrode. Original
Canceled
The graphene-based ternary barristor of claim _, wherein when a voltage is applied to the gate electrode layer, the Fermi level is moved by the graphene channel layer to adj u st a barrier height. Original
The graphene-based ternary barristor of claim different Fermi levels and adjusts a height of an means of an external electric field. and thus the as a single device with three separate signals. 1, wherein the graphene channel layer has two energy b arrier by adjusting the Fermi levels by graphene-based ternary b arristor is implemented Original
Layer stacks claimed or described, ordered top of device to substrate.
graphene-based ternary barristor
Materials described outside the worked examples.
graphene
substrate
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 8 is an Id-Vg graph of an N-type barrist o r of the graphene-based ternary barristor according to an embodiment o f the present invention. DESCR IPTI ON …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,243,076Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 8 is an Id-Vg graph of an N-type barrist o r of the graphene-based ternary barristor according to an embodiment o f the present invention. DESCR IPTI ON …
FIGS. 2 to 9 are diagrams illustrating a manufacturing process for a graphene-based CLEAN SUBSTITUTE SPECIFICATION ternary barristor according to an embodiment …
FIG. 3 according to an emb o diment of the present i nventi on. FI G. 5 is perspective view sh ow ing a source electr o de layer connected to patterned …
FIG. 4 is perspective view showing a graphene channel layer formed on the gate i nsulat io n layer of
FIG. 5 according to an embodiment of the present invention.
FIGS. 6 and 7, a PR c oa ting layer 5 5 0 may be f o rmed to co ver the source electrode layer 500 and the entire substrate in order to dope the graphene …
FIG. 7 is perspective view showing second graphene channel o f the patterned graphene channel layer of
FIG. 8 is perspective view sh ow ing the f irst graphene channel and the sec ond graphene channel according to an embodiment o f the present invention. FIG 9 …
FIG. 9, a drain electrode layer 600 is formed opposite to the source electr o de, and is electrically c o nnected to another p o rti o n of the fi rst graphene …
FIGS. 11 to 16 are band diagrams illustrating an operation of a barristor according to an embodiment of the present invention. The same reference numerals in …
FIG. 12 is diagram showing drain current with respect to gate voltage when bias is not appl i ed to gate electrode layer of the barr isto r according to an emb …
FIG. 13 is band diagram when negative bias is applied to gate electrode layer with respect to source electrode of the barr isto r according to an e mbo diment …
FIG. 14 is diagram showing drain current with respect to gate voltage when negative bias is applied to gate electrode layer with respect to source electrode of …
FIG. 15 is band diagram when positive bias is applied to gate electrode layer with respect to source electrode of the barr isto r according to an e mbo diment …
FIG. 16 is diagram showing drain current with respect to gate voltage when positive bias is applied to gate electrode l ayer with respect to source electrode …
FIGS. 17 and 1 8, Id-Vg graphs having 3-step signal o f a graphene-based ternary barrist o r according to an embodiment of the present invention are shown. …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) A graphene-based ternary barristor using a graphene channel having a region with two different Fermi levels, the graphene-based ternary barristor comprising: a substrate; a gate electrode layer formed on a center of the substrate; a gate insulation layer formed to electrically block the gate electrode layer; a graphene channel layer formed on the gate insulation layer, wherein the graphene channel layer comprises a first graphene channel and a second graphene channel; a source electrode layer electrically connected to one side of the graphene channel layer; and a drain electrode layer electrically connected to opposite sides of the source electrode layer, wherein the first graphene channel and the second graphene channel are complementarily doped with each other, and are connected in parallel to the source electrode layer and the drain electrode layer, so that the first graphene channel and the second graphene channel have two different Fermi levels from each other. Currently amended
The graphene-based ternary barristor of claim 1, wherein the graphene channel layer is doped or surface-modified with P-type and N-type dopants through a chemical or physical method. Original
The graphene-based ternary barristor of claim 1, wherein the graphene channel layer forms a Schottky barrier by using a heterogeneous junction with the drain electrode. Original
Canceled
The graphene-based ternary barristor of claim _, wherein when a voltage is applied to the gate electrode layer, the Fermi level is moved by the graphene channel layer to adj u st a barrier height. Original
The graphene-based ternary barristor of claim different Fermi levels and adjusts a height of an means of an external electric field. and thus the as a single device with three separate signals. 1, wherein the graphene channel layer has two energy b arrier by adjusting the Fermi levels by graphene-based ternary b arristor is implemented Original
Layer stacks claimed or described, ordered top of device to substrate.
graphene-based ternary barristor
Materials described outside the worked examples.
graphene
substrate
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 8 is an Id-Vg graph of an N-type barrist o r of the graphene-based ternary barristor according to an embodiment o f the present invention. DESCR IPTI ON …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,243,076Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 8 is an Id-Vg graph of an N-type barrist o r of the graphene-based ternary barristor according to an embodiment o f the present invention. DESCR IPTI ON …
FIGS. 2 to 9 are diagrams illustrating a manufacturing process for a graphene-based CLEAN SUBSTITUTE SPECIFICATION ternary barristor according to an embodiment …
FIG. 3 according to an emb o diment of the present i nventi on. FI G. 5 is perspective view sh ow ing a source electr o de layer connected to patterned …
FIG. 4 is perspective view showing a graphene channel layer formed on the gate i nsulat io n layer of
FIG. 5 according to an embodiment of the present invention.
FIGS. 6 and 7, a PR c oa ting layer 5 5 0 may be f o rmed to co ver the source electrode layer 500 and the entire substrate in order to dope the graphene …
FIG. 7 is perspective view showing second graphene channel o f the patterned graphene channel layer of
FIG. 8 is perspective view sh ow ing the f irst graphene channel and the sec ond graphene channel according to an embodiment o f the present invention. FIG 9 …
FIG. 9, a drain electrode layer 600 is formed opposite to the source electr o de, and is electrically c o nnected to another p o rti o n of the fi rst graphene …
FIGS. 11 to 16 are band diagrams illustrating an operation of a barristor according to an embodiment of the present invention. The same reference numerals in …
FIG. 12 is diagram showing drain current with respect to gate voltage when bias is not appl i ed to gate electrode layer of the barr isto r according to an emb …
FIG. 13 is band diagram when negative bias is applied to gate electrode layer with respect to source electrode of the barr isto r according to an e mbo diment …
FIG. 14 is diagram showing drain current with respect to gate voltage when negative bias is applied to gate electrode layer with respect to source electrode of …
FIG. 15 is band diagram when positive bias is applied to gate electrode layer with respect to source electrode of the barr isto r according to an e mbo diment …
FIG. 16 is diagram showing drain current with respect to gate voltage when positive bias is applied to gate electrode l ayer with respect to source electrode …
FIGS. 17 and 1 8, Id-Vg graphs having 3-step signal o f a graphene-based ternary barrist o r according to an embodiment of the present invention are shown. …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) A graphene-based ternary barristor using a graphene channel having a region with two different Fermi levels, the graphene-based ternary barristor comprising: a substrate; a gate electrode layer formed on a center of the substrate; a gate insulation layer formed to electrically block the gate electrode layer; a graphene channel layer formed on the gate insulation layer, wherein the graphene channel layer comprises a first graphene channel and a second graphene channel; a source electrode layer electrically connected to one side of the graphene channel layer; and a drain electrode layer electrically connected to opposite sides of the source electrode layer, wherein the first graphene channel and the second graphene channel are complementarily doped with each other, and are connected in parallel to the source electrode layer and the drain electrode layer, so that the first graphene channel and the second graphene channel have two different Fermi levels from each other. Currently amended
The graphene-based ternary barristor of claim 1, wherein the graphene channel layer is doped or surface-modified with P-type and N-type dopants through a chemical or physical method. Original
The graphene-based ternary barristor of claim 1, wherein the graphene channel layer forms a Schottky barrier by using a heterogeneous junction with the drain electrode. Original
Canceled
The graphene-based ternary barristor of claim _, wherein when a voltage is applied to the gate electrode layer, the Fermi level is moved by the graphene channel layer to adj u st a barrier height. Original
The graphene-based ternary barristor of claim different Fermi levels and adjusts a height of an means of an external electric field. and thus the as a single device with three separate signals. 1, wherein the graphene channel layer has two energy b arrier by adjusting the Fermi levels by graphene-based ternary b arristor is implemented Original
Layer stacks claimed or described, ordered top of device to substrate.
graphene-based ternary barristor
Materials described outside the worked examples.
graphene
substrate
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 8 is an Id-Vg graph of an N-type barrist o r of the graphene-based ternary barristor according to an embodiment o f the present invention. DESCR IPTI ON …
Related documents with shared materials, methods, properties, or citations.
gate insulation layer material
gate electrode material
FIG. 9, a drain electrode layer 600 is formed opposite to the source electr o de, and is electrically c o nnected to another p o rti o n of the fi rst graphene …
FIGS. 11 to 16 are band diagrams illustrating an operation of a barristor according to an embodiment of the present invention. The same reference numerals in …
FIG. 12 is diagram showing drain current with respect to gate voltage when bias is not appl i ed to gate electrode layer of the barr isto r according to an emb …
FIG. 14 is diagram showing drain current with respect to gate voltage when negative bias is applied to gate electrode layer with respect to source electrode of …
FIG. 16 is diagram showing drain current with respect to gate voltage when positive bias is applied to gate electrode l ayer with respect to source electrode …
FIGS. 17 and 1 8, Id-Vg graphs having 3-step signal o f a graphene-based ternary barrist o r according to an embodiment of the present invention are shown. …
gate insulation layer material
gate electrode material
FIG. 9, a drain electrode layer 600 is formed opposite to the source electr o de, and is electrically c o nnected to another p o rti o n of the fi rst graphene …
FIGS. 11 to 16 are band diagrams illustrating an operation of a barristor according to an embodiment of the present invention. The same reference numerals in …
FIG. 12 is diagram showing drain current with respect to gate voltage when bias is not appl i ed to gate electrode layer of the barr isto r according to an emb …
FIG. 14 is diagram showing drain current with respect to gate voltage when negative bias is applied to gate electrode layer with respect to source electrode of …
FIG. 16 is diagram showing drain current with respect to gate voltage when positive bias is applied to gate electrode l ayer with respect to source electrode …
FIGS. 17 and 1 8, Id-Vg graphs having 3-step signal o f a graphene-based ternary barrist o r according to an embodiment of the present invention are shown. …
gate insulation layer material
gate electrode material
FIG. 9, a drain electrode layer 600 is formed opposite to the source electr o de, and is electrically c o nnected to another p o rti o n of the fi rst graphene …
FIGS. 11 to 16 are band diagrams illustrating an operation of a barristor according to an embodiment of the present invention. The same reference numerals in …
FIG. 12 is diagram showing drain current with respect to gate voltage when bias is not appl i ed to gate electrode layer of the barr isto r according to an emb …
FIG. 14 is diagram showing drain current with respect to gate voltage when negative bias is applied to gate electrode layer with respect to source electrode of …
FIG. 16 is diagram showing drain current with respect to gate voltage when positive bias is applied to gate electrode l ayer with respect to source electrode …
FIGS. 17 and 1 8, Id-Vg graphs having 3-step signal o f a graphene-based ternary barrist o r according to an embodiment of the present invention are shown. …
gate insulation layer material
gate electrode material
FIG. 9, a drain electrode layer 600 is formed opposite to the source electr o de, and is electrically c o nnected to another p o rti o n of the fi rst graphene …
FIGS. 11 to 16 are band diagrams illustrating an operation of a barristor according to an embodiment of the present invention. The same reference numerals in …
FIG. 12 is diagram showing drain current with respect to gate voltage when bias is not appl i ed to gate electrode layer of the barr isto r according to an emb …
FIG. 14 is diagram showing drain current with respect to gate voltage when negative bias is applied to gate electrode layer with respect to source electrode of …
FIG. 16 is diagram showing drain current with respect to gate voltage when positive bias is applied to gate electrode l ayer with respect to source electrode …
FIGS. 17 and 1 8, Id-Vg graphs having 3-step signal o f a graphene-based ternary barrist o r according to an embodiment of the present invention are shown. …