Patent
US 10,607,989GRAPHENE FET DEVICES, SYSTEMS, AND METHODS OF USING THE SAME FOR SEQUENCING NUCLEIC ACIDS
Paul Hoffman
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,607,989Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1H is an illustration of a graphene layered substrate of FIG. lA configured as a chemically-sensitive field-effect transistor having a reaction layer …
FIG. 2A is an illustration of a chemically-sensitive field-effect transistor having a graphene layered well structure, such as for a system for analysis of …
FIG. 3B is a block diagram of a circuitry component for a system for analysis of biological or chemical materials. [00111]
FIG. 4A, such as for a system for analysis of biological or chemical materials, utilizing an electric field for positioning of a nano- or micro- bead. [00119] …
FIG. 5 A is an illustration of the substrate of FIG. l A, having a silicon dioxide layer positioned above a graphene layered reaction zone, and utilizing a …
FIG. 6 I is a graph of an I-Vg curve illustrating a check-slope of the I-Vg curve on one or both sides (Gm & proportional to mobility),and use of a solution …
FIG. 7E is a graph of frequency vs. normalized power spectral density for a graphene FET of the present invention. [00134]
FIG. 8A is an illustration of a chemically-sensitive field-effect transistor with a graphene layered well structure and having a permeable membrane associated …
FIG. 9D is an illustration of an optical readout of DNA sequencing using nanomaterials. [00142]
FIG. 10 A is a block diagram of components for a system for analysis of biological or chemical materials. [00143] FIG. lO B is an illustration of an exemplary …
FIG. 11 is an illustration of various planar source and drain electrode designs, including interdigitated designs. [00145]
FIG. 12 is a cross-section of a well opening stopping on an analyte- sensitive layer. [00146]
FIG. 13 is an illustration highlighting a second analyte-sensitive layer coating the walls of a well. [00147]
FIG. 14 is an illustration of using the well walls to create 3D interdigitated electrodes. [00148]
FIG. 15 is an illustration of the well structure of
FIG. 16 is an illustration showing a metal pattern in a deep trench created by photolithography. [00150]
FIG. 17. SVG 16025794.07-02-2018.JJ₄UL₆₁LRXEAPX0.SPEC.40.1.2063.162.2084.197.svg 0.117 0.07 Chemistry Black and white [00158]
FIG. 18A illustrates a graphene with channels or divots for water access and more efficient bubble transfer growth step of direct bond transfer via Van der Waals …
FIG. 19D illustrates a drain solution (while the graphene is aligned to the wafer) to transfer a layer onto a target step of the alternative option for the …
FIG. 20D illustrates a ROIC preparation and ROIC alignment step of direct bond transfer via fusion bonding. SVG …
FIG. 21D illustrates a bonding the graphene layer to the target step of an adhesive temporary bond material process. [00177]
FIG. 22A illustrates an adhesive temporary bond material process. [00181]
FIG. 23C illustrates a tape peel and graphene transfer step of an adhesive temporary bond material process with a nickel deposition layer. SVG …
FIG. 24A is an isolated view of a CMOS wafer step for employment in the fabrication methods herein described. [00188]
FIG. 25E illustrates a bonding a cover material to a ROIC wafer top insulator step of direct bond transfer via fusion bonding. [00198]
FIG. 26A illustrates a graphene on a ROIC wafer step of a CMOS integration method. SVG 16025794.07-02-2018.JJ₄UL₆₁LRXEAPX0.SPEC.43.1.2063.162.2084.197.svg …
FIG. 27 is an illustration of a top plane view of a source and drain electrodes at the bottom of a well. SVG …
FIG. 28 is an illustration of using alternating vertical metal layers to create an interdigitated type of effect to maximize the of ratio channel width to …
FIG. 29 is an illustration of the structure of
FIG. 30 is an illustration of using alternating vertical layers of metal and transistor material to create an interdigitated type of effect to maximize the …
FIG. 31H. This results in the fully formed layer stack depicted in
FIG. 32B. In a subsequent step (not shown in the figures) the formation of the electrode material over or on the patterned channel material will also fill these …
FIG. 33 is an illustration of a well that uses carbon nanotubes to create interdigitated transistors in a vertical direction. [00219] Having briefly described …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming an integrated circuit for use in performing a nucleic acid sequencing reaction, the method comprising: providing a semi-conducting substrate comprising a plurality of extended planar surfaces offset from one another by a first thickness, being defined by a plurality of side members, and having one or more transistor elements positioned between the plurality of surfaces; depositing a first insulating dielectric layer onto a top of the planar surfaces of the substrate, and extending across each planar surface from one side member to another side member; forming a plurality of trenches in the first insulating dielectric layer, each trench offset from the other by a distance, the distance forming a channel region; depositing a first layer of conductive material into each of the trenches to form a plurality of electrodes therein, a first electrode serving as a source electrode, and a second electrode serving as a drain electrode, the source and drain electrodes in contact with the one or more transistor elements; conditioning the first insulating dielectric layer in a manner so that a side and top surface of each of the plurality of electrodes extends above a surface of the first insulating dielectric layer; and depositing a 2D material layer onto the side and top surface of each of the plurality of electrodes and across the channel region to thereby form a channel between the electrodes. Original
The method according to claim 1, wherein the 2D material comprises a material selected from the group consisting of: Graphene; Molybdenum disulfide (M o S 2); Phosphorene (black phosphorous); Silicene, Borophene, Tungsten disulfide (WS₂); Boron Nitride; WSe2; Stanene (2D tin); Graphane; Germanane; Nickel H I TP; and Mxenes (Ti₂C, [T iO.5,Nb O. 5], V₂C, Nb₂C, Ti₃C2, Ti₃CN, Nb₄C3,Ta₄C₃). Original
The method according to claim 1, wherein the step of conditioning the first insulating dielectric layer is accomplished by etching. Original
The method according to claim 1, wherein the step of conditioning the first insulating dielectric layer further comprises depositing a second layer of conductive material on each of the plurality of electrodes so that each of the plurality of electrodes extends further above the surface of the insulating dielectric layer. Original
The method according to claim 1, further comprising forming an opening in the 2D material layer proximate each electrode so as to expose the top surface of each electrode. Original
The method according to claim 1, further comprising patterning the 2D material layer. Original
A method of forming an integrated circuit for use in performing a nucleic acid sequencing reaction, the method comprising: providing a semi-conducting substrate comprising a plurality of extended planar surfaces offset from one another by a first thickness, being surrounded by a plurality of side members, and having one or more transistor elements positioned between the plurality of surfaces; providing a first insulating dielectric layer on top of the planar surfaces of the substrate, and extending across each planar surface from one side member to another side member; forming a plurality of trenches in the first insulating dielectric layer, each trench offset from the other by a distance, the distance forming a channel region; depositing a first layer of conductive material into each of the trenches to form a plurality of electrodes therein, a first electrode serving as a source electrode, and a second electrode serving as a drain electrode, the source and drain electrodes in contact with the one or more transistor elements; depositing a 2D material layer onto the side and top surface of each of the plurality of electrodes and across the channel region to thereby form a channel between the electrodes; forming an opening in the 2D material proximate each electrode so as to expose at least the top surface of each electrode; and depositing a second layer of conductive material over each opening of the 2D material layer so that the second layer of conductive material contacts at least the top surface of the electrode, fills the opening, and further extends above the 2D material layer so as to contact a side and top surface of the 2D material layer. Original
The method according to claim 11, further comprising conditioning the first insulating dielectric layer in a manner so that a surface of each of the plurality of electrodes extends above a surface of the first insulating dielectric layer. Original
A method for securing an electrode to a 2D material layer, the method comprising: providing a semi-conducting substrate, the substrate having a planar surface; providing a first insulating dielectric layer onto the top planar surface of the substrate, the first insulating dielectric layer having a top surface; preparing a plurality of electrodes within the first insulating dielectric layer, each of the plurality of electrodes having a dimension even with or projecting above the top surface of the first insulating dielectric surface; depositing a 2D material layer on the plurality of electrodes to form a contact between the electrodes and the 2D material layer; and patterning the 2D material layer to form at least one channel contacting an electrode on each of the ends of the channel. Original
The method according to claim 16, wherein the plurality of electrodes comprise a first electrode serving as a source electrode, and a second electrode serving as a drain electrode. Original
. Canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene FET integrated circuit for nucleic acid sequencing
Materials described outside the worked examples.
semi-conducting substrate
conductive material (electrodes)
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1H is an illustration of a graphene layered substrate of FIG. lA configured as a chemically-sensitive field-effect transistor having a reaction layer …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.05–3 µm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,607,989Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1H is an illustration of a graphene layered substrate of FIG. lA configured as a chemically-sensitive field-effect transistor having a reaction layer …
FIG. 2A is an illustration of a chemically-sensitive field-effect transistor having a graphene layered well structure, such as for a system for analysis of …
FIG. 3B is a block diagram of a circuitry component for a system for analysis of biological or chemical materials. [00111]
FIG. 4A, such as for a system for analysis of biological or chemical materials, utilizing an electric field for positioning of a nano- or micro- bead. [00119] …
FIG. 5 A is an illustration of the substrate of FIG. l A, having a silicon dioxide layer positioned above a graphene layered reaction zone, and utilizing a …
FIG. 6 I is a graph of an I-Vg curve illustrating a check-slope of the I-Vg curve on one or both sides (Gm & proportional to mobility),and use of a solution …
FIG. 7E is a graph of frequency vs. normalized power spectral density for a graphene FET of the present invention. [00134]
FIG. 8A is an illustration of a chemically-sensitive field-effect transistor with a graphene layered well structure and having a permeable membrane associated …
FIG. 9D is an illustration of an optical readout of DNA sequencing using nanomaterials. [00142]
FIG. 10 A is a block diagram of components for a system for analysis of biological or chemical materials. [00143] FIG. lO B is an illustration of an exemplary …
FIG. 11 is an illustration of various planar source and drain electrode designs, including interdigitated designs. [00145]
FIG. 12 is a cross-section of a well opening stopping on an analyte- sensitive layer. [00146]
FIG. 13 is an illustration highlighting a second analyte-sensitive layer coating the walls of a well. [00147]
FIG. 14 is an illustration of using the well walls to create 3D interdigitated electrodes. [00148]
FIG. 15 is an illustration of the well structure of
FIG. 16 is an illustration showing a metal pattern in a deep trench created by photolithography. [00150]
FIG. 17. SVG 16025794.07-02-2018.JJ₄UL₆₁LRXEAPX0.SPEC.40.1.2063.162.2084.197.svg 0.117 0.07 Chemistry Black and white [00158]
FIG. 18A illustrates a graphene with channels or divots for water access and more efficient bubble transfer growth step of direct bond transfer via Van der Waals …
FIG. 19D illustrates a drain solution (while the graphene is aligned to the wafer) to transfer a layer onto a target step of the alternative option for the …
FIG. 20D illustrates a ROIC preparation and ROIC alignment step of direct bond transfer via fusion bonding. SVG …
FIG. 21D illustrates a bonding the graphene layer to the target step of an adhesive temporary bond material process. [00177]
FIG. 22A illustrates an adhesive temporary bond material process. [00181]
FIG. 23C illustrates a tape peel and graphene transfer step of an adhesive temporary bond material process with a nickel deposition layer. SVG …
FIG. 24A is an isolated view of a CMOS wafer step for employment in the fabrication methods herein described. [00188]
FIG. 25E illustrates a bonding a cover material to a ROIC wafer top insulator step of direct bond transfer via fusion bonding. [00198]
FIG. 26A illustrates a graphene on a ROIC wafer step of a CMOS integration method. SVG 16025794.07-02-2018.JJ₄UL₆₁LRXEAPX0.SPEC.43.1.2063.162.2084.197.svg …
FIG. 27 is an illustration of a top plane view of a source and drain electrodes at the bottom of a well. SVG …
FIG. 28 is an illustration of using alternating vertical metal layers to create an interdigitated type of effect to maximize the of ratio channel width to …
FIG. 29 is an illustration of the structure of
FIG. 30 is an illustration of using alternating vertical layers of metal and transistor material to create an interdigitated type of effect to maximize the …
FIG. 31H. This results in the fully formed layer stack depicted in
FIG. 32B. In a subsequent step (not shown in the figures) the formation of the electrode material over or on the patterned channel material will also fill these …
FIG. 33 is an illustration of a well that uses carbon nanotubes to create interdigitated transistors in a vertical direction. [00219] Having briefly described …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming an integrated circuit for use in performing a nucleic acid sequencing reaction, the method comprising: providing a semi-conducting substrate comprising a plurality of extended planar surfaces offset from one another by a first thickness, being defined by a plurality of side members, and having one or more transistor elements positioned between the plurality of surfaces; depositing a first insulating dielectric layer onto a top of the planar surfaces of the substrate, and extending across each planar surface from one side member to another side member; forming a plurality of trenches in the first insulating dielectric layer, each trench offset from the other by a distance, the distance forming a channel region; depositing a first layer of conductive material into each of the trenches to form a plurality of electrodes therein, a first electrode serving as a source electrode, and a second electrode serving as a drain electrode, the source and drain electrodes in contact with the one or more transistor elements; conditioning the first insulating dielectric layer in a manner so that a side and top surface of each of the plurality of electrodes extends above a surface of the first insulating dielectric layer; and depositing a 2D material layer onto the side and top surface of each of the plurality of electrodes and across the channel region to thereby form a channel between the electrodes. Original
The method according to claim 1, wherein the 2D material comprises a material selected from the group consisting of: Graphene; Molybdenum disulfide (M o S 2); Phosphorene (black phosphorous); Silicene, Borophene, Tungsten disulfide (WS₂); Boron Nitride; WSe2; Stanene (2D tin); Graphane; Germanane; Nickel H I TP; and Mxenes (Ti₂C, [T iO.5,Nb O. 5], V₂C, Nb₂C, Ti₃C2, Ti₃CN, Nb₄C3,Ta₄C₃). Original
The method according to claim 1, wherein the step of conditioning the first insulating dielectric layer is accomplished by etching. Original
The method according to claim 1, wherein the step of conditioning the first insulating dielectric layer further comprises depositing a second layer of conductive material on each of the plurality of electrodes so that each of the plurality of electrodes extends further above the surface of the insulating dielectric layer. Original
The method according to claim 1, further comprising forming an opening in the 2D material layer proximate each electrode so as to expose the top surface of each electrode. Original
The method according to claim 1, further comprising patterning the 2D material layer. Original
A method of forming an integrated circuit for use in performing a nucleic acid sequencing reaction, the method comprising: providing a semi-conducting substrate comprising a plurality of extended planar surfaces offset from one another by a first thickness, being surrounded by a plurality of side members, and having one or more transistor elements positioned between the plurality of surfaces; providing a first insulating dielectric layer on top of the planar surfaces of the substrate, and extending across each planar surface from one side member to another side member; forming a plurality of trenches in the first insulating dielectric layer, each trench offset from the other by a distance, the distance forming a channel region; depositing a first layer of conductive material into each of the trenches to form a plurality of electrodes therein, a first electrode serving as a source electrode, and a second electrode serving as a drain electrode, the source and drain electrodes in contact with the one or more transistor elements; depositing a 2D material layer onto the side and top surface of each of the plurality of electrodes and across the channel region to thereby form a channel between the electrodes; forming an opening in the 2D material proximate each electrode so as to expose at least the top surface of each electrode; and depositing a second layer of conductive material over each opening of the 2D material layer so that the second layer of conductive material contacts at least the top surface of the electrode, fills the opening, and further extends above the 2D material layer so as to contact a side and top surface of the 2D material layer. Original
The method according to claim 11, further comprising conditioning the first insulating dielectric layer in a manner so that a surface of each of the plurality of electrodes extends above a surface of the first insulating dielectric layer. Original
A method for securing an electrode to a 2D material layer, the method comprising: providing a semi-conducting substrate, the substrate having a planar surface; providing a first insulating dielectric layer onto the top planar surface of the substrate, the first insulating dielectric layer having a top surface; preparing a plurality of electrodes within the first insulating dielectric layer, each of the plurality of electrodes having a dimension even with or projecting above the top surface of the first insulating dielectric surface; depositing a 2D material layer on the plurality of electrodes to form a contact between the electrodes and the 2D material layer; and patterning the 2D material layer to form at least one channel contacting an electrode on each of the ends of the channel. Original
The method according to claim 16, wherein the plurality of electrodes comprise a first electrode serving as a source electrode, and a second electrode serving as a drain electrode. Original
. Canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene FET integrated circuit for nucleic acid sequencing
Materials described outside the worked examples.
semi-conducting substrate
conductive material (electrodes)
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1H is an illustration of a graphene layered substrate of FIG. lA configured as a chemically-sensitive field-effect transistor having a reaction layer …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.05–3 µm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,607,989Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1H is an illustration of a graphene layered substrate of FIG. lA configured as a chemically-sensitive field-effect transistor having a reaction layer …
FIG. 2A is an illustration of a chemically-sensitive field-effect transistor having a graphene layered well structure, such as for a system for analysis of …
FIG. 3B is a block diagram of a circuitry component for a system for analysis of biological or chemical materials. [00111]
FIG. 4A, such as for a system for analysis of biological or chemical materials, utilizing an electric field for positioning of a nano- or micro- bead. [00119] …
FIG. 5 A is an illustration of the substrate of FIG. l A, having a silicon dioxide layer positioned above a graphene layered reaction zone, and utilizing a …
FIG. 6 I is a graph of an I-Vg curve illustrating a check-slope of the I-Vg curve on one or both sides (Gm & proportional to mobility),and use of a solution …
FIG. 7E is a graph of frequency vs. normalized power spectral density for a graphene FET of the present invention. [00134]
FIG. 8A is an illustration of a chemically-sensitive field-effect transistor with a graphene layered well structure and having a permeable membrane associated …
FIG. 9D is an illustration of an optical readout of DNA sequencing using nanomaterials. [00142]
FIG. 10 A is a block diagram of components for a system for analysis of biological or chemical materials. [00143] FIG. lO B is an illustration of an exemplary …
FIG. 11 is an illustration of various planar source and drain electrode designs, including interdigitated designs. [00145]
FIG. 12 is a cross-section of a well opening stopping on an analyte- sensitive layer. [00146]
FIG. 13 is an illustration highlighting a second analyte-sensitive layer coating the walls of a well. [00147]
FIG. 14 is an illustration of using the well walls to create 3D interdigitated electrodes. [00148]
FIG. 15 is an illustration of the well structure of
FIG. 16 is an illustration showing a metal pattern in a deep trench created by photolithography. [00150]
FIG. 17. SVG 16025794.07-02-2018.JJ₄UL₆₁LRXEAPX0.SPEC.40.1.2063.162.2084.197.svg 0.117 0.07 Chemistry Black and white [00158]
FIG. 18A illustrates a graphene with channels or divots for water access and more efficient bubble transfer growth step of direct bond transfer via Van der Waals …
FIG. 19D illustrates a drain solution (while the graphene is aligned to the wafer) to transfer a layer onto a target step of the alternative option for the …
FIG. 20D illustrates a ROIC preparation and ROIC alignment step of direct bond transfer via fusion bonding. SVG …
FIG. 21D illustrates a bonding the graphene layer to the target step of an adhesive temporary bond material process. [00177]
FIG. 22A illustrates an adhesive temporary bond material process. [00181]
FIG. 23C illustrates a tape peel and graphene transfer step of an adhesive temporary bond material process with a nickel deposition layer. SVG …
FIG. 24A is an isolated view of a CMOS wafer step for employment in the fabrication methods herein described. [00188]
FIG. 25E illustrates a bonding a cover material to a ROIC wafer top insulator step of direct bond transfer via fusion bonding. [00198]
FIG. 26A illustrates a graphene on a ROIC wafer step of a CMOS integration method. SVG 16025794.07-02-2018.JJ₄UL₆₁LRXEAPX0.SPEC.43.1.2063.162.2084.197.svg …
FIG. 27 is an illustration of a top plane view of a source and drain electrodes at the bottom of a well. SVG …
FIG. 28 is an illustration of using alternating vertical metal layers to create an interdigitated type of effect to maximize the of ratio channel width to …
FIG. 29 is an illustration of the structure of
FIG. 30 is an illustration of using alternating vertical layers of metal and transistor material to create an interdigitated type of effect to maximize the …
FIG. 31H. This results in the fully formed layer stack depicted in
FIG. 32B. In a subsequent step (not shown in the figures) the formation of the electrode material over or on the patterned channel material will also fill these …
FIG. 33 is an illustration of a well that uses carbon nanotubes to create interdigitated transistors in a vertical direction. [00219] Having briefly described …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming an integrated circuit for use in performing a nucleic acid sequencing reaction, the method comprising: providing a semi-conducting substrate comprising a plurality of extended planar surfaces offset from one another by a first thickness, being defined by a plurality of side members, and having one or more transistor elements positioned between the plurality of surfaces; depositing a first insulating dielectric layer onto a top of the planar surfaces of the substrate, and extending across each planar surface from one side member to another side member; forming a plurality of trenches in the first insulating dielectric layer, each trench offset from the other by a distance, the distance forming a channel region; depositing a first layer of conductive material into each of the trenches to form a plurality of electrodes therein, a first electrode serving as a source electrode, and a second electrode serving as a drain electrode, the source and drain electrodes in contact with the one or more transistor elements; conditioning the first insulating dielectric layer in a manner so that a side and top surface of each of the plurality of electrodes extends above a surface of the first insulating dielectric layer; and depositing a 2D material layer onto the side and top surface of each of the plurality of electrodes and across the channel region to thereby form a channel between the electrodes. Original
The method according to claim 1, wherein the 2D material comprises a material selected from the group consisting of: Graphene; Molybdenum disulfide (M o S 2); Phosphorene (black phosphorous); Silicene, Borophene, Tungsten disulfide (WS₂); Boron Nitride; WSe2; Stanene (2D tin); Graphane; Germanane; Nickel H I TP; and Mxenes (Ti₂C, [T iO.5,Nb O. 5], V₂C, Nb₂C, Ti₃C2, Ti₃CN, Nb₄C3,Ta₄C₃). Original
The method according to claim 1, wherein the step of conditioning the first insulating dielectric layer is accomplished by etching. Original
The method according to claim 1, wherein the step of conditioning the first insulating dielectric layer further comprises depositing a second layer of conductive material on each of the plurality of electrodes so that each of the plurality of electrodes extends further above the surface of the insulating dielectric layer. Original
The method according to claim 1, further comprising forming an opening in the 2D material layer proximate each electrode so as to expose the top surface of each electrode. Original
The method according to claim 1, further comprising patterning the 2D material layer. Original
A method of forming an integrated circuit for use in performing a nucleic acid sequencing reaction, the method comprising: providing a semi-conducting substrate comprising a plurality of extended planar surfaces offset from one another by a first thickness, being surrounded by a plurality of side members, and having one or more transistor elements positioned between the plurality of surfaces; providing a first insulating dielectric layer on top of the planar surfaces of the substrate, and extending across each planar surface from one side member to another side member; forming a plurality of trenches in the first insulating dielectric layer, each trench offset from the other by a distance, the distance forming a channel region; depositing a first layer of conductive material into each of the trenches to form a plurality of electrodes therein, a first electrode serving as a source electrode, and a second electrode serving as a drain electrode, the source and drain electrodes in contact with the one or more transistor elements; depositing a 2D material layer onto the side and top surface of each of the plurality of electrodes and across the channel region to thereby form a channel between the electrodes; forming an opening in the 2D material proximate each electrode so as to expose at least the top surface of each electrode; and depositing a second layer of conductive material over each opening of the 2D material layer so that the second layer of conductive material contacts at least the top surface of the electrode, fills the opening, and further extends above the 2D material layer so as to contact a side and top surface of the 2D material layer. Original
The method according to claim 11, further comprising conditioning the first insulating dielectric layer in a manner so that a surface of each of the plurality of electrodes extends above a surface of the first insulating dielectric layer. Original
A method for securing an electrode to a 2D material layer, the method comprising: providing a semi-conducting substrate, the substrate having a planar surface; providing a first insulating dielectric layer onto the top planar surface of the substrate, the first insulating dielectric layer having a top surface; preparing a plurality of electrodes within the first insulating dielectric layer, each of the plurality of electrodes having a dimension even with or projecting above the top surface of the first insulating dielectric surface; depositing a 2D material layer on the plurality of electrodes to form a contact between the electrodes and the 2D material layer; and patterning the 2D material layer to form at least one channel contacting an electrode on each of the ends of the channel. Original
The method according to claim 16, wherein the plurality of electrodes comprise a first electrode serving as a source electrode, and a second electrode serving as a drain electrode. Original
. Canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene FET integrated circuit for nucleic acid sequencing
Materials described outside the worked examples.
semi-conducting substrate
conductive material (electrodes)
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1H is an illustration of a graphene layered substrate of FIG. lA configured as a chemically-sensitive field-effect transistor having a reaction layer …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.05–3 µm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,607,989Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1H is an illustration of a graphene layered substrate of FIG. lA configured as a chemically-sensitive field-effect transistor having a reaction layer …
FIG. 2A is an illustration of a chemically-sensitive field-effect transistor having a graphene layered well structure, such as for a system for analysis of …
FIG. 3B is a block diagram of a circuitry component for a system for analysis of biological or chemical materials. [00111]
FIG. 4A, such as for a system for analysis of biological or chemical materials, utilizing an electric field for positioning of a nano- or micro- bead. [00119] …
FIG. 5 A is an illustration of the substrate of FIG. l A, having a silicon dioxide layer positioned above a graphene layered reaction zone, and utilizing a …
FIG. 6 I is a graph of an I-Vg curve illustrating a check-slope of the I-Vg curve on one or both sides (Gm & proportional to mobility),and use of a solution …
FIG. 7E is a graph of frequency vs. normalized power spectral density for a graphene FET of the present invention. [00134]
FIG. 8A is an illustration of a chemically-sensitive field-effect transistor with a graphene layered well structure and having a permeable membrane associated …
FIG. 9D is an illustration of an optical readout of DNA sequencing using nanomaterials. [00142]
FIG. 10 A is a block diagram of components for a system for analysis of biological or chemical materials. [00143] FIG. lO B is an illustration of an exemplary …
FIG. 11 is an illustration of various planar source and drain electrode designs, including interdigitated designs. [00145]
FIG. 12 is a cross-section of a well opening stopping on an analyte- sensitive layer. [00146]
FIG. 13 is an illustration highlighting a second analyte-sensitive layer coating the walls of a well. [00147]
FIG. 14 is an illustration of using the well walls to create 3D interdigitated electrodes. [00148]
FIG. 15 is an illustration of the well structure of
FIG. 16 is an illustration showing a metal pattern in a deep trench created by photolithography. [00150]
FIG. 17. SVG 16025794.07-02-2018.JJ₄UL₆₁LRXEAPX0.SPEC.40.1.2063.162.2084.197.svg 0.117 0.07 Chemistry Black and white [00158]
FIG. 18A illustrates a graphene with channels or divots for water access and more efficient bubble transfer growth step of direct bond transfer via Van der Waals …
FIG. 19D illustrates a drain solution (while the graphene is aligned to the wafer) to transfer a layer onto a target step of the alternative option for the …
FIG. 20D illustrates a ROIC preparation and ROIC alignment step of direct bond transfer via fusion bonding. SVG …
FIG. 21D illustrates a bonding the graphene layer to the target step of an adhesive temporary bond material process. [00177]
FIG. 22A illustrates an adhesive temporary bond material process. [00181]
FIG. 23C illustrates a tape peel and graphene transfer step of an adhesive temporary bond material process with a nickel deposition layer. SVG …
FIG. 24A is an isolated view of a CMOS wafer step for employment in the fabrication methods herein described. [00188]
FIG. 25E illustrates a bonding a cover material to a ROIC wafer top insulator step of direct bond transfer via fusion bonding. [00198]
FIG. 26A illustrates a graphene on a ROIC wafer step of a CMOS integration method. SVG 16025794.07-02-2018.JJ₄UL₆₁LRXEAPX0.SPEC.43.1.2063.162.2084.197.svg …
FIG. 27 is an illustration of a top plane view of a source and drain electrodes at the bottom of a well. SVG …
FIG. 28 is an illustration of using alternating vertical metal layers to create an interdigitated type of effect to maximize the of ratio channel width to …
FIG. 29 is an illustration of the structure of
FIG. 30 is an illustration of using alternating vertical layers of metal and transistor material to create an interdigitated type of effect to maximize the …
FIG. 31H. This results in the fully formed layer stack depicted in
FIG. 32B. In a subsequent step (not shown in the figures) the formation of the electrode material over or on the patterned channel material will also fill these …
FIG. 33 is an illustration of a well that uses carbon nanotubes to create interdigitated transistors in a vertical direction. [00219] Having briefly described …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming an integrated circuit for use in performing a nucleic acid sequencing reaction, the method comprising: providing a semi-conducting substrate comprising a plurality of extended planar surfaces offset from one another by a first thickness, being defined by a plurality of side members, and having one or more transistor elements positioned between the plurality of surfaces; depositing a first insulating dielectric layer onto a top of the planar surfaces of the substrate, and extending across each planar surface from one side member to another side member; forming a plurality of trenches in the first insulating dielectric layer, each trench offset from the other by a distance, the distance forming a channel region; depositing a first layer of conductive material into each of the trenches to form a plurality of electrodes therein, a first electrode serving as a source electrode, and a second electrode serving as a drain electrode, the source and drain electrodes in contact with the one or more transistor elements; conditioning the first insulating dielectric layer in a manner so that a side and top surface of each of the plurality of electrodes extends above a surface of the first insulating dielectric layer; and depositing a 2D material layer onto the side and top surface of each of the plurality of electrodes and across the channel region to thereby form a channel between the electrodes. Original
The method according to claim 1, wherein the 2D material comprises a material selected from the group consisting of: Graphene; Molybdenum disulfide (M o S 2); Phosphorene (black phosphorous); Silicene, Borophene, Tungsten disulfide (WS₂); Boron Nitride; WSe2; Stanene (2D tin); Graphane; Germanane; Nickel H I TP; and Mxenes (Ti₂C, [T iO.5,Nb O. 5], V₂C, Nb₂C, Ti₃C2, Ti₃CN, Nb₄C3,Ta₄C₃). Original
The method according to claim 1, wherein the step of conditioning the first insulating dielectric layer is accomplished by etching. Original
The method according to claim 1, wherein the step of conditioning the first insulating dielectric layer further comprises depositing a second layer of conductive material on each of the plurality of electrodes so that each of the plurality of electrodes extends further above the surface of the insulating dielectric layer. Original
The method according to claim 1, further comprising forming an opening in the 2D material layer proximate each electrode so as to expose the top surface of each electrode. Original
The method according to claim 1, further comprising patterning the 2D material layer. Original
A method of forming an integrated circuit for use in performing a nucleic acid sequencing reaction, the method comprising: providing a semi-conducting substrate comprising a plurality of extended planar surfaces offset from one another by a first thickness, being surrounded by a plurality of side members, and having one or more transistor elements positioned between the plurality of surfaces; providing a first insulating dielectric layer on top of the planar surfaces of the substrate, and extending across each planar surface from one side member to another side member; forming a plurality of trenches in the first insulating dielectric layer, each trench offset from the other by a distance, the distance forming a channel region; depositing a first layer of conductive material into each of the trenches to form a plurality of electrodes therein, a first electrode serving as a source electrode, and a second electrode serving as a drain electrode, the source and drain electrodes in contact with the one or more transistor elements; depositing a 2D material layer onto the side and top surface of each of the plurality of electrodes and across the channel region to thereby form a channel between the electrodes; forming an opening in the 2D material proximate each electrode so as to expose at least the top surface of each electrode; and depositing a second layer of conductive material over each opening of the 2D material layer so that the second layer of conductive material contacts at least the top surface of the electrode, fills the opening, and further extends above the 2D material layer so as to contact a side and top surface of the 2D material layer. Original
The method according to claim 11, further comprising conditioning the first insulating dielectric layer in a manner so that a surface of each of the plurality of electrodes extends above a surface of the first insulating dielectric layer. Original
A method for securing an electrode to a 2D material layer, the method comprising: providing a semi-conducting substrate, the substrate having a planar surface; providing a first insulating dielectric layer onto the top planar surface of the substrate, the first insulating dielectric layer having a top surface; preparing a plurality of electrodes within the first insulating dielectric layer, each of the plurality of electrodes having a dimension even with or projecting above the top surface of the first insulating dielectric surface; depositing a 2D material layer on the plurality of electrodes to form a contact between the electrodes and the 2D material layer; and patterning the 2D material layer to form at least one channel contacting an electrode on each of the ends of the channel. Original
The method according to claim 16, wherein the plurality of electrodes comprise a first electrode serving as a source electrode, and a second electrode serving as a drain electrode. Original
. Canceled
Layer stacks claimed or described, ordered top of device to substrate.
graphene FET integrated circuit for nucleic acid sequencing
Materials described outside the worked examples.
semi-conducting substrate
conductive material (electrodes)
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1H is an illustration of a graphene layered substrate of FIG. lA configured as a chemically-sensitive field-effect transistor having a reaction layer …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.05–3 µm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
2D material layer
Graphene
Molybdenum disulfide
MoS₂
Phosphorene (black phosphorous)
Silicene
Borophene
Tungsten disulfide
WS₂
Boron Nitride
BN
WSe₂
Stanene (2D tin)
Graphane
MXenes
second insulating material layer
FIG. 2A is an illustration of a chemically-sensitive field-effect transistor having a graphene layered well structure, such as for a system for analysis of …
FIG. 4A, such as for a system for analysis of biological or chemical materials, utilizing an electric field for positioning of a nano- or micro- bead. [00119] …
FIG. 6 I is a graph of an I-Vg curve illustrating a check-slope of the I-Vg curve on one or both sides (Gm & proportional to mobility),and use of a solution …
FIG. 6 I is a graph of an I-Vg curve illustrating a check-slope of the I-Vg curve on one or both sides (Gm & proportional to mobility),and use of a solution …
FIG. 7E is a graph of frequency vs. normalized power spectral density for a graphene FET of the present invention. [00134]
FIG. 7E is a graph of frequency vs. normalized power spectral density for a graphene FET of the present invention. [00134]
FIG. 8A is an illustration of a chemically-sensitive field-effect transistor with a graphene layered well structure and having a permeable membrane associated …
FIG. 8A is an illustration of a chemically-sensitive field-effect transistor with a graphene layered well structure and having a permeable membrane associated …
FIG. 10 A is a block diagram of components for a system for analysis of biological or chemical materials. [00143] FIG. lO B is an illustration of an exemplary …
FIG. 14 is an illustration of using the well walls to create 3D interdigitated electrodes. [00148]
FIG. 28 is an illustration of using alternating vertical metal layers to create an interdigitated type of effect to maximize the of ratio channel width to …
FIG. 30 is an illustration of using alternating vertical layers of metal and transistor material to create an interdigitated type of effect to maximize the …
FIG. 31H. This results in the fully formed layer stack depicted in
FIG. 32B. In a subsequent step (not shown in the figures) the formation of the electrode material over or on the patterned channel material will also fill these …
FIG. 33 is an illustration of a well that uses carbon nanotubes to create interdigitated transistors in a vertical direction. [00219] Having briefly described …
| 0.5–2 µm |
| — |
Thickness | 0.1–2 µm | — |
Thickness | 0.001–10 µm | — |
Thickness | 0.01–5 µm | — |
Thickness | ≤ 1 µm | — |
Thickness | ≤ 500 nm | — |
Thickness | ≤ 50 nm | — |
Voltage | ≤ 8 V | — |
Voltage | ≤ 6 V | — |
Voltage | ≤ 4 V | — |
Thickness | ≤ 1 mm | — |
Thickness | ≤ 10 nm | — |
Thickness | 0–75 nm | — |
Thickness | 0–25 nm | — |
2D material layer
Graphene
Molybdenum disulfide
MoS₂
Phosphorene (black phosphorous)
Silicene
Borophene
Tungsten disulfide
WS₂
Boron Nitride
BN
WSe₂
Stanene (2D tin)
Graphane
MXenes
second insulating material layer
FIG. 2A is an illustration of a chemically-sensitive field-effect transistor having a graphene layered well structure, such as for a system for analysis of …
FIG. 4A, such as for a system for analysis of biological or chemical materials, utilizing an electric field for positioning of a nano- or micro- bead. [00119] …
FIG. 6 I is a graph of an I-Vg curve illustrating a check-slope of the I-Vg curve on one or both sides (Gm & proportional to mobility),and use of a solution …
FIG. 6 I is a graph of an I-Vg curve illustrating a check-slope of the I-Vg curve on one or both sides (Gm & proportional to mobility),and use of a solution …
FIG. 7E is a graph of frequency vs. normalized power spectral density for a graphene FET of the present invention. [00134]
FIG. 7E is a graph of frequency vs. normalized power spectral density for a graphene FET of the present invention. [00134]
FIG. 8A is an illustration of a chemically-sensitive field-effect transistor with a graphene layered well structure and having a permeable membrane associated …
FIG. 8A is an illustration of a chemically-sensitive field-effect transistor with a graphene layered well structure and having a permeable membrane associated …
FIG. 10 A is a block diagram of components for a system for analysis of biological or chemical materials. [00143] FIG. lO B is an illustration of an exemplary …
FIG. 14 is an illustration of using the well walls to create 3D interdigitated electrodes. [00148]
FIG. 28 is an illustration of using alternating vertical metal layers to create an interdigitated type of effect to maximize the of ratio channel width to …
FIG. 30 is an illustration of using alternating vertical layers of metal and transistor material to create an interdigitated type of effect to maximize the …
FIG. 31H. This results in the fully formed layer stack depicted in
FIG. 32B. In a subsequent step (not shown in the figures) the formation of the electrode material over or on the patterned channel material will also fill these …
FIG. 33 is an illustration of a well that uses carbon nanotubes to create interdigitated transistors in a vertical direction. [00219] Having briefly described …
| 0.5–2 µm |
| — |
Thickness | 0.1–2 µm | — |
Thickness | 0.001–10 µm | — |
Thickness | 0.01–5 µm | — |
Thickness | ≤ 1 µm | — |
Thickness | ≤ 500 nm | — |
Thickness | ≤ 50 nm | — |
Voltage | ≤ 8 V | — |
Voltage | ≤ 6 V | — |
Voltage | ≤ 4 V | — |
Thickness | ≤ 1 mm | — |
Thickness | ≤ 10 nm | — |
Thickness | 0–75 nm | — |
Thickness | 0–25 nm | — |
2D material layer
Graphene
Molybdenum disulfide
MoS₂
Phosphorene (black phosphorous)
Silicene
Borophene
Tungsten disulfide
WS₂
Boron Nitride
BN
WSe₂
Stanene (2D tin)
Graphane
MXenes
second insulating material layer
FIG. 2A is an illustration of a chemically-sensitive field-effect transistor having a graphene layered well structure, such as for a system for analysis of …
FIG. 4A, such as for a system for analysis of biological or chemical materials, utilizing an electric field for positioning of a nano- or micro- bead. [00119] …
FIG. 6 I is a graph of an I-Vg curve illustrating a check-slope of the I-Vg curve on one or both sides (Gm & proportional to mobility),and use of a solution …
FIG. 6 I is a graph of an I-Vg curve illustrating a check-slope of the I-Vg curve on one or both sides (Gm & proportional to mobility),and use of a solution …
FIG. 7E is a graph of frequency vs. normalized power spectral density for a graphene FET of the present invention. [00134]
FIG. 7E is a graph of frequency vs. normalized power spectral density for a graphene FET of the present invention. [00134]
FIG. 8A is an illustration of a chemically-sensitive field-effect transistor with a graphene layered well structure and having a permeable membrane associated …
FIG. 8A is an illustration of a chemically-sensitive field-effect transistor with a graphene layered well structure and having a permeable membrane associated …
FIG. 10 A is a block diagram of components for a system for analysis of biological or chemical materials. [00143] FIG. lO B is an illustration of an exemplary …
FIG. 14 is an illustration of using the well walls to create 3D interdigitated electrodes. [00148]
FIG. 28 is an illustration of using alternating vertical metal layers to create an interdigitated type of effect to maximize the of ratio channel width to …
FIG. 30 is an illustration of using alternating vertical layers of metal and transistor material to create an interdigitated type of effect to maximize the …
FIG. 31H. This results in the fully formed layer stack depicted in
FIG. 32B. In a subsequent step (not shown in the figures) the formation of the electrode material over or on the patterned channel material will also fill these …
FIG. 33 is an illustration of a well that uses carbon nanotubes to create interdigitated transistors in a vertical direction. [00219] Having briefly described …
| 0.5–2 µm |
| — |
Thickness | 0.1–2 µm | — |
Thickness | 0.001–10 µm | — |
Thickness | 0.01–5 µm | — |
Thickness | ≤ 1 µm | — |
Thickness | ≤ 500 nm | — |
Thickness | ≤ 50 nm | — |
Voltage | ≤ 8 V | — |
Voltage | ≤ 6 V | — |
Voltage | ≤ 4 V | — |
Thickness | ≤ 1 mm | — |
Thickness | ≤ 10 nm | — |
Thickness | 0–75 nm | — |
Thickness | 0–25 nm | — |
2D material layer
Graphene
Molybdenum disulfide
MoS₂
Phosphorene (black phosphorous)
Silicene
Borophene
Tungsten disulfide
WS₂
Boron Nitride
BN
WSe₂
Stanene (2D tin)
Graphane
MXenes
second insulating material layer
FIG. 2A is an illustration of a chemically-sensitive field-effect transistor having a graphene layered well structure, such as for a system for analysis of …
FIG. 4A, such as for a system for analysis of biological or chemical materials, utilizing an electric field for positioning of a nano- or micro- bead. [00119] …
FIG. 6 I is a graph of an I-Vg curve illustrating a check-slope of the I-Vg curve on one or both sides (Gm & proportional to mobility),and use of a solution …
FIG. 6 I is a graph of an I-Vg curve illustrating a check-slope of the I-Vg curve on one or both sides (Gm & proportional to mobility),and use of a solution …
FIG. 7E is a graph of frequency vs. normalized power spectral density for a graphene FET of the present invention. [00134]
FIG. 7E is a graph of frequency vs. normalized power spectral density for a graphene FET of the present invention. [00134]
FIG. 8A is an illustration of a chemically-sensitive field-effect transistor with a graphene layered well structure and having a permeable membrane associated …
FIG. 8A is an illustration of a chemically-sensitive field-effect transistor with a graphene layered well structure and having a permeable membrane associated …
FIG. 10 A is a block diagram of components for a system for analysis of biological or chemical materials. [00143] FIG. lO B is an illustration of an exemplary …
FIG. 14 is an illustration of using the well walls to create 3D interdigitated electrodes. [00148]
FIG. 28 is an illustration of using alternating vertical metal layers to create an interdigitated type of effect to maximize the of ratio channel width to …
FIG. 30 is an illustration of using alternating vertical layers of metal and transistor material to create an interdigitated type of effect to maximize the …
FIG. 31H. This results in the fully formed layer stack depicted in
FIG. 32B. In a subsequent step (not shown in the figures) the formation of the electrode material over or on the patterned channel material will also fill these …
FIG. 33 is an illustration of a well that uses carbon nanotubes to create interdigitated transistors in a vertical direction. [00219] Having briefly described …
| 0.5–2 µm |
| — |
Thickness | 0.1–2 µm | — |
Thickness | 0.001–10 µm | — |
Thickness | 0.01–5 µm | — |
Thickness | ≤ 1 µm | — |
Thickness | ≤ 500 nm | — |
Thickness | ≤ 50 nm | — |
Voltage | ≤ 8 V | — |
Voltage | ≤ 6 V | — |
Voltage | ≤ 4 V | — |
Thickness | ≤ 1 mm | — |
Thickness | ≤ 10 nm | — |
Thickness | 0–75 nm | — |
Thickness | 0–25 nm | — |