Patent
US 10,593,763GRAPHENE FET WITH GRAPHITIC INTERFACE LAYER AT CONTACTS
LUIGI COLOMBO
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,593,763Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a flow chart that shows steps in an example method 100 for forming a graphene-based FET having a graphitic interface layer at its S and D contacts, …
FIG. 2E shows a cross sectional view after patterning the second metal layer 214 to provide the second metal layer portion 214a providing a source with a …
FIG. 3 is a cross section view of an example graphene or CNT FET (FET) 300 having both a top gate 320 and a back gate 340, according to an example embodiment. …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene field-effect transistor (FET), comprising: a graphene layer having a graphene surface on a substrate; a patterned metal oxide layer covering portions of the graphene layer and having open areas over a graphene surface source contact and a graphene surface drain contact of the graphene layer; a metal layer including a first metal portion providing a source contact over said graphene surface source contact and a second metal portion providing a drain contact over said graphene surface drain contact, wherein said metal layer includes a carbon; a graphitic interface layer between said source contact and said graphene surface source contact and between said drain contact and said graphene surface drain contact, and at least one of a top gate and back gate structure over a channel portion of said graphene layer. Currently amended
The FET of claim 1, wherein said metal oxide layer comprises a metal selected from the group consisting of A l, Ti, Hf, Zr, V, Y, l a, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu. Original
The FET of claim 1, wherein said metal layer comprises Ni, Co, Cu, Ru, or Pd. Original
The FET of claim 1, wherein said substrate comprises silicon. Original
The FET of claim 1, wherein said graphene layer is in a form of carbon nanotube (CNTs). Original
The FET of claim 1, wherein said graphitic interface layer comprises two (2) to thirty (30) layers of graphene. Original
The FET of claim 1, wherein said graphitic interface layer is Bernal stacked. Original
A semiconductor device having a graphene field-effect transistor (FET), the graphene FET comprising: a graphene layer having a graphene surface on a substrate; a metal oxide layer over the graphene layer with an open source contact region and an open drain contact region; a metal layer including a first metal portion providing a source contact over said graphene layer in the source contact region and a second metal portion providing a drain contact over said graphene layer in the drain contact region, wherein said metal is saturated with carbon; a graphitic interface layer between said source contact and said graphene layer and between said drain contact and said graphene layer, and at least one of a top gate and back gate structure over a portion of said graphene layer. Original
The FET of claim 8, wherein said metal oxide layer comprises AI, Ti, Hf, Zr, V, Y, l a, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu. Original
The FET of claim 8, wherein said metal layer comprises Ni, Co, Cu, Ru, or Pd. Original
The FET of claim 8, wherein said substrate comprises silicon. Original
The FET of claim 8, wherein said graphene layer is in a form of carbon nanotube (CNTs). Original
The FET of claim 8, wherein said graphitic interface layer comprises two (2) to thirty (30) layers of graphene. Original
The FET of claim 8, wherein said graphitic interface layer is Bernal stacked. Original
A semiconductor device having a graphene field-effect transistor (FET), the graphene FET comprising: a graphene layer having a graphene surface on a silicon substrate; a metal oxide layer with a first opening in a source contact region and a second opening in a drain contact region; a metal layer including a first metal portion providing a source contact over said graphene layer in the first opening and a second metal portion providing a drain contact over said graphene layer in the second opening, wherein said metal layer includes a carbon concentration of at least 10 1 atoms/cm 3, and wherein said metal layer comprises Ni, C o, Cu, Ru, or Pd; a graphitic interface layer between said source contact and said graphene layer and between said drain contact and said graphene layer, and at least one of a top gate and back gate structure over a portion of said graphene layer. Original
The FET of claim 15, wherein said metal oxide layer comprises A l, Ti, Hf, Zr, V, Y, l a, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu. Original
The FET of claim 15, wherein said graphene layer is in a form of carbon nanotube (CNTs). Original
The FET of claim 15, wherein said graphitic interface layer comprises two (2) to thirty (30) layers of graphene. Original
The FET of claim 15, wherein said graphitic interface layer is Bernal stacked. Original
Layer stacks claimed or described, ordered top of device to substrate.
graphene FET with patterned metal oxide and graphitic interface layer (claim 1)
graphene FET with metal oxide and carbon-saturated metal (claim 8)
Materials described outside the worked examples.
graphene layer
metal oxide layer (low work function metal oxide)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a flow chart that shows steps in an example method 100 for forming a graphene-based FET having a graphitic interface layer at its S and D contacts, …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
typical contact resistivity for graphene (prior art background) | — | graphene layer |
contact resistivity of silicided Ni or Pt contacts to silicon (prior art comparison) | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,593,763Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a flow chart that shows steps in an example method 100 for forming a graphene-based FET having a graphitic interface layer at its S and D contacts, …
FIG. 2E shows a cross sectional view after patterning the second metal layer 214 to provide the second metal layer portion 214a providing a source with a …
FIG. 3 is a cross section view of an example graphene or CNT FET (FET) 300 having both a top gate 320 and a back gate 340, according to an example embodiment. …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene field-effect transistor (FET), comprising: a graphene layer having a graphene surface on a substrate; a patterned metal oxide layer covering portions of the graphene layer and having open areas over a graphene surface source contact and a graphene surface drain contact of the graphene layer; a metal layer including a first metal portion providing a source contact over said graphene surface source contact and a second metal portion providing a drain contact over said graphene surface drain contact, wherein said metal layer includes a carbon; a graphitic interface layer between said source contact and said graphene surface source contact and between said drain contact and said graphene surface drain contact, and at least one of a top gate and back gate structure over a channel portion of said graphene layer. Currently amended
The FET of claim 1, wherein said metal oxide layer comprises a metal selected from the group consisting of A l, Ti, Hf, Zr, V, Y, l a, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu. Original
The FET of claim 1, wherein said metal layer comprises Ni, Co, Cu, Ru, or Pd. Original
The FET of claim 1, wherein said substrate comprises silicon. Original
The FET of claim 1, wherein said graphene layer is in a form of carbon nanotube (CNTs). Original
The FET of claim 1, wherein said graphitic interface layer comprises two (2) to thirty (30) layers of graphene. Original
The FET of claim 1, wherein said graphitic interface layer is Bernal stacked. Original
A semiconductor device having a graphene field-effect transistor (FET), the graphene FET comprising: a graphene layer having a graphene surface on a substrate; a metal oxide layer over the graphene layer with an open source contact region and an open drain contact region; a metal layer including a first metal portion providing a source contact over said graphene layer in the source contact region and a second metal portion providing a drain contact over said graphene layer in the drain contact region, wherein said metal is saturated with carbon; a graphitic interface layer between said source contact and said graphene layer and between said drain contact and said graphene layer, and at least one of a top gate and back gate structure over a portion of said graphene layer. Original
The FET of claim 8, wherein said metal oxide layer comprises AI, Ti, Hf, Zr, V, Y, l a, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu. Original
The FET of claim 8, wherein said metal layer comprises Ni, Co, Cu, Ru, or Pd. Original
The FET of claim 8, wherein said substrate comprises silicon. Original
The FET of claim 8, wherein said graphene layer is in a form of carbon nanotube (CNTs). Original
The FET of claim 8, wherein said graphitic interface layer comprises two (2) to thirty (30) layers of graphene. Original
The FET of claim 8, wherein said graphitic interface layer is Bernal stacked. Original
A semiconductor device having a graphene field-effect transistor (FET), the graphene FET comprising: a graphene layer having a graphene surface on a silicon substrate; a metal oxide layer with a first opening in a source contact region and a second opening in a drain contact region; a metal layer including a first metal portion providing a source contact over said graphene layer in the first opening and a second metal portion providing a drain contact over said graphene layer in the second opening, wherein said metal layer includes a carbon concentration of at least 10 1 atoms/cm 3, and wherein said metal layer comprises Ni, C o, Cu, Ru, or Pd; a graphitic interface layer between said source contact and said graphene layer and between said drain contact and said graphene layer, and at least one of a top gate and back gate structure over a portion of said graphene layer. Original
The FET of claim 15, wherein said metal oxide layer comprises A l, Ti, Hf, Zr, V, Y, l a, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu. Original
The FET of claim 15, wherein said graphene layer is in a form of carbon nanotube (CNTs). Original
The FET of claim 15, wherein said graphitic interface layer comprises two (2) to thirty (30) layers of graphene. Original
The FET of claim 15, wherein said graphitic interface layer is Bernal stacked. Original
Layer stacks claimed or described, ordered top of device to substrate.
graphene FET with patterned metal oxide and graphitic interface layer (claim 1)
graphene FET with metal oxide and carbon-saturated metal (claim 8)
Materials described outside the worked examples.
graphene layer
metal oxide layer (low work function metal oxide)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a flow chart that shows steps in an example method 100 for forming a graphene-based FET having a graphitic interface layer at its S and D contacts, …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
typical contact resistivity for graphene (prior art background) | — | graphene layer |
contact resistivity of silicided Ni or Pt contacts to silicon (prior art comparison) | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,593,763Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a flow chart that shows steps in an example method 100 for forming a graphene-based FET having a graphitic interface layer at its S and D contacts, …
FIG. 2E shows a cross sectional view after patterning the second metal layer 214 to provide the second metal layer portion 214a providing a source with a …
FIG. 3 is a cross section view of an example graphene or CNT FET (FET) 300 having both a top gate 320 and a back gate 340, according to an example embodiment. …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene field-effect transistor (FET), comprising: a graphene layer having a graphene surface on a substrate; a patterned metal oxide layer covering portions of the graphene layer and having open areas over a graphene surface source contact and a graphene surface drain contact of the graphene layer; a metal layer including a first metal portion providing a source contact over said graphene surface source contact and a second metal portion providing a drain contact over said graphene surface drain contact, wherein said metal layer includes a carbon; a graphitic interface layer between said source contact and said graphene surface source contact and between said drain contact and said graphene surface drain contact, and at least one of a top gate and back gate structure over a channel portion of said graphene layer. Currently amended
The FET of claim 1, wherein said metal oxide layer comprises a metal selected from the group consisting of A l, Ti, Hf, Zr, V, Y, l a, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu. Original
The FET of claim 1, wherein said metal layer comprises Ni, Co, Cu, Ru, or Pd. Original
The FET of claim 1, wherein said substrate comprises silicon. Original
The FET of claim 1, wherein said graphene layer is in a form of carbon nanotube (CNTs). Original
The FET of claim 1, wherein said graphitic interface layer comprises two (2) to thirty (30) layers of graphene. Original
The FET of claim 1, wherein said graphitic interface layer is Bernal stacked. Original
A semiconductor device having a graphene field-effect transistor (FET), the graphene FET comprising: a graphene layer having a graphene surface on a substrate; a metal oxide layer over the graphene layer with an open source contact region and an open drain contact region; a metal layer including a first metal portion providing a source contact over said graphene layer in the source contact region and a second metal portion providing a drain contact over said graphene layer in the drain contact region, wherein said metal is saturated with carbon; a graphitic interface layer between said source contact and said graphene layer and between said drain contact and said graphene layer, and at least one of a top gate and back gate structure over a portion of said graphene layer. Original
The FET of claim 8, wherein said metal oxide layer comprises AI, Ti, Hf, Zr, V, Y, l a, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu. Original
The FET of claim 8, wherein said metal layer comprises Ni, Co, Cu, Ru, or Pd. Original
The FET of claim 8, wherein said substrate comprises silicon. Original
The FET of claim 8, wherein said graphene layer is in a form of carbon nanotube (CNTs). Original
The FET of claim 8, wherein said graphitic interface layer comprises two (2) to thirty (30) layers of graphene. Original
The FET of claim 8, wherein said graphitic interface layer is Bernal stacked. Original
A semiconductor device having a graphene field-effect transistor (FET), the graphene FET comprising: a graphene layer having a graphene surface on a silicon substrate; a metal oxide layer with a first opening in a source contact region and a second opening in a drain contact region; a metal layer including a first metal portion providing a source contact over said graphene layer in the first opening and a second metal portion providing a drain contact over said graphene layer in the second opening, wherein said metal layer includes a carbon concentration of at least 10 1 atoms/cm 3, and wherein said metal layer comprises Ni, C o, Cu, Ru, or Pd; a graphitic interface layer between said source contact and said graphene layer and between said drain contact and said graphene layer, and at least one of a top gate and back gate structure over a portion of said graphene layer. Original
The FET of claim 15, wherein said metal oxide layer comprises A l, Ti, Hf, Zr, V, Y, l a, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu. Original
The FET of claim 15, wherein said graphene layer is in a form of carbon nanotube (CNTs). Original
The FET of claim 15, wherein said graphitic interface layer comprises two (2) to thirty (30) layers of graphene. Original
The FET of claim 15, wherein said graphitic interface layer is Bernal stacked. Original
Layer stacks claimed or described, ordered top of device to substrate.
graphene FET with patterned metal oxide and graphitic interface layer (claim 1)
graphene FET with metal oxide and carbon-saturated metal (claim 8)
Materials described outside the worked examples.
graphene layer
metal oxide layer (low work function metal oxide)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a flow chart that shows steps in an example method 100 for forming a graphene-based FET having a graphitic interface layer at its S and D contacts, …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
typical contact resistivity for graphene (prior art background) | — | graphene layer |
contact resistivity of silicided Ni or Pt contacts to silicon (prior art comparison) | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,593,763Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a flow chart that shows steps in an example method 100 for forming a graphene-based FET having a graphitic interface layer at its S and D contacts, …
FIG. 2E shows a cross sectional view after patterning the second metal layer 214 to provide the second metal layer portion 214a providing a source with a …
FIG. 3 is a cross section view of an example graphene or CNT FET (FET) 300 having both a top gate 320 and a back gate 340, according to an example embodiment. …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A graphene field-effect transistor (FET), comprising: a graphene layer having a graphene surface on a substrate; a patterned metal oxide layer covering portions of the graphene layer and having open areas over a graphene surface source contact and a graphene surface drain contact of the graphene layer; a metal layer including a first metal portion providing a source contact over said graphene surface source contact and a second metal portion providing a drain contact over said graphene surface drain contact, wherein said metal layer includes a carbon; a graphitic interface layer between said source contact and said graphene surface source contact and between said drain contact and said graphene surface drain contact, and at least one of a top gate and back gate structure over a channel portion of said graphene layer. Currently amended
The FET of claim 1, wherein said metal oxide layer comprises a metal selected from the group consisting of A l, Ti, Hf, Zr, V, Y, l a, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu. Original
The FET of claim 1, wherein said metal layer comprises Ni, Co, Cu, Ru, or Pd. Original
The FET of claim 1, wherein said substrate comprises silicon. Original
The FET of claim 1, wherein said graphene layer is in a form of carbon nanotube (CNTs). Original
The FET of claim 1, wherein said graphitic interface layer comprises two (2) to thirty (30) layers of graphene. Original
The FET of claim 1, wherein said graphitic interface layer is Bernal stacked. Original
A semiconductor device having a graphene field-effect transistor (FET), the graphene FET comprising: a graphene layer having a graphene surface on a substrate; a metal oxide layer over the graphene layer with an open source contact region and an open drain contact region; a metal layer including a first metal portion providing a source contact over said graphene layer in the source contact region and a second metal portion providing a drain contact over said graphene layer in the drain contact region, wherein said metal is saturated with carbon; a graphitic interface layer between said source contact and said graphene layer and between said drain contact and said graphene layer, and at least one of a top gate and back gate structure over a portion of said graphene layer. Original
The FET of claim 8, wherein said metal oxide layer comprises AI, Ti, Hf, Zr, V, Y, l a, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu. Original
The FET of claim 8, wherein said metal layer comprises Ni, Co, Cu, Ru, or Pd. Original
The FET of claim 8, wherein said substrate comprises silicon. Original
The FET of claim 8, wherein said graphene layer is in a form of carbon nanotube (CNTs). Original
The FET of claim 8, wherein said graphitic interface layer comprises two (2) to thirty (30) layers of graphene. Original
The FET of claim 8, wherein said graphitic interface layer is Bernal stacked. Original
A semiconductor device having a graphene field-effect transistor (FET), the graphene FET comprising: a graphene layer having a graphene surface on a silicon substrate; a metal oxide layer with a first opening in a source contact region and a second opening in a drain contact region; a metal layer including a first metal portion providing a source contact over said graphene layer in the first opening and a second metal portion providing a drain contact over said graphene layer in the second opening, wherein said metal layer includes a carbon concentration of at least 10 1 atoms/cm 3, and wherein said metal layer comprises Ni, C o, Cu, Ru, or Pd; a graphitic interface layer between said source contact and said graphene layer and between said drain contact and said graphene layer, and at least one of a top gate and back gate structure over a portion of said graphene layer. Original
The FET of claim 15, wherein said metal oxide layer comprises A l, Ti, Hf, Zr, V, Y, l a, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Lu. Original
The FET of claim 15, wherein said graphene layer is in a form of carbon nanotube (CNTs). Original
The FET of claim 15, wherein said graphitic interface layer comprises two (2) to thirty (30) layers of graphene. Original
The FET of claim 15, wherein said graphitic interface layer is Bernal stacked. Original
Layer stacks claimed or described, ordered top of device to substrate.
graphene FET with patterned metal oxide and graphitic interface layer (claim 1)
graphene FET with metal oxide and carbon-saturated metal (claim 8)
Materials described outside the worked examples.
graphene layer
metal oxide layer (low work function metal oxide)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 is a flow chart that shows steps in an example method 100 for forming a graphene-based FET having a graphitic interface layer at its S and D contacts, …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
typical contact resistivity for graphene (prior art background) | — | graphene layer |
contact resistivity of silicided Ni or Pt contacts to silicon (prior art comparison) | — |
Related documents with shared materials, methods, properties, or citations.
graphene FET on silicon substrate with Ni/Co/Cu/Ru/Pd contact metal with carbon concentration ≥10²¹ atoms/cm3 (claim 15)
graphene or CNT FET example structure (description, FIG. 2A-2H)
carbon-containing metal contact layer
graphitic interface layer
silicon substrate
Si
carbon nanotube (CNT)
nickel (Ni) contact metal
Ni
first metal layer (low work function metal)
SiO₂ dielectric layer
SiO₂
second metal layer (carbon-saturated)
FIG. 3 is a cross section view of an example graphene or CNT FET (FET) 300 having both a top gate 320 and a back gate 340, according to an example embodiment. …
Thickness | 1.5–3 nm | — |
Pressure | 8–760 Torr | — |
Thickness | 10–200 nm | — |
Temperature | 500–1000 °C | — |
Pressure | 1e-8 Torr | — |
— | ≤ 4.3 eV | — |
Temperature | ≥ 500 °C | — |
Thickness | ≥ 10 cm | — |
Temperature | ≥ 200 °C | — |
Temperature | ≥ 600 °C | — |
graphene FET on silicon substrate with Ni/Co/Cu/Ru/Pd contact metal with carbon concentration ≥10²¹ atoms/cm3 (claim 15)
graphene or CNT FET example structure (description, FIG. 2A-2H)
carbon-containing metal contact layer
graphitic interface layer
silicon substrate
Si
carbon nanotube (CNT)
nickel (Ni) contact metal
Ni
first metal layer (low work function metal)
SiO₂ dielectric layer
SiO₂
second metal layer (carbon-saturated)
FIG. 3 is a cross section view of an example graphene or CNT FET (FET) 300 having both a top gate 320 and a back gate 340, according to an example embodiment. …
Thickness | 1.5–3 nm | — |
Pressure | 8–760 Torr | — |
Thickness | 10–200 nm | — |
Temperature | 500–1000 °C | — |
Pressure | 1e-8 Torr | — |
— | ≤ 4.3 eV | — |
Temperature | ≥ 500 °C | — |
Thickness | ≥ 10 cm | — |
Temperature | ≥ 200 °C | — |
Temperature | ≥ 600 °C | — |
graphene FET on silicon substrate with Ni/Co/Cu/Ru/Pd contact metal with carbon concentration ≥10²¹ atoms/cm3 (claim 15)
graphene or CNT FET example structure (description, FIG. 2A-2H)
carbon-containing metal contact layer
graphitic interface layer
silicon substrate
Si
carbon nanotube (CNT)
nickel (Ni) contact metal
Ni
first metal layer (low work function metal)
SiO₂ dielectric layer
SiO₂
second metal layer (carbon-saturated)
FIG. 3 is a cross section view of an example graphene or CNT FET (FET) 300 having both a top gate 320 and a back gate 340, according to an example embodiment. …
Thickness | 1.5–3 nm | — |
Pressure | 8–760 Torr | — |
Thickness | 10–200 nm | — |
Temperature | 500–1000 °C | — |
Pressure | 1e-8 Torr | — |
— | ≤ 4.3 eV | — |
Temperature | ≥ 500 °C | — |
Thickness | ≥ 10 cm | — |
Temperature | ≥ 200 °C | — |
Temperature | ≥ 600 °C | — |
graphene FET on silicon substrate with Ni/Co/Cu/Ru/Pd contact metal with carbon concentration ≥10²¹ atoms/cm3 (claim 15)
graphene or CNT FET example structure (description, FIG. 2A-2H)
carbon-containing metal contact layer
graphitic interface layer
silicon substrate
Si
carbon nanotube (CNT)
nickel (Ni) contact metal
Ni
first metal layer (low work function metal)
SiO₂ dielectric layer
SiO₂
second metal layer (carbon-saturated)
FIG. 3 is a cross section view of an example graphene or CNT FET (FET) 300 having both a top gate 320 and a back gate 340, according to an example embodiment. …
Thickness | 1.5–3 nm | — |
Pressure | 8–760 Torr | — |
Thickness | 10–200 nm | — |
Temperature | 500–1000 °C | — |
Pressure | 1e-8 Torr | — |
— | ≤ 4.3 eV | — |
Temperature | ≥ 500 °C | — |
Thickness | ≥ 10 cm | — |
Temperature | ≥ 200 °C | — |
Temperature | ≥ 600 °C | — |