Patent
US 8,957,405GRAPHENE FIELD EFFECT TRANSISTOR
James W. Adkisson
US
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Patent
Atlas literature
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US 8,957,405Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-17 show processing steps and structures in accordance with aspects of the invention; and [0012]
FIG. 2, a sacrificial seed material 25 is formed on the upper surfaces of the insulator layer 15 and mandrels 20a and 20b. According to aspects of the …
FIG. 3, the sacrificial seed material 25 is patterned such that the sacrificial seed material 25 does not extend continuously from one mandrel 20a to another …
FIG. 4 shows the formation of graphene 30 on the sacrificial seed material 25 on the mandrels 20a and 20b. In embodiments, the sacrificial seed material 25 …
FIG. 5. The mask 35' is removed after the second doping. For example,
FIG. 6 shows forming a second mask 35' over the second mandrel 20b and its associated graphene 30, leaving the first mandrel 20a and its associated graphene 30 …
FIG. 7, source/drain electrodes 45 are formed on the graphene 30 on the mandrels 20a and 20b. The source/drain electrodes 45 are electrically conductive and …
FIG. 8. As depicted in
FIG. 9 shows a first FET 60a comprising source electrode 45a l, drain electrode 45a2, and gate electrode 55 a on a first side of the mandrel 20a. On the other …
FIG. 10 shows a perspective diagrammatic view of the second FET 60b comprising source electrode 45b 1, drain electrode 45b2, and gate electrode 55b arranged on …
FIG. 11, an insulator layer 70 is formed over the entire structure. The insulator layer 70 may comprise any suitable electrical insulator material, such as, …
FIG. 12, electrical contacts 75 are formed in the insulator layer 70 and contacting the source/drain electrodes 45 and gate electrodes 55. The contacts 75 may …
FIG. 13, vent holes 80 are formed through the insulator layer 70, gate dielectric 50, and graphene 30 to expose a portion of the sacrificial seed material 25. …
FIG. 14 shows the removal of the sacrificial seed material 25. In embodiments, the sacrificial seed material 25 is etched through the vent hole 80 using any …
FIG. 15, the insulator material 90 may be formed in substantially the entire air gap 85 between the graphene 30 and the mandrels 20a and 20b. Forming the …
FIG. 16 shows additional processing of the semiconductor structure, including forming a wiring layer 95, one or more wires/interconnects 100 with optional …
FIG. 17 shows a structure similar to that of
FIG. 18 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
App l. No. 14/076,714 BUR₉₂ 01 10108US₃ CLAIMS Please AMEND claim 7 as follows.
Please CANCEL claim 12 without prejudice or disclaimer.
Layer stacks claimed or described, ordered top of device to substrate.
graphene field effect transistor (FET)
Materials described outside the worked examples.
graphene
C
nickel
Ni
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7, source/drain electrodes 45 are formed on the graphene 30 on the mandrels 20a and 20b. The source/drain electrodes 45 are electrically conductive and …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Mobility | 15000 cm2 V-1 s-1 | C |
Thickness | 10–500 nm |
Related documents with shared materials, methods, properties, or citations.
Radiation Hardened Transistors Based on Graphene and Carbon Nanotubes
METHOD OF INTERCALATING INSULATING LAYER BETWEEN METAL AND GRAPHENE LAYER AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE INTERCALATION METHOD
Patent
Atlas literature
Patent
US 8,957,405Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-17 show processing steps and structures in accordance with aspects of the invention; and [0012]
FIG. 2, a sacrificial seed material 25 is formed on the upper surfaces of the insulator layer 15 and mandrels 20a and 20b. According to aspects of the …
FIG. 3, the sacrificial seed material 25 is patterned such that the sacrificial seed material 25 does not extend continuously from one mandrel 20a to another …
FIG. 4 shows the formation of graphene 30 on the sacrificial seed material 25 on the mandrels 20a and 20b. In embodiments, the sacrificial seed material 25 …
FIG. 5. The mask 35' is removed after the second doping. For example,
FIG. 6 shows forming a second mask 35' over the second mandrel 20b and its associated graphene 30, leaving the first mandrel 20a and its associated graphene 30 …
FIG. 7, source/drain electrodes 45 are formed on the graphene 30 on the mandrels 20a and 20b. The source/drain electrodes 45 are electrically conductive and …
FIG. 8. As depicted in
FIG. 9 shows a first FET 60a comprising source electrode 45a l, drain electrode 45a2, and gate electrode 55 a on a first side of the mandrel 20a. On the other …
FIG. 10 shows a perspective diagrammatic view of the second FET 60b comprising source electrode 45b 1, drain electrode 45b2, and gate electrode 55b arranged on …
FIG. 11, an insulator layer 70 is formed over the entire structure. The insulator layer 70 may comprise any suitable electrical insulator material, such as, …
FIG. 12, electrical contacts 75 are formed in the insulator layer 70 and contacting the source/drain electrodes 45 and gate electrodes 55. The contacts 75 may …
FIG. 13, vent holes 80 are formed through the insulator layer 70, gate dielectric 50, and graphene 30 to expose a portion of the sacrificial seed material 25. …
FIG. 14 shows the removal of the sacrificial seed material 25. In embodiments, the sacrificial seed material 25 is etched through the vent hole 80 using any …
FIG. 15, the insulator material 90 may be formed in substantially the entire air gap 85 between the graphene 30 and the mandrels 20a and 20b. Forming the …
FIG. 16 shows additional processing of the semiconductor structure, including forming a wiring layer 95, one or more wires/interconnects 100 with optional …
FIG. 17 shows a structure similar to that of
FIG. 18 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
App l. No. 14/076,714 BUR₉₂ 01 10108US₃ CLAIMS Please AMEND claim 7 as follows.
Please CANCEL claim 12 without prejudice or disclaimer.
Layer stacks claimed or described, ordered top of device to substrate.
graphene field effect transistor (FET)
Materials described outside the worked examples.
graphene
C
nickel
Ni
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7, source/drain electrodes 45 are formed on the graphene 30 on the mandrels 20a and 20b. The source/drain electrodes 45 are electrically conductive and …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Mobility | 15000 cm2 V-1 s-1 | C |
Thickness | 10–500 nm |
Related documents with shared materials, methods, properties, or citations.
Radiation Hardened Transistors Based on Graphene and Carbon Nanotubes
METHOD OF INTERCALATING INSULATING LAYER BETWEEN METAL AND GRAPHENE LAYER AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE INTERCALATION METHOD
Patent
Atlas literature
Patent
US 8,957,405Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-17 show processing steps and structures in accordance with aspects of the invention; and [0012]
FIG. 2, a sacrificial seed material 25 is formed on the upper surfaces of the insulator layer 15 and mandrels 20a and 20b. According to aspects of the …
FIG. 3, the sacrificial seed material 25 is patterned such that the sacrificial seed material 25 does not extend continuously from one mandrel 20a to another …
FIG. 4 shows the formation of graphene 30 on the sacrificial seed material 25 on the mandrels 20a and 20b. In embodiments, the sacrificial seed material 25 …
FIG. 5. The mask 35' is removed after the second doping. For example,
FIG. 6 shows forming a second mask 35' over the second mandrel 20b and its associated graphene 30, leaving the first mandrel 20a and its associated graphene 30 …
FIG. 7, source/drain electrodes 45 are formed on the graphene 30 on the mandrels 20a and 20b. The source/drain electrodes 45 are electrically conductive and …
FIG. 8. As depicted in
FIG. 9 shows a first FET 60a comprising source electrode 45a l, drain electrode 45a2, and gate electrode 55 a on a first side of the mandrel 20a. On the other …
FIG. 10 shows a perspective diagrammatic view of the second FET 60b comprising source electrode 45b 1, drain electrode 45b2, and gate electrode 55b arranged on …
FIG. 11, an insulator layer 70 is formed over the entire structure. The insulator layer 70 may comprise any suitable electrical insulator material, such as, …
FIG. 12, electrical contacts 75 are formed in the insulator layer 70 and contacting the source/drain electrodes 45 and gate electrodes 55. The contacts 75 may …
FIG. 13, vent holes 80 are formed through the insulator layer 70, gate dielectric 50, and graphene 30 to expose a portion of the sacrificial seed material 25. …
FIG. 14 shows the removal of the sacrificial seed material 25. In embodiments, the sacrificial seed material 25 is etched through the vent hole 80 using any …
FIG. 15, the insulator material 90 may be formed in substantially the entire air gap 85 between the graphene 30 and the mandrels 20a and 20b. Forming the …
FIG. 16 shows additional processing of the semiconductor structure, including forming a wiring layer 95, one or more wires/interconnects 100 with optional …
FIG. 17 shows a structure similar to that of
FIG. 18 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
App l. No. 14/076,714 BUR₉₂ 01 10108US₃ CLAIMS Please AMEND claim 7 as follows.
Please CANCEL claim 12 without prejudice or disclaimer.
Layer stacks claimed or described, ordered top of device to substrate.
graphene field effect transistor (FET)
Materials described outside the worked examples.
graphene
C
nickel
Ni
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7, source/drain electrodes 45 are formed on the graphene 30 on the mandrels 20a and 20b. The source/drain electrodes 45 are electrically conductive and …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Mobility | 15000 cm2 V-1 s-1 | C |
Thickness | 10–500 nm |
Related documents with shared materials, methods, properties, or citations.
Radiation Hardened Transistors Based on Graphene and Carbon Nanotubes
METHOD OF INTERCALATING INSULATING LAYER BETWEEN METAL AND GRAPHENE LAYER AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE INTERCALATION METHOD
Patent
Atlas literature
Patent
US 8,957,405Patent drawings and their descriptions. Click a drawing to enlarge it.
FIGS. 1-17 show processing steps and structures in accordance with aspects of the invention; and [0012]
FIG. 2, a sacrificial seed material 25 is formed on the upper surfaces of the insulator layer 15 and mandrels 20a and 20b. According to aspects of the …
FIG. 3, the sacrificial seed material 25 is patterned such that the sacrificial seed material 25 does not extend continuously from one mandrel 20a to another …
FIG. 4 shows the formation of graphene 30 on the sacrificial seed material 25 on the mandrels 20a and 20b. In embodiments, the sacrificial seed material 25 …
FIG. 5. The mask 35' is removed after the second doping. For example,
FIG. 6 shows forming a second mask 35' over the second mandrel 20b and its associated graphene 30, leaving the first mandrel 20a and its associated graphene 30 …
FIG. 7, source/drain electrodes 45 are formed on the graphene 30 on the mandrels 20a and 20b. The source/drain electrodes 45 are electrically conductive and …
FIG. 8. As depicted in
FIG. 9 shows a first FET 60a comprising source electrode 45a l, drain electrode 45a2, and gate electrode 55 a on a first side of the mandrel 20a. On the other …
FIG. 10 shows a perspective diagrammatic view of the second FET 60b comprising source electrode 45b 1, drain electrode 45b2, and gate electrode 55b arranged on …
FIG. 11, an insulator layer 70 is formed over the entire structure. The insulator layer 70 may comprise any suitable electrical insulator material, such as, …
FIG. 12, electrical contacts 75 are formed in the insulator layer 70 and contacting the source/drain electrodes 45 and gate electrodes 55. The contacts 75 may …
FIG. 13, vent holes 80 are formed through the insulator layer 70, gate dielectric 50, and graphene 30 to expose a portion of the sacrificial seed material 25. …
FIG. 14 shows the removal of the sacrificial seed material 25. In embodiments, the sacrificial seed material 25 is etched through the vent hole 80 using any …
FIG. 15, the insulator material 90 may be formed in substantially the entire air gap 85 between the graphene 30 and the mandrels 20a and 20b. Forming the …
FIG. 16 shows additional processing of the semiconductor structure, including forming a wiring layer 95, one or more wires/interconnects 100 with optional …
FIG. 17 shows a structure similar to that of
FIG. 18 is a flow diagram of a design process used in semiconductor design, manufacture, and/or test.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
App l. No. 14/076,714 BUR₉₂ 01 10108US₃ CLAIMS Please AMEND claim 7 as follows.
Please CANCEL claim 12 without prejudice or disclaimer.
Layer stacks claimed or described, ordered top of device to substrate.
graphene field effect transistor (FET)
Materials described outside the worked examples.
graphene
C
nickel
Ni
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7, source/drain electrodes 45 are formed on the graphene 30 on the mandrels 20a and 20b. The source/drain electrodes 45 are electrically conductive and …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Fet Mobility | 15000 cm2 V-1 s-1 | C |
Thickness | 10–500 nm |
Related documents with shared materials, methods, properties, or citations.
Radiation Hardened Transistors Based on Graphene and Carbon Nanotubes
METHOD OF INTERCALATING INSULATING LAYER BETWEEN METAL AND GRAPHENE LAYER AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE INTERCALATION METHOD
silicon dioxide
SiO₂
silicon nitride
SiN
FIG. 9 shows a first FET 60a comprising source electrode 45a l, drain electrode 45a2, and gate electrode 55 a on a first side of the mandrel 20a. On the other …
FIG. 10 shows a perspective diagrammatic view of the second FET 60b comprising source electrode 45b 1, drain electrode 45b2, and gate electrode 55b arranged on …
FIG. 11, an insulator layer 70 is formed over the entire structure. The insulator layer 70 may comprise any suitable electrical insulator material, such as, …
FIG. 12, electrical contacts 75 are formed in the insulator layer 70 and contacting the source/drain electrodes 45 and gate electrodes 55. The contacts 75 may …
| — |
Temperature | 900–1000 °C | — |
Thickness | 10–20 nm | — |
silicon dioxide
SiO₂
silicon nitride
SiN
FIG. 9 shows a first FET 60a comprising source electrode 45a l, drain electrode 45a2, and gate electrode 55 a on a first side of the mandrel 20a. On the other …
FIG. 10 shows a perspective diagrammatic view of the second FET 60b comprising source electrode 45b 1, drain electrode 45b2, and gate electrode 55b arranged on …
FIG. 11, an insulator layer 70 is formed over the entire structure. The insulator layer 70 may comprise any suitable electrical insulator material, such as, …
FIG. 12, electrical contacts 75 are formed in the insulator layer 70 and contacting the source/drain electrodes 45 and gate electrodes 55. The contacts 75 may …
| — |
Temperature | 900–1000 °C | — |
Thickness | 10–20 nm | — |
silicon dioxide
SiO₂
silicon nitride
SiN
FIG. 9 shows a first FET 60a comprising source electrode 45a l, drain electrode 45a2, and gate electrode 55 a on a first side of the mandrel 20a. On the other …
FIG. 10 shows a perspective diagrammatic view of the second FET 60b comprising source electrode 45b 1, drain electrode 45b2, and gate electrode 55b arranged on …
FIG. 11, an insulator layer 70 is formed over the entire structure. The insulator layer 70 may comprise any suitable electrical insulator material, such as, …
FIG. 12, electrical contacts 75 are formed in the insulator layer 70 and contacting the source/drain electrodes 45 and gate electrodes 55. The contacts 75 may …
| — |
Temperature | 900–1000 °C | — |
Thickness | 10–20 nm | — |
silicon dioxide
SiO₂
silicon nitride
SiN
FIG. 9 shows a first FET 60a comprising source electrode 45a l, drain electrode 45a2, and gate electrode 55 a on a first side of the mandrel 20a. On the other …
FIG. 10 shows a perspective diagrammatic view of the second FET 60b comprising source electrode 45b 1, drain electrode 45b2, and gate electrode 55b arranged on …
FIG. 11, an insulator layer 70 is formed over the entire structure. The insulator layer 70 may comprise any suitable electrical insulator material, such as, …
FIG. 12, electrical contacts 75 are formed in the insulator layer 70 and contacting the source/drain electrodes 45 and gate electrodes 55. The contacts 75 may …
| — |
Temperature | 900–1000 °C | — |
Thickness | 10–20 nm | — |