Patent
US 9,337,026GRAPHENE GROWTH ON A CARBON-CONTAINING SEMICONDUCTOR LAYER
Jack O. Chu
US
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Atlas literature
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US 9,337,026Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a vertical cross-sectional view of a first exemplary semiconductor structure prior to deposition of a semiconductor-carbon alloy layer according to a …
FIG. 2 is a vertical cross-sectional view of the first exemplary semiconductor structure after deposition of a semiconductor-carbon alloy layer according to the …
FIG. 3 is a vertical cross-sectional view of the first exemplary semiconductor structure after conversion of the semiconductor-carbon alloy layer into at least …
FIG. 4 is a vertical cross-sectional view of the first exemplary semiconductor structure after conversion of top portions of the at least one semiconductor …
FIG. 5 is a vertical cross-sectional view of a second exemplary semiconductor structure prior to selective deposition of at least one semiconductor-carbon …
FIG. 6 is a vertical cross-sectional view of the second exemplary semiconductor structure after selective deposition of at least one semiconductor-carbon alloy …
FIG. 7 is a vertical cross-sectional view of the second exemplary semiconductor structure after conversion of the at least one semiconductor-carbon alloy layer …
FIG. 8 is a vertical cross-sectional view of the second exemplary semiconductor structure after conversion of top portions of the at least one semiconductor …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
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A semiconductor structure comprising: a semiconductor substrate comprising a single crystalline silicon-containing semiconductor material; a semiconductor carbide layer abutting said single crystalline silicon-containing semiconductor material and having a thickness less than 10 nm; a dielectric material portion located directly on or directly underneath a top surface of said semiconductor substrate and having a dielectric top surface, wherein a center portion of said dielectric top surface is physically exposed, and wherein said dielectric material portion is one ef-a patterned overlying dielectric material portion located over said top surface of said semiconductor substrate; and an embedded dielectric material portion located between recessed semiconductor surfaces of said semiconductor substrate, wherein an outermost vertical sidewall of said embedded dielectric layer material portion is in direct contact with an outermost vertical sidewall of said semiconductor carbide layer; and a graphene layer consisting of a number of graphene monolayers and abutting said semiconductor carbide layer, wherein said number is equal to or greater than 1 and equal to or less than 4, and wherein said graphene layer has a (0001) crystalline orientation along a surface normal of a top surface of said semiconductor substrate.
The semiconductor structure of Claim 11, wherein said semiconductor carbide layer is one of a silicon carbide layer, a silicon-germanium carbide layer, and a germanium carbide layer.
The semiconductor structure of Claim 11, wherein said semiconductor surface includes a sidewall semiconductor surface that is not parallel to said top surface of said semiconductor substrate.
The semiconductor structure of Claim 11, wherein said semiconductor carbide layer has a single crystalline semiconductor carbide structure that is epitaxially aligned to a single crystalline structure of said single crystalline silicon-containing semiconductor material.
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Layer stacks claimed or described, ordered top of device to substrate.
semiconductor structure with graphene layer on silicon substrate
Materials described outside the worked examples.
single crystalline silicon-containing semiconductor material
semiconductor carbide layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
semiconductor carbide layer thickness | — | semiconductor carbide layer |
number of graphene monolayers in graphene layer | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,337,026Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a vertical cross-sectional view of a first exemplary semiconductor structure prior to deposition of a semiconductor-carbon alloy layer according to a …
FIG. 2 is a vertical cross-sectional view of the first exemplary semiconductor structure after deposition of a semiconductor-carbon alloy layer according to the …
FIG. 3 is a vertical cross-sectional view of the first exemplary semiconductor structure after conversion of the semiconductor-carbon alloy layer into at least …
FIG. 4 is a vertical cross-sectional view of the first exemplary semiconductor structure after conversion of top portions of the at least one semiconductor …
FIG. 5 is a vertical cross-sectional view of a second exemplary semiconductor structure prior to selective deposition of at least one semiconductor-carbon …
FIG. 6 is a vertical cross-sectional view of the second exemplary semiconductor structure after selective deposition of at least one semiconductor-carbon alloy …
FIG. 7 is a vertical cross-sectional view of the second exemplary semiconductor structure after conversion of the at least one semiconductor-carbon alloy layer …
FIG. 8 is a vertical cross-sectional view of the second exemplary semiconductor structure after conversion of top portions of the at least one semiconductor …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
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A semiconductor structure comprising: a semiconductor substrate comprising a single crystalline silicon-containing semiconductor material; a semiconductor carbide layer abutting said single crystalline silicon-containing semiconductor material and having a thickness less than 10 nm; a dielectric material portion located directly on or directly underneath a top surface of said semiconductor substrate and having a dielectric top surface, wherein a center portion of said dielectric top surface is physically exposed, and wherein said dielectric material portion is one ef-a patterned overlying dielectric material portion located over said top surface of said semiconductor substrate; and an embedded dielectric material portion located between recessed semiconductor surfaces of said semiconductor substrate, wherein an outermost vertical sidewall of said embedded dielectric layer material portion is in direct contact with an outermost vertical sidewall of said semiconductor carbide layer; and a graphene layer consisting of a number of graphene monolayers and abutting said semiconductor carbide layer, wherein said number is equal to or greater than 1 and equal to or less than 4, and wherein said graphene layer has a (0001) crystalline orientation along a surface normal of a top surface of said semiconductor substrate.
The semiconductor structure of Claim 11, wherein said semiconductor carbide layer is one of a silicon carbide layer, a silicon-germanium carbide layer, and a germanium carbide layer.
The semiconductor structure of Claim 11, wherein said semiconductor surface includes a sidewall semiconductor surface that is not parallel to said top surface of said semiconductor substrate.
The semiconductor structure of Claim 11, wherein said semiconductor carbide layer has a single crystalline semiconductor carbide structure that is epitaxially aligned to a single crystalline structure of said single crystalline silicon-containing semiconductor material.
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canceled
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Layer stacks claimed or described, ordered top of device to substrate.
semiconductor structure with graphene layer on silicon substrate
Materials described outside the worked examples.
single crystalline silicon-containing semiconductor material
semiconductor carbide layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
semiconductor carbide layer thickness | — | semiconductor carbide layer |
number of graphene monolayers in graphene layer | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,337,026Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a vertical cross-sectional view of a first exemplary semiconductor structure prior to deposition of a semiconductor-carbon alloy layer according to a …
FIG. 2 is a vertical cross-sectional view of the first exemplary semiconductor structure after deposition of a semiconductor-carbon alloy layer according to the …
FIG. 3 is a vertical cross-sectional view of the first exemplary semiconductor structure after conversion of the semiconductor-carbon alloy layer into at least …
FIG. 4 is a vertical cross-sectional view of the first exemplary semiconductor structure after conversion of top portions of the at least one semiconductor …
FIG. 5 is a vertical cross-sectional view of a second exemplary semiconductor structure prior to selective deposition of at least one semiconductor-carbon …
FIG. 6 is a vertical cross-sectional view of the second exemplary semiconductor structure after selective deposition of at least one semiconductor-carbon alloy …
FIG. 7 is a vertical cross-sectional view of the second exemplary semiconductor structure after conversion of the at least one semiconductor-carbon alloy layer …
FIG. 8 is a vertical cross-sectional view of the second exemplary semiconductor structure after conversion of top portions of the at least one semiconductor …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
-10. canceled
canceled
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A semiconductor structure comprising: a semiconductor substrate comprising a single crystalline silicon-containing semiconductor material; a semiconductor carbide layer abutting said single crystalline silicon-containing semiconductor material and having a thickness less than 10 nm; a dielectric material portion located directly on or directly underneath a top surface of said semiconductor substrate and having a dielectric top surface, wherein a center portion of said dielectric top surface is physically exposed, and wherein said dielectric material portion is one ef-a patterned overlying dielectric material portion located over said top surface of said semiconductor substrate; and an embedded dielectric material portion located between recessed semiconductor surfaces of said semiconductor substrate, wherein an outermost vertical sidewall of said embedded dielectric layer material portion is in direct contact with an outermost vertical sidewall of said semiconductor carbide layer; and a graphene layer consisting of a number of graphene monolayers and abutting said semiconductor carbide layer, wherein said number is equal to or greater than 1 and equal to or less than 4, and wherein said graphene layer has a (0001) crystalline orientation along a surface normal of a top surface of said semiconductor substrate.
The semiconductor structure of Claim 11, wherein said semiconductor carbide layer is one of a silicon carbide layer, a silicon-germanium carbide layer, and a germanium carbide layer.
The semiconductor structure of Claim 11, wherein said semiconductor surface includes a sidewall semiconductor surface that is not parallel to said top surface of said semiconductor substrate.
The semiconductor structure of Claim 11, wherein said semiconductor carbide layer has a single crystalline semiconductor carbide structure that is epitaxially aligned to a single crystalline structure of said single crystalline silicon-containing semiconductor material.
-23. 3 I:\GF- IB M\2683\23493A\AMEND\23493A.am4.doc canceled
canceled
canceled
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Layer stacks claimed or described, ordered top of device to substrate.
semiconductor structure with graphene layer on silicon substrate
Materials described outside the worked examples.
single crystalline silicon-containing semiconductor material
semiconductor carbide layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
semiconductor carbide layer thickness | — | semiconductor carbide layer |
number of graphene monolayers in graphene layer | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,337,026Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a vertical cross-sectional view of a first exemplary semiconductor structure prior to deposition of a semiconductor-carbon alloy layer according to a …
FIG. 2 is a vertical cross-sectional view of the first exemplary semiconductor structure after deposition of a semiconductor-carbon alloy layer according to the …
FIG. 3 is a vertical cross-sectional view of the first exemplary semiconductor structure after conversion of the semiconductor-carbon alloy layer into at least …
FIG. 4 is a vertical cross-sectional view of the first exemplary semiconductor structure after conversion of top portions of the at least one semiconductor …
FIG. 5 is a vertical cross-sectional view of a second exemplary semiconductor structure prior to selective deposition of at least one semiconductor-carbon …
FIG. 6 is a vertical cross-sectional view of the second exemplary semiconductor structure after selective deposition of at least one semiconductor-carbon alloy …
FIG. 7 is a vertical cross-sectional view of the second exemplary semiconductor structure after conversion of the at least one semiconductor-carbon alloy layer …
FIG. 8 is a vertical cross-sectional view of the second exemplary semiconductor structure after conversion of top portions of the at least one semiconductor …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
-10. canceled
canceled
canceled
canceled
canceled
canceled
canceled
canceled
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A semiconductor structure comprising: a semiconductor substrate comprising a single crystalline silicon-containing semiconductor material; a semiconductor carbide layer abutting said single crystalline silicon-containing semiconductor material and having a thickness less than 10 nm; a dielectric material portion located directly on or directly underneath a top surface of said semiconductor substrate and having a dielectric top surface, wherein a center portion of said dielectric top surface is physically exposed, and wherein said dielectric material portion is one ef-a patterned overlying dielectric material portion located over said top surface of said semiconductor substrate; and an embedded dielectric material portion located between recessed semiconductor surfaces of said semiconductor substrate, wherein an outermost vertical sidewall of said embedded dielectric layer material portion is in direct contact with an outermost vertical sidewall of said semiconductor carbide layer; and a graphene layer consisting of a number of graphene monolayers and abutting said semiconductor carbide layer, wherein said number is equal to or greater than 1 and equal to or less than 4, and wherein said graphene layer has a (0001) crystalline orientation along a surface normal of a top surface of said semiconductor substrate.
The semiconductor structure of Claim 11, wherein said semiconductor carbide layer is one of a silicon carbide layer, a silicon-germanium carbide layer, and a germanium carbide layer.
The semiconductor structure of Claim 11, wherein said semiconductor surface includes a sidewall semiconductor surface that is not parallel to said top surface of said semiconductor substrate.
The semiconductor structure of Claim 11, wherein said semiconductor carbide layer has a single crystalline semiconductor carbide structure that is epitaxially aligned to a single crystalline structure of said single crystalline silicon-containing semiconductor material.
-23. 3 I:\GF- IB M\2683\23493A\AMEND\23493A.am4.doc canceled
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
semiconductor structure with graphene layer on silicon substrate
Materials described outside the worked examples.
single crystalline silicon-containing semiconductor material
semiconductor carbide layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
semiconductor carbide layer thickness | — | semiconductor carbide layer |
number of graphene monolayers in graphene layer | — |
Related documents with shared materials, methods, properties, or citations.
graphene layer
dielectric material portion
silicon carbide
SiC
silicon-germanium carbide
SiGeC
germanium carbide
GeC
semiconductor-carbon alloy layer
silicon substrate
Si
embedded dielectric material portion
graphene layer crystalline orientation | (0001) along surface normal of substrate top surface | graphene layer |
Thickness | 150–300 mm | — |
Thickness | 200–300 mm | — |
Thickness | 500000–1000000 nm | — |
Temperature | 400–1000 °C | — |
Thickness | 0.5–10 nm | — |
Thickness | 1–3 nm | — |
Thickness | 0.5–5 nm | — |
Temperature | 300–600 °C | — |
Temperature | 400–500 °C | — |
Temperature | 1000–1200 °C | — |
Thickness | ≤ 5 nm | — |
Temperature | ≤ 1200 °C | — |
Thickness | ≤ 10 nm | — |
Temperature | ≥ 1200 °C | — |
Temperature | ≥ 1300 °C | — |
FORMATION OF GRAPHENE WAFERS ON SILICON SUBSTRATES
graphene layer
dielectric material portion
silicon carbide
SiC
silicon-germanium carbide
SiGeC
germanium carbide
GeC
semiconductor-carbon alloy layer
silicon substrate
Si
embedded dielectric material portion
graphene layer crystalline orientation | (0001) along surface normal of substrate top surface | graphene layer |
Thickness | 150–300 mm | — |
Thickness | 200–300 mm | — |
Thickness | 500000–1000000 nm | — |
Temperature | 400–1000 °C | — |
Thickness | 0.5–10 nm | — |
Thickness | 1–3 nm | — |
Thickness | 0.5–5 nm | — |
Temperature | 300–600 °C | — |
Temperature | 400–500 °C | — |
Temperature | 1000–1200 °C | — |
Thickness | ≤ 5 nm | — |
Temperature | ≤ 1200 °C | — |
Thickness | ≤ 10 nm | — |
Temperature | ≥ 1200 °C | — |
Temperature | ≥ 1300 °C | — |
FORMATION OF GRAPHENE WAFERS ON SILICON SUBSTRATES
graphene layer
dielectric material portion
silicon carbide
SiC
silicon-germanium carbide
SiGeC
germanium carbide
GeC
semiconductor-carbon alloy layer
silicon substrate
Si
embedded dielectric material portion
graphene layer crystalline orientation | (0001) along surface normal of substrate top surface | graphene layer |
Thickness | 150–300 mm | — |
Thickness | 200–300 mm | — |
Thickness | 500000–1000000 nm | — |
Temperature | 400–1000 °C | — |
Thickness | 0.5–10 nm | — |
Thickness | 1–3 nm | — |
Thickness | 0.5–5 nm | — |
Temperature | 300–600 °C | — |
Temperature | 400–500 °C | — |
Temperature | 1000–1200 °C | — |
Thickness | ≤ 5 nm | — |
Temperature | ≤ 1200 °C | — |
Thickness | ≤ 10 nm | — |
Temperature | ≥ 1200 °C | — |
Temperature | ≥ 1300 °C | — |
FORMATION OF GRAPHENE WAFERS ON SILICON SUBSTRATES
graphene layer
dielectric material portion
silicon carbide
SiC
silicon-germanium carbide
SiGeC
germanium carbide
GeC
semiconductor-carbon alloy layer
silicon substrate
Si
embedded dielectric material portion
graphene layer crystalline orientation | (0001) along surface normal of substrate top surface | graphene layer |
Thickness | 150–300 mm | — |
Thickness | 200–300 mm | — |
Thickness | 500000–1000000 nm | — |
Temperature | 400–1000 °C | — |
Thickness | 0.5–10 nm | — |
Thickness | 1–3 nm | — |
Thickness | 0.5–5 nm | — |
Temperature | 300–600 °C | — |
Temperature | 400–500 °C | — |
Temperature | 1000–1200 °C | — |
Thickness | ≤ 5 nm | — |
Temperature | ≤ 1200 °C | — |
Thickness | ≤ 10 nm | — |
Temperature | ≥ 1200 °C | — |
Temperature | ≥ 1300 °C | — |
FORMATION OF GRAPHENE WAFERS ON SILICON SUBSTRATES