Patent
US 10,012,899GRAPHENE PELLICLE FOR EXTREME ULTRAVIOLET LITHOGRAPHY
Chih-Chiang Tu
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,012,899Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic diagram of a lithography system that may benefit from various aspects of the present disclosure. [0006]
FIG. 2 is a flowchart illustrating a method of making a pellicle for use in a EUV lithography system, according to various aspects of the present disclosure. …
FIGS. 3A, 3 B, 3C, 3 D, 3E, 3F, 3G, 3H, 3 1, 3J, 3K, and 3L are cross-sectional views of an apparatus during various fabrication stages, according to some …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: depositing a first material layer over a first substrate; depositing a graphene layer over the first material layer; depositing an amorphous silicon layer over the graphene layer; bonding the amorphous silicon layer to a second substrate, thereby forming an as sembly; annealing the assembly, thereby converting the amorphous silicon layer to a silicon oxide layer; removing the first substrate from the assembly; and removing the first material layer from the assembly, thereby exposing the graphene layer.
The method of claim 1, further comprising: attaching the assembly to a carrier with the graphene layer in direct contact with the carrier; and after the attaching of the assembly to the carrier, removing the second substrate from the assembly.
The method of claim 1, wherein each of the first and second substrates comprises silicon, and the first material layer comprises nickel.
The method of claim 1, wherein the removing of the first substrate includes a dry etching process.
The method of claim 1, wherein the removing of the first material layer includes a dry etching process.
The method of claim 1, after the removing of the first material layer, further comprising: TSMC No. P₂₀₁₆₀₆₄₂US01/Attorney Docket No. 24061.3419US01 applying oxygen plasma to a surface of the graphene layer opposite another surface of the graphene layer that interfaces with the silicon oxide layer.
The method of claim 1, wherein the removing of the second substrate includes a dry etching process.
The method of claim 1, wherein the graphene layer has a thickness ranging from 5 to 50 nm, and the amorphous silicon layer has a thickness ranging from 50 to 150 nm.
The method of claim 1, wherein the annealing of the assembly is performed at a temperature in a range from 600 to 1000 degrees Celsius and in an ambient having oxygen.
The method of claim 1, wherein the amorphous silicon layer is bonded to the second substrate by van der Waals force.
A method, comprising: depositing a nickel layer over a first silicon substrate; depositing a graphene layer over the nickel layer; depositing an amorphous silicon layer over the graphene layer; bonding the amorphous silicon layer to a second silicon substrate by van der Waals force, thereby forming an assembly; annealing the assembly in an ambient having oxygen, thereby converting the amorphous silicon layer to a silicon oxide layer; removing the first silicon substrate from the assembly; removing the nickel layer from the assembly; attaching the assembly to a carrier with the graphene layer in direct contact with the carrier; and after the attaching of the assembly to the carrier, removing the second silicon substrate from the assembly.
TSMC No. P₂₀₁₆₀₆₄₂US01/Attorney Docket No. 24061.3419US01
The method of claim 16, wherein the removing of the first substrate and the nickel layer includes a dry etching process, and the removing of the second substrate includes another dry etching process.
The method of claim 16, wherein the depositing of the nickel layer is by sputtering, and the nickel layer has a thickness ranging from 50 to 500 nm.
The method of claim 16, wherein the graphene layer has a thickness ranging from 5 to 50 nm, and the amorphous silicon layer has a thickness ranging from 50 to 150 nm.
The method of claim 16, after the removing comprising: applying oxygen plasma to a surface of the first substrate and the nickel layer, further of the graphene layer. 18
Layer stacks claimed or described, ordered top of device to substrate.
EUV pellicle membrane
Materials described outside the worked examples.
graphene layer
first material layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene layer thickness (claimed range) | 5–50 | graphene layer |
amorphous silicon layer thickness (claimed range) | 50–150 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,012,899Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic diagram of a lithography system that may benefit from various aspects of the present disclosure. [0006]
FIG. 2 is a flowchart illustrating a method of making a pellicle for use in a EUV lithography system, according to various aspects of the present disclosure. …
FIGS. 3A, 3 B, 3C, 3 D, 3E, 3F, 3G, 3H, 3 1, 3J, 3K, and 3L are cross-sectional views of an apparatus during various fabrication stages, according to some …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: depositing a first material layer over a first substrate; depositing a graphene layer over the first material layer; depositing an amorphous silicon layer over the graphene layer; bonding the amorphous silicon layer to a second substrate, thereby forming an as sembly; annealing the assembly, thereby converting the amorphous silicon layer to a silicon oxide layer; removing the first substrate from the assembly; and removing the first material layer from the assembly, thereby exposing the graphene layer.
The method of claim 1, further comprising: attaching the assembly to a carrier with the graphene layer in direct contact with the carrier; and after the attaching of the assembly to the carrier, removing the second substrate from the assembly.
The method of claim 1, wherein each of the first and second substrates comprises silicon, and the first material layer comprises nickel.
The method of claim 1, wherein the removing of the first substrate includes a dry etching process.
The method of claim 1, wherein the removing of the first material layer includes a dry etching process.
The method of claim 1, after the removing of the first material layer, further comprising: TSMC No. P₂₀₁₆₀₆₄₂US01/Attorney Docket No. 24061.3419US01 applying oxygen plasma to a surface of the graphene layer opposite another surface of the graphene layer that interfaces with the silicon oxide layer.
The method of claim 1, wherein the removing of the second substrate includes a dry etching process.
The method of claim 1, wherein the graphene layer has a thickness ranging from 5 to 50 nm, and the amorphous silicon layer has a thickness ranging from 50 to 150 nm.
The method of claim 1, wherein the annealing of the assembly is performed at a temperature in a range from 600 to 1000 degrees Celsius and in an ambient having oxygen.
The method of claim 1, wherein the amorphous silicon layer is bonded to the second substrate by van der Waals force.
A method, comprising: depositing a nickel layer over a first silicon substrate; depositing a graphene layer over the nickel layer; depositing an amorphous silicon layer over the graphene layer; bonding the amorphous silicon layer to a second silicon substrate by van der Waals force, thereby forming an assembly; annealing the assembly in an ambient having oxygen, thereby converting the amorphous silicon layer to a silicon oxide layer; removing the first silicon substrate from the assembly; removing the nickel layer from the assembly; attaching the assembly to a carrier with the graphene layer in direct contact with the carrier; and after the attaching of the assembly to the carrier, removing the second silicon substrate from the assembly.
TSMC No. P₂₀₁₆₀₆₄₂US01/Attorney Docket No. 24061.3419US01
The method of claim 16, wherein the removing of the first substrate and the nickel layer includes a dry etching process, and the removing of the second substrate includes another dry etching process.
The method of claim 16, wherein the depositing of the nickel layer is by sputtering, and the nickel layer has a thickness ranging from 50 to 500 nm.
The method of claim 16, wherein the graphene layer has a thickness ranging from 5 to 50 nm, and the amorphous silicon layer has a thickness ranging from 50 to 150 nm.
The method of claim 16, after the removing comprising: applying oxygen plasma to a surface of the first substrate and the nickel layer, further of the graphene layer. 18
Layer stacks claimed or described, ordered top of device to substrate.
EUV pellicle membrane
Materials described outside the worked examples.
graphene layer
first material layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene layer thickness (claimed range) | 5–50 | graphene layer |
amorphous silicon layer thickness (claimed range) | 50–150 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,012,899Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic diagram of a lithography system that may benefit from various aspects of the present disclosure. [0006]
FIG. 2 is a flowchart illustrating a method of making a pellicle for use in a EUV lithography system, according to various aspects of the present disclosure. …
FIGS. 3A, 3 B, 3C, 3 D, 3E, 3F, 3G, 3H, 3 1, 3J, 3K, and 3L are cross-sectional views of an apparatus during various fabrication stages, according to some …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: depositing a first material layer over a first substrate; depositing a graphene layer over the first material layer; depositing an amorphous silicon layer over the graphene layer; bonding the amorphous silicon layer to a second substrate, thereby forming an as sembly; annealing the assembly, thereby converting the amorphous silicon layer to a silicon oxide layer; removing the first substrate from the assembly; and removing the first material layer from the assembly, thereby exposing the graphene layer.
The method of claim 1, further comprising: attaching the assembly to a carrier with the graphene layer in direct contact with the carrier; and after the attaching of the assembly to the carrier, removing the second substrate from the assembly.
The method of claim 1, wherein each of the first and second substrates comprises silicon, and the first material layer comprises nickel.
The method of claim 1, wherein the removing of the first substrate includes a dry etching process.
The method of claim 1, wherein the removing of the first material layer includes a dry etching process.
The method of claim 1, after the removing of the first material layer, further comprising: TSMC No. P₂₀₁₆₀₆₄₂US01/Attorney Docket No. 24061.3419US01 applying oxygen plasma to a surface of the graphene layer opposite another surface of the graphene layer that interfaces with the silicon oxide layer.
The method of claim 1, wherein the removing of the second substrate includes a dry etching process.
The method of claim 1, wherein the graphene layer has a thickness ranging from 5 to 50 nm, and the amorphous silicon layer has a thickness ranging from 50 to 150 nm.
The method of claim 1, wherein the annealing of the assembly is performed at a temperature in a range from 600 to 1000 degrees Celsius and in an ambient having oxygen.
The method of claim 1, wherein the amorphous silicon layer is bonded to the second substrate by van der Waals force.
A method, comprising: depositing a nickel layer over a first silicon substrate; depositing a graphene layer over the nickel layer; depositing an amorphous silicon layer over the graphene layer; bonding the amorphous silicon layer to a second silicon substrate by van der Waals force, thereby forming an assembly; annealing the assembly in an ambient having oxygen, thereby converting the amorphous silicon layer to a silicon oxide layer; removing the first silicon substrate from the assembly; removing the nickel layer from the assembly; attaching the assembly to a carrier with the graphene layer in direct contact with the carrier; and after the attaching of the assembly to the carrier, removing the second silicon substrate from the assembly.
TSMC No. P₂₀₁₆₀₆₄₂US01/Attorney Docket No. 24061.3419US01
The method of claim 16, wherein the removing of the first substrate and the nickel layer includes a dry etching process, and the removing of the second substrate includes another dry etching process.
The method of claim 16, wherein the depositing of the nickel layer is by sputtering, and the nickel layer has a thickness ranging from 50 to 500 nm.
The method of claim 16, wherein the graphene layer has a thickness ranging from 5 to 50 nm, and the amorphous silicon layer has a thickness ranging from 50 to 150 nm.
The method of claim 16, after the removing comprising: applying oxygen plasma to a surface of the first substrate and the nickel layer, further of the graphene layer. 18
Layer stacks claimed or described, ordered top of device to substrate.
EUV pellicle membrane
Materials described outside the worked examples.
graphene layer
first material layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene layer thickness (claimed range) | 5–50 | graphene layer |
amorphous silicon layer thickness (claimed range) | 50–150 |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,012,899Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic diagram of a lithography system that may benefit from various aspects of the present disclosure. [0006]
FIG. 2 is a flowchart illustrating a method of making a pellicle for use in a EUV lithography system, according to various aspects of the present disclosure. …
FIGS. 3A, 3 B, 3C, 3 D, 3E, 3F, 3G, 3H, 3 1, 3J, 3K, and 3L are cross-sectional views of an apparatus during various fabrication stages, according to some …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method, comprising: depositing a first material layer over a first substrate; depositing a graphene layer over the first material layer; depositing an amorphous silicon layer over the graphene layer; bonding the amorphous silicon layer to a second substrate, thereby forming an as sembly; annealing the assembly, thereby converting the amorphous silicon layer to a silicon oxide layer; removing the first substrate from the assembly; and removing the first material layer from the assembly, thereby exposing the graphene layer.
The method of claim 1, further comprising: attaching the assembly to a carrier with the graphene layer in direct contact with the carrier; and after the attaching of the assembly to the carrier, removing the second substrate from the assembly.
The method of claim 1, wherein each of the first and second substrates comprises silicon, and the first material layer comprises nickel.
The method of claim 1, wherein the removing of the first substrate includes a dry etching process.
The method of claim 1, wherein the removing of the first material layer includes a dry etching process.
The method of claim 1, after the removing of the first material layer, further comprising: TSMC No. P₂₀₁₆₀₆₄₂US01/Attorney Docket No. 24061.3419US01 applying oxygen plasma to a surface of the graphene layer opposite another surface of the graphene layer that interfaces with the silicon oxide layer.
The method of claim 1, wherein the removing of the second substrate includes a dry etching process.
The method of claim 1, wherein the graphene layer has a thickness ranging from 5 to 50 nm, and the amorphous silicon layer has a thickness ranging from 50 to 150 nm.
The method of claim 1, wherein the annealing of the assembly is performed at a temperature in a range from 600 to 1000 degrees Celsius and in an ambient having oxygen.
The method of claim 1, wherein the amorphous silicon layer is bonded to the second substrate by van der Waals force.
A method, comprising: depositing a nickel layer over a first silicon substrate; depositing a graphene layer over the nickel layer; depositing an amorphous silicon layer over the graphene layer; bonding the amorphous silicon layer to a second silicon substrate by van der Waals force, thereby forming an assembly; annealing the assembly in an ambient having oxygen, thereby converting the amorphous silicon layer to a silicon oxide layer; removing the first silicon substrate from the assembly; removing the nickel layer from the assembly; attaching the assembly to a carrier with the graphene layer in direct contact with the carrier; and after the attaching of the assembly to the carrier, removing the second silicon substrate from the assembly.
TSMC No. P₂₀₁₆₀₆₄₂US01/Attorney Docket No. 24061.3419US01
The method of claim 16, wherein the removing of the first substrate and the nickel layer includes a dry etching process, and the removing of the second substrate includes another dry etching process.
The method of claim 16, wherein the depositing of the nickel layer is by sputtering, and the nickel layer has a thickness ranging from 50 to 500 nm.
The method of claim 16, wherein the graphene layer has a thickness ranging from 5 to 50 nm, and the amorphous silicon layer has a thickness ranging from 50 to 150 nm.
The method of claim 16, after the removing comprising: applying oxygen plasma to a surface of the first substrate and the nickel layer, further of the graphene layer. 18
Layer stacks claimed or described, ordered top of device to substrate.
EUV pellicle membrane
Materials described outside the worked examples.
graphene layer
first material layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
graphene layer thickness (claimed range) | 5–50 | graphene layer |
amorphous silicon layer thickness (claimed range) | 50–150 |
Related documents with shared materials, methods, properties, or citations.
amorphous silicon layer
a-Si
silicon oxide layer
SiO₂
nickel layer
Ni
silicon substrate
Si
nickel layer thickness (claimed range) | 50–500 | Ni |
annealing temperature for a-Si to SiO2 conversion (claimed range) | 600–1000 | a-Si |
Thickness | 50–500 nm | — |
Thickness | 50–100 nm | — |
Thickness | 5–50 nm | — |
Thickness | 5–10 nm | — |
Pressure | 0.1–10 Torr | — |
Temperature | 560–640 °C | — |
Thickness | 50–150 nm | — |
Temperature | 600–1000 °C | — |
Thickness | 30–50 Å | — |
Thickness | 1–100 nm | — |
amorphous silicon layer
a-Si
silicon oxide layer
SiO₂
nickel layer
Ni
silicon substrate
Si
nickel layer thickness (claimed range) | 50–500 | Ni |
annealing temperature for a-Si to SiO2 conversion (claimed range) | 600–1000 | a-Si |
Thickness | 50–500 nm | — |
Thickness | 50–100 nm | — |
Thickness | 5–50 nm | — |
Thickness | 5–10 nm | — |
Pressure | 0.1–10 Torr | — |
Temperature | 560–640 °C | — |
Thickness | 50–150 nm | — |
Temperature | 600–1000 °C | — |
Thickness | 30–50 Å | — |
Thickness | 1–100 nm | — |
amorphous silicon layer
a-Si
silicon oxide layer
SiO₂
nickel layer
Ni
silicon substrate
Si
nickel layer thickness (claimed range) | 50–500 | Ni |
annealing temperature for a-Si to SiO2 conversion (claimed range) | 600–1000 | a-Si |
Thickness | 50–500 nm | — |
Thickness | 50–100 nm | — |
Thickness | 5–50 nm | — |
Thickness | 5–10 nm | — |
Pressure | 0.1–10 Torr | — |
Temperature | 560–640 °C | — |
Thickness | 50–150 nm | — |
Temperature | 600–1000 °C | — |
Thickness | 30–50 Å | — |
Thickness | 1–100 nm | — |
amorphous silicon layer
a-Si
silicon oxide layer
SiO₂
nickel layer
Ni
silicon substrate
Si
nickel layer thickness (claimed range) | 50–500 | Ni |
annealing temperature for a-Si to SiO2 conversion (claimed range) | 600–1000 | a-Si |
Thickness | 50–500 nm | — |
Thickness | 50–100 nm | — |
Thickness | 5–50 nm | — |
Thickness | 5–10 nm | — |
Pressure | 0.1–10 Torr | — |
Temperature | 560–640 °C | — |
Thickness | 50–150 nm | — |
Temperature | 600–1000 °C | — |
Thickness | 30–50 Å | — |
Thickness | 1–100 nm | — |