Patent
US 9,412,654GRAPHENE SACRIFICIAL DEPOSITION LAYER ON BEOL COPPER LINER-SEED FOR MITIGATING QUEUE-TIME ISSUES BETWEEN LINER AND PLATING STEP
Junjing Bao
US
Copyright © 2026 Matter42. All rights reserved.
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Atlas literature
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US 9,412,654Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of an exemplary semiconductor structure after forming a stack of material layers over a lower level interconnect structure in …
FIG. 2 after forming a second diffusion barrier layer on sidewalls and bottom surfaces of the openings and topmost surfaces of the stack. [0008]
FIG. 3 after forming a copper seed layer on the second diffusion barrier layer. [0009]
FIG. 4 after forming a graphene sacrificial layer on the copper seed layer. [0010]
FIG. 5 after subjecting the graphene sacrificial layer to a plasma treatment. [0011]
FIG. 6 after forming a copper-containing layer on the copper seed layer to fill the openings. [0012]
FIG. 7 after planarizing the second diffusion barrier layer, the copper seed layer and the copper-containing layer to provide upper level interconnect …
FIG. 8 after forming a second dielectric cap layer over the upper level interconnect structures and a second dielectric material layer in the stack.
FIG. 9 is a cross-sectional view of the exemplary semiconductor structure of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The method of Claim 1, wherein the graphene sacrificial layer is formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (P EC VD), microwave plasma chemical vapor deposition (MPCVD), or ultraviolet (UV) assisted chemical vapor deposition.
The method of Claim 2, wherein the graphene sacrificial layer is formed at a temperature no greater than 400 C.
The method of Claim 1, wherein the graphene sacrificial layer comprise a monolayer of graphene.
The method of Claim 1, wherein the graphene sacrificial layer comprises multilayers containing 2 to 10 monolayers of graphene.
The method of Claim 1, wherein the graphene sacrificial layer is epitaxial aligned with the copper seed layer.
The method of Claim 1, further comprising forming a diffusion barrier layer on the sidewalls and the bottom surface of the at least one opening prior to the forming the copper seed layer.
The method of Claim 8, wherein the diffusion barrier layer comprises Ta, TaN, W, WN, TiN, Ta/TaN, Ta/TaN/Ta, or TaN/Ta.
The method of Claim 1, wherein copper seed layer comprises copper or a copper alloy.
The method of Claim 1, wherein the copper seed layer is formed by CVD, PECVD, atomic layer deposition (ALD), or physical vapor deposition (PVD).
The method of Claim 1, wherein the plasma treatment comprises exposing the graphene sacrificial layer to a gas comprising hydrogen, nitrogen, or argon.
The method of Claim 1, wherein the plasma treatment introduces disorders and defects in the graphene sacrificial layer.
The method of Claim 1, wherein the copper-containing layer comprises copper or a copper alloy.
The method of Claim 14, wherein the copper alloy comprises copper-aluminum, copper-cobalt, copper-manganese, copper-magnesium, copper-tin, or copper-titanium.
The method of Claim 1, wherein the at least one dielectric material layer is located on a lower interconnect structure, said lower interconnect structure comprising at least one conductive structures embedded in a first dielectric material layer.
The method of Claim 16, wherein the at least one dielectric material layer comprises a first dielectric cap layer present on topmost surfaces of the lower interconnect structure and a second dielectric material layer present on the first dielectric cap layer.
The method of Claim 1, further comprising removing portions of the copper seed layer and the copper-containing layer from a topmost surface of the at least one dielectric material layer.
The method of Claim 19, further comprising forming a second dielectric cap layer on topmost surfaces of remaining portions of the copper seed layer and the copper-containing layer and the at least one dielectric material layer. FI S₉₂₀₁₄₀₂₇₅US₁ Page 14 of
Layer stacks claimed or described, ordered top of device to substrate.
copper interconnect structure
Materials described outside the worked examples.
graphene sacrificial layer
copper seed layer
Cu
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–1000 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,412,654Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of an exemplary semiconductor structure after forming a stack of material layers over a lower level interconnect structure in …
FIG. 2 after forming a second diffusion barrier layer on sidewalls and bottom surfaces of the openings and topmost surfaces of the stack. [0008]
FIG. 3 after forming a copper seed layer on the second diffusion barrier layer. [0009]
FIG. 4 after forming a graphene sacrificial layer on the copper seed layer. [0010]
FIG. 5 after subjecting the graphene sacrificial layer to a plasma treatment. [0011]
FIG. 6 after forming a copper-containing layer on the copper seed layer to fill the openings. [0012]
FIG. 7 after planarizing the second diffusion barrier layer, the copper seed layer and the copper-containing layer to provide upper level interconnect …
FIG. 8 after forming a second dielectric cap layer over the upper level interconnect structures and a second dielectric material layer in the stack.
FIG. 9 is a cross-sectional view of the exemplary semiconductor structure of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The method of Claim 1, wherein the graphene sacrificial layer is formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (P EC VD), microwave plasma chemical vapor deposition (MPCVD), or ultraviolet (UV) assisted chemical vapor deposition.
The method of Claim 2, wherein the graphene sacrificial layer is formed at a temperature no greater than 400 C.
The method of Claim 1, wherein the graphene sacrificial layer comprise a monolayer of graphene.
The method of Claim 1, wherein the graphene sacrificial layer comprises multilayers containing 2 to 10 monolayers of graphene.
The method of Claim 1, wherein the graphene sacrificial layer is epitaxial aligned with the copper seed layer.
The method of Claim 1, further comprising forming a diffusion barrier layer on the sidewalls and the bottom surface of the at least one opening prior to the forming the copper seed layer.
The method of Claim 8, wherein the diffusion barrier layer comprises Ta, TaN, W, WN, TiN, Ta/TaN, Ta/TaN/Ta, or TaN/Ta.
The method of Claim 1, wherein copper seed layer comprises copper or a copper alloy.
The method of Claim 1, wherein the copper seed layer is formed by CVD, PECVD, atomic layer deposition (ALD), or physical vapor deposition (PVD).
The method of Claim 1, wherein the plasma treatment comprises exposing the graphene sacrificial layer to a gas comprising hydrogen, nitrogen, or argon.
The method of Claim 1, wherein the plasma treatment introduces disorders and defects in the graphene sacrificial layer.
The method of Claim 1, wherein the copper-containing layer comprises copper or a copper alloy.
The method of Claim 14, wherein the copper alloy comprises copper-aluminum, copper-cobalt, copper-manganese, copper-magnesium, copper-tin, or copper-titanium.
The method of Claim 1, wherein the at least one dielectric material layer is located on a lower interconnect structure, said lower interconnect structure comprising at least one conductive structures embedded in a first dielectric material layer.
The method of Claim 16, wherein the at least one dielectric material layer comprises a first dielectric cap layer present on topmost surfaces of the lower interconnect structure and a second dielectric material layer present on the first dielectric cap layer.
The method of Claim 1, further comprising removing portions of the copper seed layer and the copper-containing layer from a topmost surface of the at least one dielectric material layer.
The method of Claim 19, further comprising forming a second dielectric cap layer on topmost surfaces of remaining portions of the copper seed layer and the copper-containing layer and the at least one dielectric material layer. FI S₉₂₀₁₄₀₂₇₅US₁ Page 14 of
Layer stacks claimed or described, ordered top of device to substrate.
copper interconnect structure
Materials described outside the worked examples.
graphene sacrificial layer
copper seed layer
Cu
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–1000 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,412,654Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of an exemplary semiconductor structure after forming a stack of material layers over a lower level interconnect structure in …
FIG. 2 after forming a second diffusion barrier layer on sidewalls and bottom surfaces of the openings and topmost surfaces of the stack. [0008]
FIG. 3 after forming a copper seed layer on the second diffusion barrier layer. [0009]
FIG. 4 after forming a graphene sacrificial layer on the copper seed layer. [0010]
FIG. 5 after subjecting the graphene sacrificial layer to a plasma treatment. [0011]
FIG. 6 after forming a copper-containing layer on the copper seed layer to fill the openings. [0012]
FIG. 7 after planarizing the second diffusion barrier layer, the copper seed layer and the copper-containing layer to provide upper level interconnect …
FIG. 8 after forming a second dielectric cap layer over the upper level interconnect structures and a second dielectric material layer in the stack.
FIG. 9 is a cross-sectional view of the exemplary semiconductor structure of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The method of Claim 1, wherein the graphene sacrificial layer is formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (P EC VD), microwave plasma chemical vapor deposition (MPCVD), or ultraviolet (UV) assisted chemical vapor deposition.
The method of Claim 2, wherein the graphene sacrificial layer is formed at a temperature no greater than 400 C.
The method of Claim 1, wherein the graphene sacrificial layer comprise a monolayer of graphene.
The method of Claim 1, wherein the graphene sacrificial layer comprises multilayers containing 2 to 10 monolayers of graphene.
The method of Claim 1, wherein the graphene sacrificial layer is epitaxial aligned with the copper seed layer.
The method of Claim 1, further comprising forming a diffusion barrier layer on the sidewalls and the bottom surface of the at least one opening prior to the forming the copper seed layer.
The method of Claim 8, wherein the diffusion barrier layer comprises Ta, TaN, W, WN, TiN, Ta/TaN, Ta/TaN/Ta, or TaN/Ta.
The method of Claim 1, wherein copper seed layer comprises copper or a copper alloy.
The method of Claim 1, wherein the copper seed layer is formed by CVD, PECVD, atomic layer deposition (ALD), or physical vapor deposition (PVD).
The method of Claim 1, wherein the plasma treatment comprises exposing the graphene sacrificial layer to a gas comprising hydrogen, nitrogen, or argon.
The method of Claim 1, wherein the plasma treatment introduces disorders and defects in the graphene sacrificial layer.
The method of Claim 1, wherein the copper-containing layer comprises copper or a copper alloy.
The method of Claim 14, wherein the copper alloy comprises copper-aluminum, copper-cobalt, copper-manganese, copper-magnesium, copper-tin, or copper-titanium.
The method of Claim 1, wherein the at least one dielectric material layer is located on a lower interconnect structure, said lower interconnect structure comprising at least one conductive structures embedded in a first dielectric material layer.
The method of Claim 16, wherein the at least one dielectric material layer comprises a first dielectric cap layer present on topmost surfaces of the lower interconnect structure and a second dielectric material layer present on the first dielectric cap layer.
The method of Claim 1, further comprising removing portions of the copper seed layer and the copper-containing layer from a topmost surface of the at least one dielectric material layer.
The method of Claim 19, further comprising forming a second dielectric cap layer on topmost surfaces of remaining portions of the copper seed layer and the copper-containing layer and the at least one dielectric material layer. FI S₉₂₀₁₄₀₂₇₅US₁ Page 14 of
Layer stacks claimed or described, ordered top of device to substrate.
copper interconnect structure
Materials described outside the worked examples.
graphene sacrificial layer
copper seed layer
Cu
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–1000 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,412,654Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of an exemplary semiconductor structure after forming a stack of material layers over a lower level interconnect structure in …
FIG. 2 after forming a second diffusion barrier layer on sidewalls and bottom surfaces of the openings and topmost surfaces of the stack. [0008]
FIG. 3 after forming a copper seed layer on the second diffusion barrier layer. [0009]
FIG. 4 after forming a graphene sacrificial layer on the copper seed layer. [0010]
FIG. 5 after subjecting the graphene sacrificial layer to a plasma treatment. [0011]
FIG. 6 after forming a copper-containing layer on the copper seed layer to fill the openings. [0012]
FIG. 7 after planarizing the second diffusion barrier layer, the copper seed layer and the copper-containing layer to provide upper level interconnect …
FIG. 8 after forming a second dielectric cap layer over the upper level interconnect structures and a second dielectric material layer in the stack.
FIG. 9 is a cross-sectional view of the exemplary semiconductor structure of
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
The method of Claim 1, wherein the graphene sacrificial layer is formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (P EC VD), microwave plasma chemical vapor deposition (MPCVD), or ultraviolet (UV) assisted chemical vapor deposition.
The method of Claim 2, wherein the graphene sacrificial layer is formed at a temperature no greater than 400 C.
The method of Claim 1, wherein the graphene sacrificial layer comprise a monolayer of graphene.
The method of Claim 1, wherein the graphene sacrificial layer comprises multilayers containing 2 to 10 monolayers of graphene.
The method of Claim 1, wherein the graphene sacrificial layer is epitaxial aligned with the copper seed layer.
The method of Claim 1, further comprising forming a diffusion barrier layer on the sidewalls and the bottom surface of the at least one opening prior to the forming the copper seed layer.
The method of Claim 8, wherein the diffusion barrier layer comprises Ta, TaN, W, WN, TiN, Ta/TaN, Ta/TaN/Ta, or TaN/Ta.
The method of Claim 1, wherein copper seed layer comprises copper or a copper alloy.
The method of Claim 1, wherein the copper seed layer is formed by CVD, PECVD, atomic layer deposition (ALD), or physical vapor deposition (PVD).
The method of Claim 1, wherein the plasma treatment comprises exposing the graphene sacrificial layer to a gas comprising hydrogen, nitrogen, or argon.
The method of Claim 1, wherein the plasma treatment introduces disorders and defects in the graphene sacrificial layer.
The method of Claim 1, wherein the copper-containing layer comprises copper or a copper alloy.
The method of Claim 14, wherein the copper alloy comprises copper-aluminum, copper-cobalt, copper-manganese, copper-magnesium, copper-tin, or copper-titanium.
The method of Claim 1, wherein the at least one dielectric material layer is located on a lower interconnect structure, said lower interconnect structure comprising at least one conductive structures embedded in a first dielectric material layer.
The method of Claim 16, wherein the at least one dielectric material layer comprises a first dielectric cap layer present on topmost surfaces of the lower interconnect structure and a second dielectric material layer present on the first dielectric cap layer.
The method of Claim 1, further comprising removing portions of the copper seed layer and the copper-containing layer from a topmost surface of the at least one dielectric material layer.
The method of Claim 19, further comprising forming a second dielectric cap layer on topmost surfaces of remaining portions of the copper seed layer and the copper-containing layer and the at least one dielectric material layer. FI S₉₂₀₁₄₀₂₇₅US₁ Page 14 of
Layer stacks claimed or described, ordered top of device to substrate.
copper interconnect structure
Materials described outside the worked examples.
graphene sacrificial layer
copper seed layer
Cu
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 100–1000 nm | — |
Thickness |
Related documents with shared materials, methods, properties, or citations.
copper-containing layer
diffusion barrier layer
first dielectric material layer
first dielectric cap layer
second dielectric material layer
low-k dielectric material
| — |
Thickness | 15–50 nm | — |
Thickness | 1–10 nm | — |
Thickness | 0.5–10 nm | — |
Thickness | 4–40 nm | — |
copper-containing layer
diffusion barrier layer
first dielectric material layer
first dielectric cap layer
second dielectric material layer
low-k dielectric material
| — |
Thickness | 15–50 nm | — |
Thickness | 1–10 nm | — |
Thickness | 0.5–10 nm | — |
Thickness | 4–40 nm | — |
copper-containing layer
diffusion barrier layer
first dielectric material layer
first dielectric cap layer
second dielectric material layer
low-k dielectric material
| — |
Thickness | 15–50 nm | — |
Thickness | 1–10 nm | — |
Thickness | 0.5–10 nm | — |
Thickness | 4–40 nm | — |
copper-containing layer
diffusion barrier layer
first dielectric material layer
first dielectric cap layer
second dielectric material layer
low-k dielectric material
| — |
Thickness | 15–50 nm | — |
Thickness | 1–10 nm | — |
Thickness | 0.5–10 nm | — |
Thickness | 4–40 nm | — |