Patent
US 9,608,103HIGH ELECTRON MOBILITY TRANSISTOR WITH PERIODICALLY CARBON DOPED GALLIUM NITRIDE
Jeffrey Craig Ramer
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,608,103Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a cross-sectional view of a prior art structure for an HEMT device. [0022]
FIG. 2 B shows a cross-sectional view of an HEMT device with alternating layers of undoped gallium nitride and carbon doped gallium nitride, according to …
FIGS. 3A-H shows cross-sectional views of the manufacturing steps for producing an HEMT device with alternating layers of undoped gallium nitride and …
FIG. 4 shows a plot of the carbon concentration of an HEMT device with alternating layers of undoped gallium nitride and carbon doped gallium nitride, …
FIG. 5 shows a plot of the vertical breakdown voltage of a plurality of HEMT devices according to the prior art. [0027]
FIG. 6 shows a plot of the vertical breakdown voltage of a plurality of HEMT devices with alternating layers of undoped gallium nitride and carbon doped …
FIG. 7 shows a plot of the lateral breakdown voltage of a plurality of HEMT devices according to the prior art. [0029]
FIG. 8 shows a plot of the lateral breakdown voltage of a plurality of HEMT devices with alternating layers of undoped gallium nitride and carbon-doped gallium …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a high electron mobility transistor device, the method comprising: providing a substrate; forming a channel layer stack on the substrate having at least four alternating layers of gallium nitride layers and carbon doped gallium nitride layers; and forming a barrier layer on the channel layer stack, wherein the high electron mobility transistor device has a lateral breakdown voltage between 1000V and 1280V or a vertical breakdown voltage between 1000V and 1180V -i capable of operating at a voltage between 1000V and 1160V.
The method according to claim 1, wherein forming the channel layer stack comprises growing each of the gallium nitride layers in first growth conditions such that carbon incorporation in the gallium nitride is suppressed, and growing each of the carbon doped gallium nitride layers in second growth conditions such that carbon incorporation in the gallium nitride is promoted.
The method according to claim 1, wherein forming the channel layer stack comprises forming each of the gallium nitride layers with a carbon concentration less than 1E 18 Atoms/cm 3; and 2 Application No. 14/505,304 Docket No.: 1283810-0022 US Amendment dated Reply to Office Action of forming each of the carbon doped gallium nitride layers having a carbon concentration of greater than 1Ei 8 Atoms/cm 3.
The method according to claim 1, wherein forming the channel layer stack comprises growing each of the gallium nitride layers to a thickness greater than ln m and less than 200nm, and growing each of the carbon doped gallium nitride layers to a thickness greater than lnm and less than 500nm.
The method according to claim 1, wherein forming the channel layer stack comprises growing each one of the gallium nitride layers and each one of the carbon doped gallium nitride layers such that the ratio of the thickness of each of the carbon doped gallium nitride layers to the thickness of each of the gallium nitride layers is greater than 1:3 and less than 3:1.
The method according to claim 1, further comprising: forming a source electrode electrically coupled to the barrier layer; forming a drain electrode electrically coupled to the barrier layer; and forming a gate electrode electrically coupled to the barrier layer between the source and drain electrodes, wherein the source and drain electrodes form an ohmic connection with the barrier layer, and the gate electrode forms a non-ohmic connection with the barrier layer.
The method according to claim 1, wherein the barrier layer comprises aluminum gallium nitride.
The method according to claim 1, further comprising: forming a buffer layer between the substrate and the channel layer stack.
The method of claim 1, wherein an uppermost layer of the channel layer stack is a gallium nitride layer.
The method of claim 1, wherein a lowermost layer of the channel layer stack is a gallium nitride layer.
The method of claim 1, wherein both an uppermost layer and a lowe rm ost layer of the channel layer stack are gallium nitride layers.
The method of claim 1, wherein the high electron mobility transistor device has a lateral breakdown voltage between 1000V and 1280V and a vertical breakdown voltage between 1000V and 11 80V.
A high electron mobility transistor device comprising: a substrate; a channel layer stack on the substrate having at least four alternating layers of gallium nitride layers and carbon doped gallium nitride layers; and a barrier layer on the channel layer stack, wherein the high electron mobility transistor device has a lateral breakdown voltage between 1000V and 1280V or a vertical breakdown voltage between 1000V and 1180V is capable of operating at a voltage between 1000V and 1160V.
The high electron mobility transistor device of claim 15, wherein each of the gallium nitride layers have a carbon concentration less than 1E₁₈ Atoms/cm 3 and each of carbon doped gallium nitride layers have a carbon concentration of greater than 1E 18 Atoms/cm 3
The high electron mobility transistor device of claim 15, wherein each of the gallium nitride layers have a thickness greater than mn m and less than 200nm, and each of the carbon doped gallium nitride layers have a thickness greater than mn m and less than 500 nm.
The high electron mobility transistor device of claim 15, wherein the ratio of the thickness of each of the carbon doped gallium nitride layers to the thickness of each of the gallium nitride layers is greater than 1:3 and less than 3:1.
The high electron mobility transistor device of claim 15, further comprising: a source electrode electrically coupled to the barrier layer; a drain electrode electrically coupled to the barrier layer; and a gate electrode electrically coupled to the barrier layer between the source and drain electrodes, wherein the source and drain electrodes form an ohmic connection with the barrier layer, and the gate electrode forms a non-ohmic connection with the barrier layer.
The high electron mobility transistor device according to claim 15, wherein the barrier layer comprises aluminum gallium nitride.
The high electron mobility transistor device according to claim 15, further comprising: a buffer layer between the substrate and the channel layer stack.
The high electron mobility transistor device of claim 15, wherein an uppermost layer of the channel layer stack is a gallium nitride layer.
The high electron mobility transistor device of claim 15, wherein a lowe rm ost layer of the channel layer stack is a gallium nitride layer.
The high electron mobility transistor device of claim 15, wherein both an uppermost layer and a lowermost layer of the channel layer stack are gallium nitride layers.
The high electron mobility transistor device of claim 15, wherein the high electron mobility transistor device has a lateral breakdown voltage between 1000V and 1280V and a vertical breakdown voltage between 1000V and 1180V. 8
Layer stacks claimed or described, ordered top of device to substrate.
high electron mobility transistor (HEMT)
Materials described outside the worked examples.
gallium nitride
GaN
carbon doped gallium nitride
c-GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Lateral Breakdown Voltage | 1000–1280 V | — |
Vertical Breakdown Voltage | 1000–1180 V | — |
Operating Voltage |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,608,103Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a cross-sectional view of a prior art structure for an HEMT device. [0022]
FIG. 2 B shows a cross-sectional view of an HEMT device with alternating layers of undoped gallium nitride and carbon doped gallium nitride, according to …
FIGS. 3A-H shows cross-sectional views of the manufacturing steps for producing an HEMT device with alternating layers of undoped gallium nitride and …
FIG. 4 shows a plot of the carbon concentration of an HEMT device with alternating layers of undoped gallium nitride and carbon doped gallium nitride, …
FIG. 5 shows a plot of the vertical breakdown voltage of a plurality of HEMT devices according to the prior art. [0027]
FIG. 6 shows a plot of the vertical breakdown voltage of a plurality of HEMT devices with alternating layers of undoped gallium nitride and carbon doped …
FIG. 7 shows a plot of the lateral breakdown voltage of a plurality of HEMT devices according to the prior art. [0029]
FIG. 8 shows a plot of the lateral breakdown voltage of a plurality of HEMT devices with alternating layers of undoped gallium nitride and carbon-doped gallium …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a high electron mobility transistor device, the method comprising: providing a substrate; forming a channel layer stack on the substrate having at least four alternating layers of gallium nitride layers and carbon doped gallium nitride layers; and forming a barrier layer on the channel layer stack, wherein the high electron mobility transistor device has a lateral breakdown voltage between 1000V and 1280V or a vertical breakdown voltage between 1000V and 1180V -i capable of operating at a voltage between 1000V and 1160V.
The method according to claim 1, wherein forming the channel layer stack comprises growing each of the gallium nitride layers in first growth conditions such that carbon incorporation in the gallium nitride is suppressed, and growing each of the carbon doped gallium nitride layers in second growth conditions such that carbon incorporation in the gallium nitride is promoted.
The method according to claim 1, wherein forming the channel layer stack comprises forming each of the gallium nitride layers with a carbon concentration less than 1E 18 Atoms/cm 3; and 2 Application No. 14/505,304 Docket No.: 1283810-0022 US Amendment dated Reply to Office Action of forming each of the carbon doped gallium nitride layers having a carbon concentration of greater than 1Ei 8 Atoms/cm 3.
The method according to claim 1, wherein forming the channel layer stack comprises growing each of the gallium nitride layers to a thickness greater than ln m and less than 200nm, and growing each of the carbon doped gallium nitride layers to a thickness greater than lnm and less than 500nm.
The method according to claim 1, wherein forming the channel layer stack comprises growing each one of the gallium nitride layers and each one of the carbon doped gallium nitride layers such that the ratio of the thickness of each of the carbon doped gallium nitride layers to the thickness of each of the gallium nitride layers is greater than 1:3 and less than 3:1.
The method according to claim 1, further comprising: forming a source electrode electrically coupled to the barrier layer; forming a drain electrode electrically coupled to the barrier layer; and forming a gate electrode electrically coupled to the barrier layer between the source and drain electrodes, wherein the source and drain electrodes form an ohmic connection with the barrier layer, and the gate electrode forms a non-ohmic connection with the barrier layer.
The method according to claim 1, wherein the barrier layer comprises aluminum gallium nitride.
The method according to claim 1, further comprising: forming a buffer layer between the substrate and the channel layer stack.
The method of claim 1, wherein an uppermost layer of the channel layer stack is a gallium nitride layer.
The method of claim 1, wherein a lowermost layer of the channel layer stack is a gallium nitride layer.
The method of claim 1, wherein both an uppermost layer and a lowe rm ost layer of the channel layer stack are gallium nitride layers.
The method of claim 1, wherein the high electron mobility transistor device has a lateral breakdown voltage between 1000V and 1280V and a vertical breakdown voltage between 1000V and 11 80V.
A high electron mobility transistor device comprising: a substrate; a channel layer stack on the substrate having at least four alternating layers of gallium nitride layers and carbon doped gallium nitride layers; and a barrier layer on the channel layer stack, wherein the high electron mobility transistor device has a lateral breakdown voltage between 1000V and 1280V or a vertical breakdown voltage between 1000V and 1180V is capable of operating at a voltage between 1000V and 1160V.
The high electron mobility transistor device of claim 15, wherein each of the gallium nitride layers have a carbon concentration less than 1E₁₈ Atoms/cm 3 and each of carbon doped gallium nitride layers have a carbon concentration of greater than 1E 18 Atoms/cm 3
The high electron mobility transistor device of claim 15, wherein each of the gallium nitride layers have a thickness greater than mn m and less than 200nm, and each of the carbon doped gallium nitride layers have a thickness greater than mn m and less than 500 nm.
The high electron mobility transistor device of claim 15, wherein the ratio of the thickness of each of the carbon doped gallium nitride layers to the thickness of each of the gallium nitride layers is greater than 1:3 and less than 3:1.
The high electron mobility transistor device of claim 15, further comprising: a source electrode electrically coupled to the barrier layer; a drain electrode electrically coupled to the barrier layer; and a gate electrode electrically coupled to the barrier layer between the source and drain electrodes, wherein the source and drain electrodes form an ohmic connection with the barrier layer, and the gate electrode forms a non-ohmic connection with the barrier layer.
The high electron mobility transistor device according to claim 15, wherein the barrier layer comprises aluminum gallium nitride.
The high electron mobility transistor device according to claim 15, further comprising: a buffer layer between the substrate and the channel layer stack.
The high electron mobility transistor device of claim 15, wherein an uppermost layer of the channel layer stack is a gallium nitride layer.
The high electron mobility transistor device of claim 15, wherein a lowe rm ost layer of the channel layer stack is a gallium nitride layer.
The high electron mobility transistor device of claim 15, wherein both an uppermost layer and a lowermost layer of the channel layer stack are gallium nitride layers.
The high electron mobility transistor device of claim 15, wherein the high electron mobility transistor device has a lateral breakdown voltage between 1000V and 1280V and a vertical breakdown voltage between 1000V and 1180V. 8
Layer stacks claimed or described, ordered top of device to substrate.
high electron mobility transistor (HEMT)
Materials described outside the worked examples.
gallium nitride
GaN
carbon doped gallium nitride
c-GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Lateral Breakdown Voltage | 1000–1280 V | — |
Vertical Breakdown Voltage | 1000–1180 V | — |
Operating Voltage |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,608,103Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a cross-sectional view of a prior art structure for an HEMT device. [0022]
FIG. 2 B shows a cross-sectional view of an HEMT device with alternating layers of undoped gallium nitride and carbon doped gallium nitride, according to …
FIGS. 3A-H shows cross-sectional views of the manufacturing steps for producing an HEMT device with alternating layers of undoped gallium nitride and …
FIG. 4 shows a plot of the carbon concentration of an HEMT device with alternating layers of undoped gallium nitride and carbon doped gallium nitride, …
FIG. 5 shows a plot of the vertical breakdown voltage of a plurality of HEMT devices according to the prior art. [0027]
FIG. 6 shows a plot of the vertical breakdown voltage of a plurality of HEMT devices with alternating layers of undoped gallium nitride and carbon doped …
FIG. 7 shows a plot of the lateral breakdown voltage of a plurality of HEMT devices according to the prior art. [0029]
FIG. 8 shows a plot of the lateral breakdown voltage of a plurality of HEMT devices with alternating layers of undoped gallium nitride and carbon-doped gallium …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a high electron mobility transistor device, the method comprising: providing a substrate; forming a channel layer stack on the substrate having at least four alternating layers of gallium nitride layers and carbon doped gallium nitride layers; and forming a barrier layer on the channel layer stack, wherein the high electron mobility transistor device has a lateral breakdown voltage between 1000V and 1280V or a vertical breakdown voltage between 1000V and 1180V -i capable of operating at a voltage between 1000V and 1160V.
The method according to claim 1, wherein forming the channel layer stack comprises growing each of the gallium nitride layers in first growth conditions such that carbon incorporation in the gallium nitride is suppressed, and growing each of the carbon doped gallium nitride layers in second growth conditions such that carbon incorporation in the gallium nitride is promoted.
The method according to claim 1, wherein forming the channel layer stack comprises forming each of the gallium nitride layers with a carbon concentration less than 1E 18 Atoms/cm 3; and 2 Application No. 14/505,304 Docket No.: 1283810-0022 US Amendment dated Reply to Office Action of forming each of the carbon doped gallium nitride layers having a carbon concentration of greater than 1Ei 8 Atoms/cm 3.
The method according to claim 1, wherein forming the channel layer stack comprises growing each of the gallium nitride layers to a thickness greater than ln m and less than 200nm, and growing each of the carbon doped gallium nitride layers to a thickness greater than lnm and less than 500nm.
The method according to claim 1, wherein forming the channel layer stack comprises growing each one of the gallium nitride layers and each one of the carbon doped gallium nitride layers such that the ratio of the thickness of each of the carbon doped gallium nitride layers to the thickness of each of the gallium nitride layers is greater than 1:3 and less than 3:1.
The method according to claim 1, further comprising: forming a source electrode electrically coupled to the barrier layer; forming a drain electrode electrically coupled to the barrier layer; and forming a gate electrode electrically coupled to the barrier layer between the source and drain electrodes, wherein the source and drain electrodes form an ohmic connection with the barrier layer, and the gate electrode forms a non-ohmic connection with the barrier layer.
The method according to claim 1, wherein the barrier layer comprises aluminum gallium nitride.
The method according to claim 1, further comprising: forming a buffer layer between the substrate and the channel layer stack.
The method of claim 1, wherein an uppermost layer of the channel layer stack is a gallium nitride layer.
The method of claim 1, wherein a lowermost layer of the channel layer stack is a gallium nitride layer.
The method of claim 1, wherein both an uppermost layer and a lowe rm ost layer of the channel layer stack are gallium nitride layers.
The method of claim 1, wherein the high electron mobility transistor device has a lateral breakdown voltage between 1000V and 1280V and a vertical breakdown voltage between 1000V and 11 80V.
A high electron mobility transistor device comprising: a substrate; a channel layer stack on the substrate having at least four alternating layers of gallium nitride layers and carbon doped gallium nitride layers; and a barrier layer on the channel layer stack, wherein the high electron mobility transistor device has a lateral breakdown voltage between 1000V and 1280V or a vertical breakdown voltage between 1000V and 1180V is capable of operating at a voltage between 1000V and 1160V.
The high electron mobility transistor device of claim 15, wherein each of the gallium nitride layers have a carbon concentration less than 1E₁₈ Atoms/cm 3 and each of carbon doped gallium nitride layers have a carbon concentration of greater than 1E 18 Atoms/cm 3
The high electron mobility transistor device of claim 15, wherein each of the gallium nitride layers have a thickness greater than mn m and less than 200nm, and each of the carbon doped gallium nitride layers have a thickness greater than mn m and less than 500 nm.
The high electron mobility transistor device of claim 15, wherein the ratio of the thickness of each of the carbon doped gallium nitride layers to the thickness of each of the gallium nitride layers is greater than 1:3 and less than 3:1.
The high electron mobility transistor device of claim 15, further comprising: a source electrode electrically coupled to the barrier layer; a drain electrode electrically coupled to the barrier layer; and a gate electrode electrically coupled to the barrier layer between the source and drain electrodes, wherein the source and drain electrodes form an ohmic connection with the barrier layer, and the gate electrode forms a non-ohmic connection with the barrier layer.
The high electron mobility transistor device according to claim 15, wherein the barrier layer comprises aluminum gallium nitride.
The high electron mobility transistor device according to claim 15, further comprising: a buffer layer between the substrate and the channel layer stack.
The high electron mobility transistor device of claim 15, wherein an uppermost layer of the channel layer stack is a gallium nitride layer.
The high electron mobility transistor device of claim 15, wherein a lowe rm ost layer of the channel layer stack is a gallium nitride layer.
The high electron mobility transistor device of claim 15, wherein both an uppermost layer and a lowermost layer of the channel layer stack are gallium nitride layers.
The high electron mobility transistor device of claim 15, wherein the high electron mobility transistor device has a lateral breakdown voltage between 1000V and 1280V and a vertical breakdown voltage between 1000V and 1180V. 8
Layer stacks claimed or described, ordered top of device to substrate.
high electron mobility transistor (HEMT)
Materials described outside the worked examples.
gallium nitride
GaN
carbon doped gallium nitride
c-GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Lateral Breakdown Voltage | 1000–1280 V | — |
Vertical Breakdown Voltage | 1000–1180 V | — |
Operating Voltage |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,608,103Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a cross-sectional view of a prior art structure for an HEMT device. [0022]
FIG. 2 B shows a cross-sectional view of an HEMT device with alternating layers of undoped gallium nitride and carbon doped gallium nitride, according to …
FIGS. 3A-H shows cross-sectional views of the manufacturing steps for producing an HEMT device with alternating layers of undoped gallium nitride and …
FIG. 4 shows a plot of the carbon concentration of an HEMT device with alternating layers of undoped gallium nitride and carbon doped gallium nitride, …
FIG. 5 shows a plot of the vertical breakdown voltage of a plurality of HEMT devices according to the prior art. [0027]
FIG. 6 shows a plot of the vertical breakdown voltage of a plurality of HEMT devices with alternating layers of undoped gallium nitride and carbon doped …
FIG. 7 shows a plot of the lateral breakdown voltage of a plurality of HEMT devices according to the prior art. [0029]
FIG. 8 shows a plot of the lateral breakdown voltage of a plurality of HEMT devices with alternating layers of undoped gallium nitride and carbon-doped gallium …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of forming a high electron mobility transistor device, the method comprising: providing a substrate; forming a channel layer stack on the substrate having at least four alternating layers of gallium nitride layers and carbon doped gallium nitride layers; and forming a barrier layer on the channel layer stack, wherein the high electron mobility transistor device has a lateral breakdown voltage between 1000V and 1280V or a vertical breakdown voltage between 1000V and 1180V -i capable of operating at a voltage between 1000V and 1160V.
The method according to claim 1, wherein forming the channel layer stack comprises growing each of the gallium nitride layers in first growth conditions such that carbon incorporation in the gallium nitride is suppressed, and growing each of the carbon doped gallium nitride layers in second growth conditions such that carbon incorporation in the gallium nitride is promoted.
The method according to claim 1, wherein forming the channel layer stack comprises forming each of the gallium nitride layers with a carbon concentration less than 1E 18 Atoms/cm 3; and 2 Application No. 14/505,304 Docket No.: 1283810-0022 US Amendment dated Reply to Office Action of forming each of the carbon doped gallium nitride layers having a carbon concentration of greater than 1Ei 8 Atoms/cm 3.
The method according to claim 1, wherein forming the channel layer stack comprises growing each of the gallium nitride layers to a thickness greater than ln m and less than 200nm, and growing each of the carbon doped gallium nitride layers to a thickness greater than lnm and less than 500nm.
The method according to claim 1, wherein forming the channel layer stack comprises growing each one of the gallium nitride layers and each one of the carbon doped gallium nitride layers such that the ratio of the thickness of each of the carbon doped gallium nitride layers to the thickness of each of the gallium nitride layers is greater than 1:3 and less than 3:1.
The method according to claim 1, further comprising: forming a source electrode electrically coupled to the barrier layer; forming a drain electrode electrically coupled to the barrier layer; and forming a gate electrode electrically coupled to the barrier layer between the source and drain electrodes, wherein the source and drain electrodes form an ohmic connection with the barrier layer, and the gate electrode forms a non-ohmic connection with the barrier layer.
The method according to claim 1, wherein the barrier layer comprises aluminum gallium nitride.
The method according to claim 1, further comprising: forming a buffer layer between the substrate and the channel layer stack.
The method of claim 1, wherein an uppermost layer of the channel layer stack is a gallium nitride layer.
The method of claim 1, wherein a lowermost layer of the channel layer stack is a gallium nitride layer.
The method of claim 1, wherein both an uppermost layer and a lowe rm ost layer of the channel layer stack are gallium nitride layers.
The method of claim 1, wherein the high electron mobility transistor device has a lateral breakdown voltage between 1000V and 1280V and a vertical breakdown voltage between 1000V and 11 80V.
A high electron mobility transistor device comprising: a substrate; a channel layer stack on the substrate having at least four alternating layers of gallium nitride layers and carbon doped gallium nitride layers; and a barrier layer on the channel layer stack, wherein the high electron mobility transistor device has a lateral breakdown voltage between 1000V and 1280V or a vertical breakdown voltage between 1000V and 1180V is capable of operating at a voltage between 1000V and 1160V.
The high electron mobility transistor device of claim 15, wherein each of the gallium nitride layers have a carbon concentration less than 1E₁₈ Atoms/cm 3 and each of carbon doped gallium nitride layers have a carbon concentration of greater than 1E 18 Atoms/cm 3
The high electron mobility transistor device of claim 15, wherein each of the gallium nitride layers have a thickness greater than mn m and less than 200nm, and each of the carbon doped gallium nitride layers have a thickness greater than mn m and less than 500 nm.
The high electron mobility transistor device of claim 15, wherein the ratio of the thickness of each of the carbon doped gallium nitride layers to the thickness of each of the gallium nitride layers is greater than 1:3 and less than 3:1.
The high electron mobility transistor device of claim 15, further comprising: a source electrode electrically coupled to the barrier layer; a drain electrode electrically coupled to the barrier layer; and a gate electrode electrically coupled to the barrier layer between the source and drain electrodes, wherein the source and drain electrodes form an ohmic connection with the barrier layer, and the gate electrode forms a non-ohmic connection with the barrier layer.
The high electron mobility transistor device according to claim 15, wherein the barrier layer comprises aluminum gallium nitride.
The high electron mobility transistor device according to claim 15, further comprising: a buffer layer between the substrate and the channel layer stack.
The high electron mobility transistor device of claim 15, wherein an uppermost layer of the channel layer stack is a gallium nitride layer.
The high electron mobility transistor device of claim 15, wherein a lowe rm ost layer of the channel layer stack is a gallium nitride layer.
The high electron mobility transistor device of claim 15, wherein both an uppermost layer and a lowermost layer of the channel layer stack are gallium nitride layers.
The high electron mobility transistor device of claim 15, wherein the high electron mobility transistor device has a lateral breakdown voltage between 1000V and 1280V and a vertical breakdown voltage between 1000V and 1180V. 8
Layer stacks claimed or described, ordered top of device to substrate.
high electron mobility transistor (HEMT)
Materials described outside the worked examples.
gallium nitride
GaN
carbon doped gallium nitride
c-GaN
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Lateral Breakdown Voltage | 1000–1280 V | — |
Vertical Breakdown Voltage | 1000–1180 V | — |
Operating Voltage |
Related documents with shared materials, methods, properties, or citations.
aluminum gallium nitride
AlxGa₁-xN
buffer layer material
| 1000–1160 V |
| — |
Thickness | ≤ 200 nm | — |
Thickness | ≤ 500 nm | — |
Pressure | ≤ 700 Torr | — |
Thickness | ≥ 1 nm | — |
Pressure | ≥ 35 Torr | — |
aluminum gallium nitride
AlxGa₁-xN
buffer layer material
| 1000–1160 V |
| — |
Thickness | ≤ 200 nm | — |
Thickness | ≤ 500 nm | — |
Pressure | ≤ 700 Torr | — |
Thickness | ≥ 1 nm | — |
Pressure | ≥ 35 Torr | — |
aluminum gallium nitride
AlxGa₁-xN
buffer layer material
| 1000–1160 V |
| — |
Thickness | ≤ 200 nm | — |
Thickness | ≤ 500 nm | — |
Pressure | ≤ 700 Torr | — |
Thickness | ≥ 1 nm | — |
Pressure | ≥ 35 Torr | — |
aluminum gallium nitride
AlxGa₁-xN
buffer layer material
| 1000–1160 V |
| — |
Thickness | ≤ 200 nm | — |
Thickness | ≤ 500 nm | — |
Pressure | ≤ 700 Torr | — |
Thickness | ≥ 1 nm | — |
Pressure | ≥ 35 Torr | — |