Patent
US 9,224,596METHODS OF FABRICATING THICK SEMI-INSULATING OR INSULATING EPITAXIAL GALLIUM NITRIDE LAYERS
Adam William Saxler
US
Copyright © 2026 Matter42. All rights reserved.
Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a cross-section of a semiconductor structure incorporating a thick semiinsulating or insulating GaN layer according to some embodiments of the present invention.
Figure 2 is a cross-section of a semiconductor structure inco r porating a thick semiinsulating or insulating GaN layer and a conductive SiC substrate according to further embodiments of the present invention.
Figure 3 is a cross-section of a semiconductor structure incorporating a thick semiinsulating or insulating GaN layer with a conductive buffer layer on a conductive substrate according to f ur ther embodiments of the present invention.
Figure 4 is a cross-section of a semiconductor structure incorporating a thick semiinsulating or insulating GaN layer with a conductive buffer layer on a conductive SiC substrate according to further embodiments of the present invention. 7 Attorney Docket No. 5308-553TSDV
Figure 5 is a cross-section of a semiconductor structure incorporating a via through a thic k semi-insulating or insulating GaN layer on a conductive substrate according to further embodiments of the present invention.
Figure 6 is a cross-section of a semiconductor structure incorporating a via through a thick semi-insulating or insulating GaN layer with a conductive buffer layer on a conductive substrate according to further embodiments of the present invention.
Figure 7 is a cross-section of a semiconductor structure incorporating a via through a thic k semi-insulating or insulating GaN layer to an implanted layer of a conductive substrate according to fu r ther embodiments of the present invention.
Figure 8 is a cross-section of a semiconductor structure incorporating a via through a thic k semi-insulating or insulating GaN layer and a semiconductor substrate according to further embodiments of the present invention.
Figure 9 is a cross-section of a semiconductor structure incorporating a via through a thic k semi-insulating or insulating GaN layer and an etch stop layer according to further embodiments of the p resent invention.
Figure 10 is a cross-section of a semiconductor structure incorporating a thick semiinsulating or insulating GaN layer with a conductive layer according to further embodiments of the present invention.
Figure 11 is a cross-section of a semiconductor structure incorporating a via through a thick semi-insulating or insulating GaN layer on a conductive layer according to further embodiments of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a semiconductor device structure, comprising: epitaxially forming a semi-insulating or insulating GaN epitaxial layer on a conductive semiconductor substrate, the semi-insulating or insulating GaN epitaxial layer having a thickness of at least about 4 p m; and forming a conductive buffer layer disposed between the substrate and the GaN epitaxial layer; providing a backside contact on a surface of the conductive substrate, opposite the insulating or semi-insulating GaN epitaxial layer; and forming a via hole and corresponding via metal in the via hole that extends through the conductive substrate and exposes a portion of the backside contact, wherein forming the via metal comprises forming the via metal that contacts the backside contact at the exposed portion through the conductive substrate.
The method of Claim 1, wherein the GaN epitaxial layer has a thickness of at least about 8 pm.
The method of Claim 1, wherein the GaN epitaxial layer has a thickness of at least about pm.
The method of Claim 1; wherein the GaN epitaxial layer has a resistivity of at least 1 05 £2-cm.
The method of Claim 1, further comprising forming a GaN based semiconductor device on the GaN epitaxial layer. In re: Saxler et al. Serial No.: 13/975,491 Filed: Pag e 3
The method of Claim 1, wherein the GaN epitaxial layer is doped with a deep level transition metal dopant.
The method of Claim 1, wherein the substrate comprises silicon.
. canceled
The method of Claim [[7]] 5, wherein the via hole and via metal extend to the substrate and wherein the via metal provides an ohmic contact to the substrate.
The method of Claim [[7]] 5, further comprising forming a region of higher doping concentration in the substrate beneath the via.
The method of Claim 9, further comprising forming a two dimensional electron gas structure (2DEG) disposed between the substrate and the GaN epitaxial layer.
. canceled
The method of Claim [[7]] 5, wherein the via hole and the via metal extend to the conductive buffer layer and wherein the via metal provides an ohmic contact to the conductive buffer layer.
The method of Claim 11, further comprising forming an etch stop layer disposed between the conductive buffer layer and the GaN epitaxial layer.
The method of Claim 11, wherein forming a conductive buffer layer comprises: forming a first conductive layer of a first conductivity type on the substrate; and forming a second conductive layer of a second conductivity type, opposite the first conductivity type, on the first conductive layer and disposed between the first conductive layer and the GaN epitaxial layer; and wherein the via hole and the via metal extend through the second conductive layer to the first conductive layer. In re: Sax ler et al. Serial No.: 13/975,49 1 Filed: Page 4
A method of fabricating a GaN semiconductor device structure, comprising: epitaxially forming an insulating or semi-insulating GaN epitaxial layer on a semiconductor substrate, the GaN epitaxial layer having a thickness of at least 4 m; and forming a conductive semiconductor layer disposed between the semiconductor substrate and the insulating or semi-insulating GaN epitaxial layer; providing a backside contact on a surface of the semiconductor substrate, opposite the insulating or semi-insulating GaN epitaxial layer; and forming a via hole and corresponding via metal in the via hole that extends through the semiconductor substrate and exposes a portion of the backside contact, wherein forming the via metal comprises forming the via metal that contacts the backside contact at the exposed portion through the semiconductor substrate.
The method of Claim 19, wherein the semiconductor substrate comprises an insulating or semi-insulating semiconductor substrate. In re: Sax ler et al. Serial No.: 13/975,49 1 Filed: Pag e
The method of Claim 19, wherein the substrate comprises silicon carbide and/or sapphire.
The method of Claim 19, wherein the semiconductor substrate comprises an electrically conductive substrate.
The method of Claim 19, wherein the substrate comprises silicon.
A method of fabricating a GaN semiconductor device structure, comprising: epitaxially forming an insulating or semi-insulating GaN epitaxial layer on a conductive SiC substrate, the GaN epitaxial layer having a thickness of at least 4 p m; and forming a conductive buffer layer disposed between the conductive SiC substrate and the GaN epitaxial layer, wherein forming a conductive buffer layer comprises: forming a first conductive layer of a first conductivity type on the substrate; and forming a second conductive layer of a second conductivity type, opposite the first conductivity type, on the first conductive layer and disposed between the first conductive layer and the GaN epitaxial layer.
The method of Claim 26, wherein the GaN epitaxial layer has a resistivity of at least about 1 05 2 -cm.
The method of Claim 26, wherein the GaN based epitaxial layer is doped with a deep level transition metal dopant. In re: Sax ler et al. Serial No.: 13/975,49 1 Filed: Page 6
. canceled
A method of fabricating a GaN semiconductor device structure, comprising: epitaxially forming an insulating or semi-insulating GaN epitaxial layer on a conductive GaN substrate; forming a GaN based semiconductor device on the GaN epitaxial layer; -and forming a via hole and corresponding via metal in the via hole that extends through layers of the GaN based semiconductor device and the GaN epitaxial layer; and providing a backside contact on a surface of the conductive GaN substrate, opposite the insulating or semi-insulating GaN epitaxial layer, wherein forming the via hole further comprises forming the via hole that extends through the conductive substrate and exposes a portion of the backside contact; and wherein forming the via metal comprises forming the via metal that contacts the backside contact at the exposed portion through the conductive substrate.
33-34. canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN semiconductor device structure on conductive semiconductor substrate
GaN semiconductor device structure with conductive semiconductor layer
GaN semiconductor device structure on conductive SiC substrate
GaN semiconductor device structure on conductive GaN substrate
AlGaN/GaN HEMT
Materials described outside the worked examples.
semi-insulating or insulating GaN epitaxial layer
GaN
conductive semiconductor substrate
conductive buffer layer
deep level transition metal dopant (Fe, Co, Mn, Cr, V and/or Ni)
silicon substrate
Si
semiconductor substrate
silicon carbide and/or sapphire substrate
diamond substrate
C
conductive SiC substrate
SiC
AlGaN barrier layer
AlGaN
aluminum nitride buffer layer
AlN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN epitaxial layer resistivity (claimed minimum) | 100000 | GaN |
Thickness | 30–200 nm | — |
Voltage | ≥ 1 V | — |
Voltage | ≥ 50 V | — |
Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a cross-section of a semiconductor structure incorporating a thick semiinsulating or insulating GaN layer according to some embodiments of the present invention.
Figure 2 is a cross-section of a semiconductor structure inco r porating a thick semiinsulating or insulating GaN layer and a conductive SiC substrate according to further embodiments of the present invention.
Figure 3 is a cross-section of a semiconductor structure incorporating a thick semiinsulating or insulating GaN layer with a conductive buffer layer on a conductive substrate according to f ur ther embodiments of the present invention.
Figure 4 is a cross-section of a semiconductor structure incorporating a thick semiinsulating or insulating GaN layer with a conductive buffer layer on a conductive SiC substrate according to further embodiments of the present invention. 7 Attorney Docket No. 5308-553TSDV
Figure 5 is a cross-section of a semiconductor structure incorporating a via through a thic k semi-insulating or insulating GaN layer on a conductive substrate according to further embodiments of the present invention.
Figure 6 is a cross-section of a semiconductor structure incorporating a via through a thick semi-insulating or insulating GaN layer with a conductive buffer layer on a conductive substrate according to further embodiments of the present invention.
Figure 7 is a cross-section of a semiconductor structure incorporating a via through a thic k semi-insulating or insulating GaN layer to an implanted layer of a conductive substrate according to fu r ther embodiments of the present invention.
Figure 8 is a cross-section of a semiconductor structure incorporating a via through a thic k semi-insulating or insulating GaN layer and a semiconductor substrate according to further embodiments of the present invention.
Figure 9 is a cross-section of a semiconductor structure incorporating a via through a thic k semi-insulating or insulating GaN layer and an etch stop layer according to further embodiments of the p resent invention.
Figure 10 is a cross-section of a semiconductor structure incorporating a thick semiinsulating or insulating GaN layer with a conductive layer according to further embodiments of the present invention.
Figure 11 is a cross-section of a semiconductor structure incorporating a via through a thick semi-insulating or insulating GaN layer on a conductive layer according to further embodiments of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a semiconductor device structure, comprising: epitaxially forming a semi-insulating or insulating GaN epitaxial layer on a conductive semiconductor substrate, the semi-insulating or insulating GaN epitaxial layer having a thickness of at least about 4 p m; and forming a conductive buffer layer disposed between the substrate and the GaN epitaxial layer; providing a backside contact on a surface of the conductive substrate, opposite the insulating or semi-insulating GaN epitaxial layer; and forming a via hole and corresponding via metal in the via hole that extends through the conductive substrate and exposes a portion of the backside contact, wherein forming the via metal comprises forming the via metal that contacts the backside contact at the exposed portion through the conductive substrate.
The method of Claim 1, wherein the GaN epitaxial layer has a thickness of at least about 8 pm.
The method of Claim 1, wherein the GaN epitaxial layer has a thickness of at least about pm.
The method of Claim 1; wherein the GaN epitaxial layer has a resistivity of at least 1 05 £2-cm.
The method of Claim 1, further comprising forming a GaN based semiconductor device on the GaN epitaxial layer. In re: Saxler et al. Serial No.: 13/975,491 Filed: Pag e 3
The method of Claim 1, wherein the GaN epitaxial layer is doped with a deep level transition metal dopant.
The method of Claim 1, wherein the substrate comprises silicon.
. canceled
The method of Claim [[7]] 5, wherein the via hole and via metal extend to the substrate and wherein the via metal provides an ohmic contact to the substrate.
The method of Claim [[7]] 5, further comprising forming a region of higher doping concentration in the substrate beneath the via.
The method of Claim 9, further comprising forming a two dimensional electron gas structure (2DEG) disposed between the substrate and the GaN epitaxial layer.
. canceled
The method of Claim [[7]] 5, wherein the via hole and the via metal extend to the conductive buffer layer and wherein the via metal provides an ohmic contact to the conductive buffer layer.
The method of Claim 11, further comprising forming an etch stop layer disposed between the conductive buffer layer and the GaN epitaxial layer.
The method of Claim 11, wherein forming a conductive buffer layer comprises: forming a first conductive layer of a first conductivity type on the substrate; and forming a second conductive layer of a second conductivity type, opposite the first conductivity type, on the first conductive layer and disposed between the first conductive layer and the GaN epitaxial layer; and wherein the via hole and the via metal extend through the second conductive layer to the first conductive layer. In re: Sax ler et al. Serial No.: 13/975,49 1 Filed: Page 4
A method of fabricating a GaN semiconductor device structure, comprising: epitaxially forming an insulating or semi-insulating GaN epitaxial layer on a semiconductor substrate, the GaN epitaxial layer having a thickness of at least 4 m; and forming a conductive semiconductor layer disposed between the semiconductor substrate and the insulating or semi-insulating GaN epitaxial layer; providing a backside contact on a surface of the semiconductor substrate, opposite the insulating or semi-insulating GaN epitaxial layer; and forming a via hole and corresponding via metal in the via hole that extends through the semiconductor substrate and exposes a portion of the backside contact, wherein forming the via metal comprises forming the via metal that contacts the backside contact at the exposed portion through the semiconductor substrate.
The method of Claim 19, wherein the semiconductor substrate comprises an insulating or semi-insulating semiconductor substrate. In re: Sax ler et al. Serial No.: 13/975,49 1 Filed: Pag e
The method of Claim 19, wherein the substrate comprises silicon carbide and/or sapphire.
The method of Claim 19, wherein the semiconductor substrate comprises an electrically conductive substrate.
The method of Claim 19, wherein the substrate comprises silicon.
A method of fabricating a GaN semiconductor device structure, comprising: epitaxially forming an insulating or semi-insulating GaN epitaxial layer on a conductive SiC substrate, the GaN epitaxial layer having a thickness of at least 4 p m; and forming a conductive buffer layer disposed between the conductive SiC substrate and the GaN epitaxial layer, wherein forming a conductive buffer layer comprises: forming a first conductive layer of a first conductivity type on the substrate; and forming a second conductive layer of a second conductivity type, opposite the first conductivity type, on the first conductive layer and disposed between the first conductive layer and the GaN epitaxial layer.
The method of Claim 26, wherein the GaN epitaxial layer has a resistivity of at least about 1 05 2 -cm.
The method of Claim 26, wherein the GaN based epitaxial layer is doped with a deep level transition metal dopant. In re: Sax ler et al. Serial No.: 13/975,49 1 Filed: Page 6
. canceled
A method of fabricating a GaN semiconductor device structure, comprising: epitaxially forming an insulating or semi-insulating GaN epitaxial layer on a conductive GaN substrate; forming a GaN based semiconductor device on the GaN epitaxial layer; -and forming a via hole and corresponding via metal in the via hole that extends through layers of the GaN based semiconductor device and the GaN epitaxial layer; and providing a backside contact on a surface of the conductive GaN substrate, opposite the insulating or semi-insulating GaN epitaxial layer, wherein forming the via hole further comprises forming the via hole that extends through the conductive substrate and exposes a portion of the backside contact; and wherein forming the via metal comprises forming the via metal that contacts the backside contact at the exposed portion through the conductive substrate.
33-34. canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN semiconductor device structure on conductive semiconductor substrate
GaN semiconductor device structure with conductive semiconductor layer
GaN semiconductor device structure on conductive SiC substrate
GaN semiconductor device structure on conductive GaN substrate
AlGaN/GaN HEMT
Materials described outside the worked examples.
semi-insulating or insulating GaN epitaxial layer
GaN
conductive semiconductor substrate
conductive buffer layer
deep level transition metal dopant (Fe, Co, Mn, Cr, V and/or Ni)
silicon substrate
Si
semiconductor substrate
silicon carbide and/or sapphire substrate
diamond substrate
C
conductive SiC substrate
SiC
AlGaN barrier layer
AlGaN
aluminum nitride buffer layer
AlN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN epitaxial layer resistivity (claimed minimum) | 100000 | GaN |
Thickness | 30–200 nm | — |
Voltage | ≥ 1 V | — |
Voltage | ≥ 50 V | — |
Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a cross-section of a semiconductor structure incorporating a thick semiinsulating or insulating GaN layer according to some embodiments of the present invention.
Figure 2 is a cross-section of a semiconductor structure inco r porating a thick semiinsulating or insulating GaN layer and a conductive SiC substrate according to further embodiments of the present invention.
Figure 3 is a cross-section of a semiconductor structure incorporating a thick semiinsulating or insulating GaN layer with a conductive buffer layer on a conductive substrate according to f ur ther embodiments of the present invention.
Figure 4 is a cross-section of a semiconductor structure incorporating a thick semiinsulating or insulating GaN layer with a conductive buffer layer on a conductive SiC substrate according to further embodiments of the present invention. 7 Attorney Docket No. 5308-553TSDV
Figure 5 is a cross-section of a semiconductor structure incorporating a via through a thic k semi-insulating or insulating GaN layer on a conductive substrate according to further embodiments of the present invention.
Figure 6 is a cross-section of a semiconductor structure incorporating a via through a thick semi-insulating or insulating GaN layer with a conductive buffer layer on a conductive substrate according to further embodiments of the present invention.
Figure 7 is a cross-section of a semiconductor structure incorporating a via through a thic k semi-insulating or insulating GaN layer to an implanted layer of a conductive substrate according to fu r ther embodiments of the present invention.
Figure 8 is a cross-section of a semiconductor structure incorporating a via through a thic k semi-insulating or insulating GaN layer and a semiconductor substrate according to further embodiments of the present invention.
Figure 9 is a cross-section of a semiconductor structure incorporating a via through a thic k semi-insulating or insulating GaN layer and an etch stop layer according to further embodiments of the p resent invention.
Figure 10 is a cross-section of a semiconductor structure incorporating a thick semiinsulating or insulating GaN layer with a conductive layer according to further embodiments of the present invention.
Figure 11 is a cross-section of a semiconductor structure incorporating a via through a thick semi-insulating or insulating GaN layer on a conductive layer according to further embodiments of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a semiconductor device structure, comprising: epitaxially forming a semi-insulating or insulating GaN epitaxial layer on a conductive semiconductor substrate, the semi-insulating or insulating GaN epitaxial layer having a thickness of at least about 4 p m; and forming a conductive buffer layer disposed between the substrate and the GaN epitaxial layer; providing a backside contact on a surface of the conductive substrate, opposite the insulating or semi-insulating GaN epitaxial layer; and forming a via hole and corresponding via metal in the via hole that extends through the conductive substrate and exposes a portion of the backside contact, wherein forming the via metal comprises forming the via metal that contacts the backside contact at the exposed portion through the conductive substrate.
The method of Claim 1, wherein the GaN epitaxial layer has a thickness of at least about 8 pm.
The method of Claim 1, wherein the GaN epitaxial layer has a thickness of at least about pm.
The method of Claim 1; wherein the GaN epitaxial layer has a resistivity of at least 1 05 £2-cm.
The method of Claim 1, further comprising forming a GaN based semiconductor device on the GaN epitaxial layer. In re: Saxler et al. Serial No.: 13/975,491 Filed: Pag e 3
The method of Claim 1, wherein the GaN epitaxial layer is doped with a deep level transition metal dopant.
The method of Claim 1, wherein the substrate comprises silicon.
. canceled
The method of Claim [[7]] 5, wherein the via hole and via metal extend to the substrate and wherein the via metal provides an ohmic contact to the substrate.
The method of Claim [[7]] 5, further comprising forming a region of higher doping concentration in the substrate beneath the via.
The method of Claim 9, further comprising forming a two dimensional electron gas structure (2DEG) disposed between the substrate and the GaN epitaxial layer.
. canceled
The method of Claim [[7]] 5, wherein the via hole and the via metal extend to the conductive buffer layer and wherein the via metal provides an ohmic contact to the conductive buffer layer.
The method of Claim 11, further comprising forming an etch stop layer disposed between the conductive buffer layer and the GaN epitaxial layer.
The method of Claim 11, wherein forming a conductive buffer layer comprises: forming a first conductive layer of a first conductivity type on the substrate; and forming a second conductive layer of a second conductivity type, opposite the first conductivity type, on the first conductive layer and disposed between the first conductive layer and the GaN epitaxial layer; and wherein the via hole and the via metal extend through the second conductive layer to the first conductive layer. In re: Sax ler et al. Serial No.: 13/975,49 1 Filed: Page 4
A method of fabricating a GaN semiconductor device structure, comprising: epitaxially forming an insulating or semi-insulating GaN epitaxial layer on a semiconductor substrate, the GaN epitaxial layer having a thickness of at least 4 m; and forming a conductive semiconductor layer disposed between the semiconductor substrate and the insulating or semi-insulating GaN epitaxial layer; providing a backside contact on a surface of the semiconductor substrate, opposite the insulating or semi-insulating GaN epitaxial layer; and forming a via hole and corresponding via metal in the via hole that extends through the semiconductor substrate and exposes a portion of the backside contact, wherein forming the via metal comprises forming the via metal that contacts the backside contact at the exposed portion through the semiconductor substrate.
The method of Claim 19, wherein the semiconductor substrate comprises an insulating or semi-insulating semiconductor substrate. In re: Sax ler et al. Serial No.: 13/975,49 1 Filed: Pag e
The method of Claim 19, wherein the substrate comprises silicon carbide and/or sapphire.
The method of Claim 19, wherein the semiconductor substrate comprises an electrically conductive substrate.
The method of Claim 19, wherein the substrate comprises silicon.
A method of fabricating a GaN semiconductor device structure, comprising: epitaxially forming an insulating or semi-insulating GaN epitaxial layer on a conductive SiC substrate, the GaN epitaxial layer having a thickness of at least 4 p m; and forming a conductive buffer layer disposed between the conductive SiC substrate and the GaN epitaxial layer, wherein forming a conductive buffer layer comprises: forming a first conductive layer of a first conductivity type on the substrate; and forming a second conductive layer of a second conductivity type, opposite the first conductivity type, on the first conductive layer and disposed between the first conductive layer and the GaN epitaxial layer.
The method of Claim 26, wherein the GaN epitaxial layer has a resistivity of at least about 1 05 2 -cm.
The method of Claim 26, wherein the GaN based epitaxial layer is doped with a deep level transition metal dopant. In re: Sax ler et al. Serial No.: 13/975,49 1 Filed: Page 6
. canceled
A method of fabricating a GaN semiconductor device structure, comprising: epitaxially forming an insulating or semi-insulating GaN epitaxial layer on a conductive GaN substrate; forming a GaN based semiconductor device on the GaN epitaxial layer; -and forming a via hole and corresponding via metal in the via hole that extends through layers of the GaN based semiconductor device and the GaN epitaxial layer; and providing a backside contact on a surface of the conductive GaN substrate, opposite the insulating or semi-insulating GaN epitaxial layer, wherein forming the via hole further comprises forming the via hole that extends through the conductive substrate and exposes a portion of the backside contact; and wherein forming the via metal comprises forming the via metal that contacts the backside contact at the exposed portion through the conductive substrate.
33-34. canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN semiconductor device structure on conductive semiconductor substrate
GaN semiconductor device structure with conductive semiconductor layer
GaN semiconductor device structure on conductive SiC substrate
GaN semiconductor device structure on conductive GaN substrate
AlGaN/GaN HEMT
Materials described outside the worked examples.
semi-insulating or insulating GaN epitaxial layer
GaN
conductive semiconductor substrate
conductive buffer layer
deep level transition metal dopant (Fe, Co, Mn, Cr, V and/or Ni)
silicon substrate
Si
semiconductor substrate
silicon carbide and/or sapphire substrate
diamond substrate
C
conductive SiC substrate
SiC
AlGaN barrier layer
AlGaN
aluminum nitride buffer layer
AlN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN epitaxial layer resistivity (claimed minimum) | 100000 | GaN |
Thickness | 30–200 nm | — |
Voltage | ≥ 1 V | — |
Voltage | ≥ 50 V | — |
Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a cross-section of a semiconductor structure incorporating a thick semiinsulating or insulating GaN layer according to some embodiments of the present invention.
Figure 2 is a cross-section of a semiconductor structure inco r porating a thick semiinsulating or insulating GaN layer and a conductive SiC substrate according to further embodiments of the present invention.
Figure 3 is a cross-section of a semiconductor structure incorporating a thick semiinsulating or insulating GaN layer with a conductive buffer layer on a conductive substrate according to f ur ther embodiments of the present invention.
Figure 4 is a cross-section of a semiconductor structure incorporating a thick semiinsulating or insulating GaN layer with a conductive buffer layer on a conductive SiC substrate according to further embodiments of the present invention. 7 Attorney Docket No. 5308-553TSDV
Figure 5 is a cross-section of a semiconductor structure incorporating a via through a thic k semi-insulating or insulating GaN layer on a conductive substrate according to further embodiments of the present invention.
Figure 6 is a cross-section of a semiconductor structure incorporating a via through a thick semi-insulating or insulating GaN layer with a conductive buffer layer on a conductive substrate according to further embodiments of the present invention.
Figure 7 is a cross-section of a semiconductor structure incorporating a via through a thic k semi-insulating or insulating GaN layer to an implanted layer of a conductive substrate according to fu r ther embodiments of the present invention.
Figure 8 is a cross-section of a semiconductor structure incorporating a via through a thic k semi-insulating or insulating GaN layer and a semiconductor substrate according to further embodiments of the present invention.
Figure 9 is a cross-section of a semiconductor structure incorporating a via through a thic k semi-insulating or insulating GaN layer and an etch stop layer according to further embodiments of the p resent invention.
Figure 10 is a cross-section of a semiconductor structure incorporating a thick semiinsulating or insulating GaN layer with a conductive layer according to further embodiments of the present invention.
Figure 11 is a cross-section of a semiconductor structure incorporating a via through a thick semi-insulating or insulating GaN layer on a conductive layer according to further embodiments of the present invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method of fabricating a semiconductor device structure, comprising: epitaxially forming a semi-insulating or insulating GaN epitaxial layer on a conductive semiconductor substrate, the semi-insulating or insulating GaN epitaxial layer having a thickness of at least about 4 p m; and forming a conductive buffer layer disposed between the substrate and the GaN epitaxial layer; providing a backside contact on a surface of the conductive substrate, opposite the insulating or semi-insulating GaN epitaxial layer; and forming a via hole and corresponding via metal in the via hole that extends through the conductive substrate and exposes a portion of the backside contact, wherein forming the via metal comprises forming the via metal that contacts the backside contact at the exposed portion through the conductive substrate.
The method of Claim 1, wherein the GaN epitaxial layer has a thickness of at least about 8 pm.
The method of Claim 1, wherein the GaN epitaxial layer has a thickness of at least about pm.
The method of Claim 1; wherein the GaN epitaxial layer has a resistivity of at least 1 05 £2-cm.
The method of Claim 1, further comprising forming a GaN based semiconductor device on the GaN epitaxial layer. In re: Saxler et al. Serial No.: 13/975,491 Filed: Pag e 3
The method of Claim 1, wherein the GaN epitaxial layer is doped with a deep level transition metal dopant.
The method of Claim 1, wherein the substrate comprises silicon.
. canceled
The method of Claim [[7]] 5, wherein the via hole and via metal extend to the substrate and wherein the via metal provides an ohmic contact to the substrate.
The method of Claim [[7]] 5, further comprising forming a region of higher doping concentration in the substrate beneath the via.
The method of Claim 9, further comprising forming a two dimensional electron gas structure (2DEG) disposed between the substrate and the GaN epitaxial layer.
. canceled
The method of Claim [[7]] 5, wherein the via hole and the via metal extend to the conductive buffer layer and wherein the via metal provides an ohmic contact to the conductive buffer layer.
The method of Claim 11, further comprising forming an etch stop layer disposed between the conductive buffer layer and the GaN epitaxial layer.
The method of Claim 11, wherein forming a conductive buffer layer comprises: forming a first conductive layer of a first conductivity type on the substrate; and forming a second conductive layer of a second conductivity type, opposite the first conductivity type, on the first conductive layer and disposed between the first conductive layer and the GaN epitaxial layer; and wherein the via hole and the via metal extend through the second conductive layer to the first conductive layer. In re: Sax ler et al. Serial No.: 13/975,49 1 Filed: Page 4
A method of fabricating a GaN semiconductor device structure, comprising: epitaxially forming an insulating or semi-insulating GaN epitaxial layer on a semiconductor substrate, the GaN epitaxial layer having a thickness of at least 4 m; and forming a conductive semiconductor layer disposed between the semiconductor substrate and the insulating or semi-insulating GaN epitaxial layer; providing a backside contact on a surface of the semiconductor substrate, opposite the insulating or semi-insulating GaN epitaxial layer; and forming a via hole and corresponding via metal in the via hole that extends through the semiconductor substrate and exposes a portion of the backside contact, wherein forming the via metal comprises forming the via metal that contacts the backside contact at the exposed portion through the semiconductor substrate.
The method of Claim 19, wherein the semiconductor substrate comprises an insulating or semi-insulating semiconductor substrate. In re: Sax ler et al. Serial No.: 13/975,49 1 Filed: Pag e
The method of Claim 19, wherein the substrate comprises silicon carbide and/or sapphire.
The method of Claim 19, wherein the semiconductor substrate comprises an electrically conductive substrate.
The method of Claim 19, wherein the substrate comprises silicon.
A method of fabricating a GaN semiconductor device structure, comprising: epitaxially forming an insulating or semi-insulating GaN epitaxial layer on a conductive SiC substrate, the GaN epitaxial layer having a thickness of at least 4 p m; and forming a conductive buffer layer disposed between the conductive SiC substrate and the GaN epitaxial layer, wherein forming a conductive buffer layer comprises: forming a first conductive layer of a first conductivity type on the substrate; and forming a second conductive layer of a second conductivity type, opposite the first conductivity type, on the first conductive layer and disposed between the first conductive layer and the GaN epitaxial layer.
The method of Claim 26, wherein the GaN epitaxial layer has a resistivity of at least about 1 05 2 -cm.
The method of Claim 26, wherein the GaN based epitaxial layer is doped with a deep level transition metal dopant. In re: Sax ler et al. Serial No.: 13/975,49 1 Filed: Page 6
. canceled
A method of fabricating a GaN semiconductor device structure, comprising: epitaxially forming an insulating or semi-insulating GaN epitaxial layer on a conductive GaN substrate; forming a GaN based semiconductor device on the GaN epitaxial layer; -and forming a via hole and corresponding via metal in the via hole that extends through layers of the GaN based semiconductor device and the GaN epitaxial layer; and providing a backside contact on a surface of the conductive GaN substrate, opposite the insulating or semi-insulating GaN epitaxial layer, wherein forming the via hole further comprises forming the via hole that extends through the conductive substrate and exposes a portion of the backside contact; and wherein forming the via metal comprises forming the via metal that contacts the backside contact at the exposed portion through the conductive substrate.
33-34. canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN semiconductor device structure on conductive semiconductor substrate
GaN semiconductor device structure with conductive semiconductor layer
GaN semiconductor device structure on conductive SiC substrate
GaN semiconductor device structure on conductive GaN substrate
AlGaN/GaN HEMT
Materials described outside the worked examples.
semi-insulating or insulating GaN epitaxial layer
GaN
conductive semiconductor substrate
conductive buffer layer
deep level transition metal dopant (Fe, Co, Mn, Cr, V and/or Ni)
silicon substrate
Si
semiconductor substrate
silicon carbide and/or sapphire substrate
diamond substrate
C
conductive SiC substrate
SiC
AlGaN barrier layer
AlGaN
aluminum nitride buffer layer
AlN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
GaN epitaxial layer resistivity (claimed minimum) | 100000 | GaN |
Thickness | 30–200 nm | — |
Voltage | ≥ 1 V | — |
Voltage | ≥ 50 V | — |