Patent
US 10,700,201HEMT GaN DEVICE WITH A NON-UNIFORM LATERAL TWO DIMENSIONAL ELECTRON GAS PROFILE AND METHOD OF MANUFACTURING THE SAME
Sameh G. Khalil
US
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Patent
Atlas literature
Patent
US 10,700,201Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a deposited layer on top of the carrier supplying layer with varying size openings to induce a stress and modulate the density of a two …
FIG. 2 shows a deposited layer on top of the carrier supplying layer with a varying height profile to induce a stress and modulate the density of a two …
FIG. 4 shows another embodiment of a stress inducing layer with a varying height profile to induce a stress and modulate the density of a two dimensional …
FIG. 5 shows a deposited layer on top of the carrier supplying layer with openings increasing in size from the gate to the drain in accordance with the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high electron mobility field effect transistor (HEMT) having a substrate, a channel layer on the substrate and a barrier layer on the channel layer, the HEMT comprising: a stress inducing layer on the barrier layer, the stress inducing layer varying a piezo-electric effect in the barrier layer in a drift region between a gate and a drain; wherein a two dimensional electron gas (2DEG) has a non- uniform lateral distribution in the drift region between the gate and the drain; wherein the stress inducing layer comprises a material having a height that decreases linearly and monotonically in the drift region in the direction from the gate towards the drain; and wherein the 2DEG decreases in density in the drift region between the gate and the drain.
The HEMT of claim 1 further comprising: an opening in the stress inducing layer under the drain for providing contact of the drain to the barrier layer; and an opening in the stress inducing layer under a source for providing contact of the source to the barrier layer.
The HEMT of claim 1 further comprising: a passivation layer over the stress inducing layer.
The HEMT of claim 1 wherein: the substrate comprises silicon (Si), sapphire, silicon carbide (SiC), OR bulk single crystal gallium nitride (S aN); the channel layer comprises a S aN layer; and the barrier layer comprises a Al ~ aN layer.
A method of fabricating a high electron mobility field effect transistor (HEMT), the method comprising: forming a channel layer on a substrate; forming a barrier layer on the channel layer; and forming a stress inducing layer on the barrier layer, the stress inducing layer varying the piezo-electric effect in the barrier layer in a drift region between a gate and a drain; wherein a two dimensional electron gas (2DEG) has a non- uniform lateral distribution in the drift region between the gate and the drain.
The method of claim 7 wherein forming the stress inducing layer on the barrier layer comprises forming a material having a plurality of varying size openings between the gate and the drain.
The method of claim 7 wherein forming the stress inducing layer on the barrier layer comprises forming a material having a height that increases linearly and monotonically from the gate towards the drain using gray scale photolithography.
The method of claim 7 wherein forming the stress inducing layer on the barrier layer comprises forming a material having a height that decreases linearly and monotonically from the gate towards the drain using gray scale photolithography.
The method of claim 7 wherein: the substrate comprises silicon (Si), sapphire, silicon carbide (SiC), OR bulk single crystal gallium nitride (GaN); the channel layer comprises a GaN layer; and the barrier layer comprises a l GaN layer.
The method of claim 7 further comprising: forming a passivation layer over the barrier layer; and forming a gate comprising the steps of: forming a trench extending through the passivation layer and into the barrier layer; and depositing a gate dielectric layer in the trench; and forming gate metal on the gate dielectric.
The method of claim 7 further comprising: forming an opening in the stress inducing layer under the drain for providing contact of the drain to the barrier layer; and forming an opening in the stress inducing layer under a source for providing contact of the source to the barrier layer.
Layer stacks claimed or described, ordered top of device to substrate.
high electron mobility field effect transistor (HEMT)
Materials described outside the worked examples.
substrate
GaN
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,700,201Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a deposited layer on top of the carrier supplying layer with varying size openings to induce a stress and modulate the density of a two …
FIG. 2 shows a deposited layer on top of the carrier supplying layer with a varying height profile to induce a stress and modulate the density of a two …
FIG. 4 shows another embodiment of a stress inducing layer with a varying height profile to induce a stress and modulate the density of a two dimensional …
FIG. 5 shows a deposited layer on top of the carrier supplying layer with openings increasing in size from the gate to the drain in accordance with the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high electron mobility field effect transistor (HEMT) having a substrate, a channel layer on the substrate and a barrier layer on the channel layer, the HEMT comprising: a stress inducing layer on the barrier layer, the stress inducing layer varying a piezo-electric effect in the barrier layer in a drift region between a gate and a drain; wherein a two dimensional electron gas (2DEG) has a non- uniform lateral distribution in the drift region between the gate and the drain; wherein the stress inducing layer comprises a material having a height that decreases linearly and monotonically in the drift region in the direction from the gate towards the drain; and wherein the 2DEG decreases in density in the drift region between the gate and the drain.
The HEMT of claim 1 further comprising: an opening in the stress inducing layer under the drain for providing contact of the drain to the barrier layer; and an opening in the stress inducing layer under a source for providing contact of the source to the barrier layer.
The HEMT of claim 1 further comprising: a passivation layer over the stress inducing layer.
The HEMT of claim 1 wherein: the substrate comprises silicon (Si), sapphire, silicon carbide (SiC), OR bulk single crystal gallium nitride (S aN); the channel layer comprises a S aN layer; and the barrier layer comprises a Al ~ aN layer.
A method of fabricating a high electron mobility field effect transistor (HEMT), the method comprising: forming a channel layer on a substrate; forming a barrier layer on the channel layer; and forming a stress inducing layer on the barrier layer, the stress inducing layer varying the piezo-electric effect in the barrier layer in a drift region between a gate and a drain; wherein a two dimensional electron gas (2DEG) has a non- uniform lateral distribution in the drift region between the gate and the drain.
The method of claim 7 wherein forming the stress inducing layer on the barrier layer comprises forming a material having a plurality of varying size openings between the gate and the drain.
The method of claim 7 wherein forming the stress inducing layer on the barrier layer comprises forming a material having a height that increases linearly and monotonically from the gate towards the drain using gray scale photolithography.
The method of claim 7 wherein forming the stress inducing layer on the barrier layer comprises forming a material having a height that decreases linearly and monotonically from the gate towards the drain using gray scale photolithography.
The method of claim 7 wherein: the substrate comprises silicon (Si), sapphire, silicon carbide (SiC), OR bulk single crystal gallium nitride (GaN); the channel layer comprises a GaN layer; and the barrier layer comprises a l GaN layer.
The method of claim 7 further comprising: forming a passivation layer over the barrier layer; and forming a gate comprising the steps of: forming a trench extending through the passivation layer and into the barrier layer; and depositing a gate dielectric layer in the trench; and forming gate metal on the gate dielectric.
The method of claim 7 further comprising: forming an opening in the stress inducing layer under the drain for providing contact of the drain to the barrier layer; and forming an opening in the stress inducing layer under a source for providing contact of the source to the barrier layer.
Layer stacks claimed or described, ordered top of device to substrate.
high electron mobility field effect transistor (HEMT)
Materials described outside the worked examples.
substrate
GaN
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,700,201Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a deposited layer on top of the carrier supplying layer with varying size openings to induce a stress and modulate the density of a two …
FIG. 2 shows a deposited layer on top of the carrier supplying layer with a varying height profile to induce a stress and modulate the density of a two …
FIG. 4 shows another embodiment of a stress inducing layer with a varying height profile to induce a stress and modulate the density of a two dimensional …
FIG. 5 shows a deposited layer on top of the carrier supplying layer with openings increasing in size from the gate to the drain in accordance with the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high electron mobility field effect transistor (HEMT) having a substrate, a channel layer on the substrate and a barrier layer on the channel layer, the HEMT comprising: a stress inducing layer on the barrier layer, the stress inducing layer varying a piezo-electric effect in the barrier layer in a drift region between a gate and a drain; wherein a two dimensional electron gas (2DEG) has a non- uniform lateral distribution in the drift region between the gate and the drain; wherein the stress inducing layer comprises a material having a height that decreases linearly and monotonically in the drift region in the direction from the gate towards the drain; and wherein the 2DEG decreases in density in the drift region between the gate and the drain.
The HEMT of claim 1 further comprising: an opening in the stress inducing layer under the drain for providing contact of the drain to the barrier layer; and an opening in the stress inducing layer under a source for providing contact of the source to the barrier layer.
The HEMT of claim 1 further comprising: a passivation layer over the stress inducing layer.
The HEMT of claim 1 wherein: the substrate comprises silicon (Si), sapphire, silicon carbide (SiC), OR bulk single crystal gallium nitride (S aN); the channel layer comprises a S aN layer; and the barrier layer comprises a Al ~ aN layer.
A method of fabricating a high electron mobility field effect transistor (HEMT), the method comprising: forming a channel layer on a substrate; forming a barrier layer on the channel layer; and forming a stress inducing layer on the barrier layer, the stress inducing layer varying the piezo-electric effect in the barrier layer in a drift region between a gate and a drain; wherein a two dimensional electron gas (2DEG) has a non- uniform lateral distribution in the drift region between the gate and the drain.
The method of claim 7 wherein forming the stress inducing layer on the barrier layer comprises forming a material having a plurality of varying size openings between the gate and the drain.
The method of claim 7 wherein forming the stress inducing layer on the barrier layer comprises forming a material having a height that increases linearly and monotonically from the gate towards the drain using gray scale photolithography.
The method of claim 7 wherein forming the stress inducing layer on the barrier layer comprises forming a material having a height that decreases linearly and monotonically from the gate towards the drain using gray scale photolithography.
The method of claim 7 wherein: the substrate comprises silicon (Si), sapphire, silicon carbide (SiC), OR bulk single crystal gallium nitride (GaN); the channel layer comprises a GaN layer; and the barrier layer comprises a l GaN layer.
The method of claim 7 further comprising: forming a passivation layer over the barrier layer; and forming a gate comprising the steps of: forming a trench extending through the passivation layer and into the barrier layer; and depositing a gate dielectric layer in the trench; and forming gate metal on the gate dielectric.
The method of claim 7 further comprising: forming an opening in the stress inducing layer under the drain for providing contact of the drain to the barrier layer; and forming an opening in the stress inducing layer under a source for providing contact of the source to the barrier layer.
Layer stacks claimed or described, ordered top of device to substrate.
high electron mobility field effect transistor (HEMT)
Materials described outside the worked examples.
substrate
GaN
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,700,201Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 shows a deposited layer on top of the carrier supplying layer with varying size openings to induce a stress and modulate the density of a two …
FIG. 2 shows a deposited layer on top of the carrier supplying layer with a varying height profile to induce a stress and modulate the density of a two …
FIG. 4 shows another embodiment of a stress inducing layer with a varying height profile to induce a stress and modulate the density of a two dimensional …
FIG. 5 shows a deposited layer on top of the carrier supplying layer with openings increasing in size from the gate to the drain in accordance with the present …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high electron mobility field effect transistor (HEMT) having a substrate, a channel layer on the substrate and a barrier layer on the channel layer, the HEMT comprising: a stress inducing layer on the barrier layer, the stress inducing layer varying a piezo-electric effect in the barrier layer in a drift region between a gate and a drain; wherein a two dimensional electron gas (2DEG) has a non- uniform lateral distribution in the drift region between the gate and the drain; wherein the stress inducing layer comprises a material having a height that decreases linearly and monotonically in the drift region in the direction from the gate towards the drain; and wherein the 2DEG decreases in density in the drift region between the gate and the drain.
The HEMT of claim 1 further comprising: an opening in the stress inducing layer under the drain for providing contact of the drain to the barrier layer; and an opening in the stress inducing layer under a source for providing contact of the source to the barrier layer.
The HEMT of claim 1 further comprising: a passivation layer over the stress inducing layer.
The HEMT of claim 1 wherein: the substrate comprises silicon (Si), sapphire, silicon carbide (SiC), OR bulk single crystal gallium nitride (S aN); the channel layer comprises a S aN layer; and the barrier layer comprises a Al ~ aN layer.
A method of fabricating a high electron mobility field effect transistor (HEMT), the method comprising: forming a channel layer on a substrate; forming a barrier layer on the channel layer; and forming a stress inducing layer on the barrier layer, the stress inducing layer varying the piezo-electric effect in the barrier layer in a drift region between a gate and a drain; wherein a two dimensional electron gas (2DEG) has a non- uniform lateral distribution in the drift region between the gate and the drain.
The method of claim 7 wherein forming the stress inducing layer on the barrier layer comprises forming a material having a plurality of varying size openings between the gate and the drain.
The method of claim 7 wherein forming the stress inducing layer on the barrier layer comprises forming a material having a height that increases linearly and monotonically from the gate towards the drain using gray scale photolithography.
The method of claim 7 wherein forming the stress inducing layer on the barrier layer comprises forming a material having a height that decreases linearly and monotonically from the gate towards the drain using gray scale photolithography.
The method of claim 7 wherein: the substrate comprises silicon (Si), sapphire, silicon carbide (SiC), OR bulk single crystal gallium nitride (GaN); the channel layer comprises a GaN layer; and the barrier layer comprises a l GaN layer.
The method of claim 7 further comprising: forming a passivation layer over the barrier layer; and forming a gate comprising the steps of: forming a trench extending through the passivation layer and into the barrier layer; and depositing a gate dielectric layer in the trench; and forming gate metal on the gate dielectric.
The method of claim 7 further comprising: forming an opening in the stress inducing layer under the drain for providing contact of the drain to the barrier layer; and forming an opening in the stress inducing layer under a source for providing contact of the source to the barrier layer.
Layer stacks claimed or described, ordered top of device to substrate.
high electron mobility field effect transistor (HEMT)
Materials described outside the worked examples.
substrate
GaN
Additional fabrication and treatment steps described in the patent.
Related documents with shared materials, methods, properties, or citations.
AlGaN
stress inducing layer
passivation layer
silicon
Si
sapphire
silicon carbide
SiC
AlN spacer layer
AlN
buffer layer of GaN or AlGaN
AlGaN
stress inducing layer
passivation layer
silicon
Si
sapphire
silicon carbide
SiC
AlN spacer layer
AlN
buffer layer of GaN or AlGaN
AlGaN
stress inducing layer
passivation layer
silicon
Si
sapphire
silicon carbide
SiC
AlN spacer layer
AlN
buffer layer of GaN or AlGaN
AlGaN
stress inducing layer
passivation layer
silicon
Si
sapphire
silicon carbide
SiC
AlN spacer layer
AlN
buffer layer of GaN or AlGaN