Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a sectional view of a HEMT in accordance with an example embodiment of the invention.
FIG. 2 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 3 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 4 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 5 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 6 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 7 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 8 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 9 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 10 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 11 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 12 is a graph showing 2D TCAD simulations illus- trating an impact of embedded, non-overlapping source field plate in accordance with an example embodiment …
FIG. 20 1, having many features that are similar to those in the HEMT 100, and for those similar features the same refer- ence numbers are used in describing …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device comprising: 45 a semiconductor die including a plurality of semiconduc-tor layers disposed on an insulating substrate; a source contact and a drain contact electrically coupled to a channel formed in the semiconductor layers and defining an active area of the device; 50 a barrier layer formed on a channel layer of said semiconductor die within said active area of the device; a cap layer formed on said barrier layer of said semicon-ductor die within said active area of the device; a first passivation layer formed on a surface of said cap layer of said semiconductor die within said active area of the device; a T-shaped gate contact disposed within said active area of the device, wherein (i) said T-shaped gate contact is electrically separated from said channel and comprises 60 a column portion and a cap portion, (ii) said column portion extends from a bottom surface of said cap portion, through an opening in said first passivation layer, and contacts said surface of said cap layer of said semiconductor die, and (111) said bottom surface of said cap portion contacts a surface of said first passivation layer; a field plate disposed above said first passivation layer within said active area of the device, wherein the entire field plate is laterally separated from a drain edge of said bottom surface of said cap portion of said T-shaped gate contact by a first distance ranging from about 0.1 µm to about 1 µm, a bottom surface of the entire field plate is uniformly separated from said surface of said cap layer by at least said first passivation layer, and the entire field plate is non-overlapping of said cap portion of said T-shaped gate contact; and a second passivation layer formed on said surface of said first passivation layer, upper surfaces of said cap por-tion of said T-shaped gate contact, and upper surfaces of said field plate.
The device according to claim 1, wherein said device comprises at least one of a gallium nitride (GaN) transistor, a metal oxide semiconductor field effect transistor (MOS-FET), and a metal insulator semiconductor high electron mobility transistor (MIS-HEMT).
The device according to claim 1, wherein said device comprises a Nitrogen polar (n-polar) or Gallium polar (Ga-polar) device structure.
The device according to claim 1, wherein said field plate comprises a source connected field plate.
The device according to claim 1, wherein said device comprises a high electron mobility transistor (HEMT) hav-ing a source connected field plate.
The device according to claim 1, wherein said field plate comprises multiple fingers.
The device according to claim 1, wherein: said first passivation layer comprises an inorganic dielec-tric layer; said second passivation layer comprises an inorganic dielectric layer or an organic dielectric layer; and said field plate is embedded between said first passivation layer and said second passivation layer.
The device according to claim 1, wherein said field plate and said cap portion of said T-shaped gate contact have the same thickness.
The device according to claim 1, wherein said field plate has a first thickness, said cap portion of said T-shaped gate contact has a second thickness, and the first thickness is smaller than the second thickness.
The device according to claim 1, wherein said field plate has a first thickness, said cap portion of said T-shaped gate contact has a second thickness, and the first thickness is greater than the second thickness.
The device according to claim 1, wherein: said cap portion of said T-shaped gate contact is formed on said first passivation layer; and said field plate is formed on said surface of said first passivation layer.
The device according to claim 1, wherein: said cap portion of said T-shaped gate contact is formed on said first passivation layer; and a portion or all of said field plate is embedded within a recess in said first passivation layer.
The device according to claim 1, wherein: said cap portion of said T-shaped gate contact is formed on said first passivation layer; and said field plate is disposed above and the bottom surface of the entire field plate is uniformly separated from said surface of said first passivation layer by a second distance ranging from about 0.05 µm to about 0.5 µm, and is completely embedded in said second passivation layer.
The device according to claim 1, wherein: said cap portion of said T-shaped gate contact is formed on said first passivation layer; and said field plate is disposed above and the bottom surface of the entire field plate is uniformly separated from said surface of said first passivation layer by a second distance ranging from about 0.05 µm to about 0.5 µm, and is partially embedded in said second passivation layer.
The device according to claim 1, wherein: said field plate is formed on said first passivation layer; said cap portion of said T-shaped gate contact is separated from said first passivation layer by a portion of said second passivation layer; and said column portion of said T-shaped gate contact extends through said portion of said second passivation layer and through said first passivation layer.
The device according to claim 1, wherein: said plurality of semiconductor layers include said barrier layer and said channel layer forming a heterojunction; said barrier layer comprises at least one of an aluminum gallium nitride (AlGaN) epi layer, an indium aluminum nitride (InAlN) epi layer, and an aluminum nitride (AlN) epi layer; said channel layer comprises a gallium nitride (GaN) epi layer; and said epi layers are grown on a substrate comprising at least one of silicon, silicon carbide (SiC), Sapphire, and Diamond.
A device comprising: 30 a semiconductor die including a plurality of semiconduc-tor layers disposed on an insulating substrate; a source contact and a drain contact electrically coupled to a channel formed in the semiconductor layers and defining an active area of the device; 35 a barrier layer formed on a channel layer of said semiconductor die within said active area of the device; a cap layer formed on said barrier layer of said semicon-ductor die within said active area of the device; a first passivation layer formed on a surface of said cap layer of said semiconductor die within said active area of the device; a T-shaped gate contact disposed within said active area of the device, wherein (i) said T-shaped gate contact is electrically separated from said channel and comprises 45 a column portion and a cap portion, (ii) said column portion extends from a bottom surface of said cap portion, through an opening in said first passivation layer, and contacts said surface of said cap layer of said semiconductor die, and (111) said bottom surface of said cap portion contacts a surface of said first passivation layer; a first source connected field plate formed on said first passivation layer within said active area of the device, wherein the entire first source connected field plate is laterally separated from a drain edge of said bottom surface of said cap portion of said T-shaped gate contact by a distance ranging from about 0.1 µm to about 1 µm, a bottom surface of the entire field plate is uniformly separated from said surface of said cap layer B₁ by at least said first passivation layer, and the entire first source connected field plate is non-overlapping of said cap portion of said T-shaped gate contact; a second passivation layer formed on said surface of said first passivation layer, upper surfaces of said cap por-tion of said T-shaped gate contact, and upper surfaces of said first source connected field plate; and a second source connected field plate disposed on said second passivation layer above said first source con-nected field plate and extending lateral toward said source contact such that said second source connected field plate overlaps said T-shaped gate contact.
A device comprising: a semiconductor die including a plurality of semiconduc-tor layers disposed on an insulating substrate; a source contact and a drain contact electrically coupled to a channel formed in the semiconductor layers and defining an active area of the device; a barrier layer formed on a channel layer of said semiconductor die within said active area of the device; a cap layer formed on said barrier layer of said semicon-ductor die within said active area of the device; a first passivation layer formed on a surface of said cap layer of said semiconductor die within said active area of the device; a T-shaped gate contact disposed within said active area of the device, wherein (i) said T-shaped gate contact is electrically separated from said channel and comprises a column portion and a cap portion, (ii) said column portion extends from a bottom surface of said cap portion, through an opening in said first passivation layer, and contacts said surface of said cap layer of said semiconductor die, and (111) said cap portion is formed on said first passivation layer; a second passivation layer covering said first passivation layer and said cap portion of said T-shaped gate con-tact; and a source connected field plate adjacent to and laterally separated from said cap portion of said T-shaped gate contact, wherein said source connected field plate has a first portion and a second portion, the first portion overlaps said cap portion of said T-shaped gate contact, the second portion has a bottom edge that is formed within a recess etched in at least one of said first passivation layer and said second passivation layer, the entire second portion is laterally separated from a drain edge of said bottom surface of said cap portion of said T-shaped gate contact by a distance ranging from about 0.1 µm to about 1 µm, and the entire second portion is non-overlapping of said cap portion of said T-shaped gate contact.
The device according to claim 18, wherein a vertical position of said bottom edge of said second portion of said source connected field plate is lower than said bottom surface of said cap portion of said T shaped gate contact.
The device according to claim 18, wherein said bottom edge of said second portion of said source connected field plate and said bottom surface of said cap portion of said T shaped gate contact are at the same level. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT with embedded non-overlapping source field plate
GaN HEMT with first and second source connected field plates
GaN HEMT with recessed source connected field plate having overlapping first portion and non-overlapping second portion
HEMT 100 (described embodiment)
Materials described outside the worked examples.
gallium nitride
GaN
barrier layer material
first passivation layer (inorganic dielectric)
cap layer
second passivation layer (inorganic or organic dielectric)
aluminum gallium nitride
AlGaN
indium aluminum nitride
InAlN
aluminum nitride
AlN
silicon
Si
silicon carbide
SiC
sapphire
diamond
nucleation layer
AlzGa₁-zN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 12 is a graph showing 2D TCAD simulations illus- trating an impact of embedded, non-overlapping source field plate in accordance with an example embodiment …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.1–1 µm | — |
Thickness | 50–500 nm | — |
Thickness | 10–1000 nm | — |
Thickness | 0.2–2 um | — |
Thickness | 0.5–2 µm | — |
Thickness | 0.05–0.5 µm | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 8
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Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a sectional view of a HEMT in accordance with an example embodiment of the invention.
FIG. 2 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 3 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 4 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 5 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 6 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 7 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 8 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 9 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 10 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 11 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 12 is a graph showing 2D TCAD simulations illus- trating an impact of embedded, non-overlapping source field plate in accordance with an example embodiment …
FIG. 20 1, having many features that are similar to those in the HEMT 100, and for those similar features the same refer- ence numbers are used in describing …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device comprising: 45 a semiconductor die including a plurality of semiconduc-tor layers disposed on an insulating substrate; a source contact and a drain contact electrically coupled to a channel formed in the semiconductor layers and defining an active area of the device; 50 a barrier layer formed on a channel layer of said semiconductor die within said active area of the device; a cap layer formed on said barrier layer of said semicon-ductor die within said active area of the device; a first passivation layer formed on a surface of said cap layer of said semiconductor die within said active area of the device; a T-shaped gate contact disposed within said active area of the device, wherein (i) said T-shaped gate contact is electrically separated from said channel and comprises 60 a column portion and a cap portion, (ii) said column portion extends from a bottom surface of said cap portion, through an opening in said first passivation layer, and contacts said surface of said cap layer of said semiconductor die, and (111) said bottom surface of said cap portion contacts a surface of said first passivation layer; a field plate disposed above said first passivation layer within said active area of the device, wherein the entire field plate is laterally separated from a drain edge of said bottom surface of said cap portion of said T-shaped gate contact by a first distance ranging from about 0.1 µm to about 1 µm, a bottom surface of the entire field plate is uniformly separated from said surface of said cap layer by at least said first passivation layer, and the entire field plate is non-overlapping of said cap portion of said T-shaped gate contact; and a second passivation layer formed on said surface of said first passivation layer, upper surfaces of said cap por-tion of said T-shaped gate contact, and upper surfaces of said field plate.
The device according to claim 1, wherein said device comprises at least one of a gallium nitride (GaN) transistor, a metal oxide semiconductor field effect transistor (MOS-FET), and a metal insulator semiconductor high electron mobility transistor (MIS-HEMT).
The device according to claim 1, wherein said device comprises a Nitrogen polar (n-polar) or Gallium polar (Ga-polar) device structure.
The device according to claim 1, wherein said field plate comprises a source connected field plate.
The device according to claim 1, wherein said device comprises a high electron mobility transistor (HEMT) hav-ing a source connected field plate.
The device according to claim 1, wherein said field plate comprises multiple fingers.
The device according to claim 1, wherein: said first passivation layer comprises an inorganic dielec-tric layer; said second passivation layer comprises an inorganic dielectric layer or an organic dielectric layer; and said field plate is embedded between said first passivation layer and said second passivation layer.
The device according to claim 1, wherein said field plate and said cap portion of said T-shaped gate contact have the same thickness.
The device according to claim 1, wherein said field plate has a first thickness, said cap portion of said T-shaped gate contact has a second thickness, and the first thickness is smaller than the second thickness.
The device according to claim 1, wherein said field plate has a first thickness, said cap portion of said T-shaped gate contact has a second thickness, and the first thickness is greater than the second thickness.
The device according to claim 1, wherein: said cap portion of said T-shaped gate contact is formed on said first passivation layer; and said field plate is formed on said surface of said first passivation layer.
The device according to claim 1, wherein: said cap portion of said T-shaped gate contact is formed on said first passivation layer; and a portion or all of said field plate is embedded within a recess in said first passivation layer.
The device according to claim 1, wherein: said cap portion of said T-shaped gate contact is formed on said first passivation layer; and said field plate is disposed above and the bottom surface of the entire field plate is uniformly separated from said surface of said first passivation layer by a second distance ranging from about 0.05 µm to about 0.5 µm, and is completely embedded in said second passivation layer.
The device according to claim 1, wherein: said cap portion of said T-shaped gate contact is formed on said first passivation layer; and said field plate is disposed above and the bottom surface of the entire field plate is uniformly separated from said surface of said first passivation layer by a second distance ranging from about 0.05 µm to about 0.5 µm, and is partially embedded in said second passivation layer.
The device according to claim 1, wherein: said field plate is formed on said first passivation layer; said cap portion of said T-shaped gate contact is separated from said first passivation layer by a portion of said second passivation layer; and said column portion of said T-shaped gate contact extends through said portion of said second passivation layer and through said first passivation layer.
The device according to claim 1, wherein: said plurality of semiconductor layers include said barrier layer and said channel layer forming a heterojunction; said barrier layer comprises at least one of an aluminum gallium nitride (AlGaN) epi layer, an indium aluminum nitride (InAlN) epi layer, and an aluminum nitride (AlN) epi layer; said channel layer comprises a gallium nitride (GaN) epi layer; and said epi layers are grown on a substrate comprising at least one of silicon, silicon carbide (SiC), Sapphire, and Diamond.
A device comprising: 30 a semiconductor die including a plurality of semiconduc-tor layers disposed on an insulating substrate; a source contact and a drain contact electrically coupled to a channel formed in the semiconductor layers and defining an active area of the device; 35 a barrier layer formed on a channel layer of said semiconductor die within said active area of the device; a cap layer formed on said barrier layer of said semicon-ductor die within said active area of the device; a first passivation layer formed on a surface of said cap layer of said semiconductor die within said active area of the device; a T-shaped gate contact disposed within said active area of the device, wherein (i) said T-shaped gate contact is electrically separated from said channel and comprises 45 a column portion and a cap portion, (ii) said column portion extends from a bottom surface of said cap portion, through an opening in said first passivation layer, and contacts said surface of said cap layer of said semiconductor die, and (111) said bottom surface of said cap portion contacts a surface of said first passivation layer; a first source connected field plate formed on said first passivation layer within said active area of the device, wherein the entire first source connected field plate is laterally separated from a drain edge of said bottom surface of said cap portion of said T-shaped gate contact by a distance ranging from about 0.1 µm to about 1 µm, a bottom surface of the entire field plate is uniformly separated from said surface of said cap layer B₁ by at least said first passivation layer, and the entire first source connected field plate is non-overlapping of said cap portion of said T-shaped gate contact; a second passivation layer formed on said surface of said first passivation layer, upper surfaces of said cap por-tion of said T-shaped gate contact, and upper surfaces of said first source connected field plate; and a second source connected field plate disposed on said second passivation layer above said first source con-nected field plate and extending lateral toward said source contact such that said second source connected field plate overlaps said T-shaped gate contact.
A device comprising: a semiconductor die including a plurality of semiconduc-tor layers disposed on an insulating substrate; a source contact and a drain contact electrically coupled to a channel formed in the semiconductor layers and defining an active area of the device; a barrier layer formed on a channel layer of said semiconductor die within said active area of the device; a cap layer formed on said barrier layer of said semicon-ductor die within said active area of the device; a first passivation layer formed on a surface of said cap layer of said semiconductor die within said active area of the device; a T-shaped gate contact disposed within said active area of the device, wherein (i) said T-shaped gate contact is electrically separated from said channel and comprises a column portion and a cap portion, (ii) said column portion extends from a bottom surface of said cap portion, through an opening in said first passivation layer, and contacts said surface of said cap layer of said semiconductor die, and (111) said cap portion is formed on said first passivation layer; a second passivation layer covering said first passivation layer and said cap portion of said T-shaped gate con-tact; and a source connected field plate adjacent to and laterally separated from said cap portion of said T-shaped gate contact, wherein said source connected field plate has a first portion and a second portion, the first portion overlaps said cap portion of said T-shaped gate contact, the second portion has a bottom edge that is formed within a recess etched in at least one of said first passivation layer and said second passivation layer, the entire second portion is laterally separated from a drain edge of said bottom surface of said cap portion of said T-shaped gate contact by a distance ranging from about 0.1 µm to about 1 µm, and the entire second portion is non-overlapping of said cap portion of said T-shaped gate contact.
The device according to claim 18, wherein a vertical position of said bottom edge of said second portion of said source connected field plate is lower than said bottom surface of said cap portion of said T shaped gate contact.
The device according to claim 18, wherein said bottom edge of said second portion of said source connected field plate and said bottom surface of said cap portion of said T shaped gate contact are at the same level. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT with embedded non-overlapping source field plate
GaN HEMT with first and second source connected field plates
GaN HEMT with recessed source connected field plate having overlapping first portion and non-overlapping second portion
HEMT 100 (described embodiment)
Materials described outside the worked examples.
gallium nitride
GaN
barrier layer material
first passivation layer (inorganic dielectric)
cap layer
second passivation layer (inorganic or organic dielectric)
aluminum gallium nitride
AlGaN
indium aluminum nitride
InAlN
aluminum nitride
AlN
silicon
Si
silicon carbide
SiC
sapphire
diamond
nucleation layer
AlzGa₁-zN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 12 is a graph showing 2D TCAD simulations illus- trating an impact of embedded, non-overlapping source field plate in accordance with an example embodiment …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.1–1 µm | — |
Thickness | 50–500 nm | — |
Thickness | 10–1000 nm | — |
Thickness | 0.2–2 um | — |
Thickness | 0.5–2 µm | — |
Thickness | 0.05–0.5 µm | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 8
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Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a sectional view of a HEMT in accordance with an example embodiment of the invention.
FIG. 2 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 3 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 4 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 5 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 6 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 7 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 8 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 9 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 10 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 11 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 12 is a graph showing 2D TCAD simulations illus- trating an impact of embedded, non-overlapping source field plate in accordance with an example embodiment …
FIG. 20 1, having many features that are similar to those in the HEMT 100, and for those similar features the same refer- ence numbers are used in describing …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device comprising: 45 a semiconductor die including a plurality of semiconduc-tor layers disposed on an insulating substrate; a source contact and a drain contact electrically coupled to a channel formed in the semiconductor layers and defining an active area of the device; 50 a barrier layer formed on a channel layer of said semiconductor die within said active area of the device; a cap layer formed on said barrier layer of said semicon-ductor die within said active area of the device; a first passivation layer formed on a surface of said cap layer of said semiconductor die within said active area of the device; a T-shaped gate contact disposed within said active area of the device, wherein (i) said T-shaped gate contact is electrically separated from said channel and comprises 60 a column portion and a cap portion, (ii) said column portion extends from a bottom surface of said cap portion, through an opening in said first passivation layer, and contacts said surface of said cap layer of said semiconductor die, and (111) said bottom surface of said cap portion contacts a surface of said first passivation layer; a field plate disposed above said first passivation layer within said active area of the device, wherein the entire field plate is laterally separated from a drain edge of said bottom surface of said cap portion of said T-shaped gate contact by a first distance ranging from about 0.1 µm to about 1 µm, a bottom surface of the entire field plate is uniformly separated from said surface of said cap layer by at least said first passivation layer, and the entire field plate is non-overlapping of said cap portion of said T-shaped gate contact; and a second passivation layer formed on said surface of said first passivation layer, upper surfaces of said cap por-tion of said T-shaped gate contact, and upper surfaces of said field plate.
The device according to claim 1, wherein said device comprises at least one of a gallium nitride (GaN) transistor, a metal oxide semiconductor field effect transistor (MOS-FET), and a metal insulator semiconductor high electron mobility transistor (MIS-HEMT).
The device according to claim 1, wherein said device comprises a Nitrogen polar (n-polar) or Gallium polar (Ga-polar) device structure.
The device according to claim 1, wherein said field plate comprises a source connected field plate.
The device according to claim 1, wherein said device comprises a high electron mobility transistor (HEMT) hav-ing a source connected field plate.
The device according to claim 1, wherein said field plate comprises multiple fingers.
The device according to claim 1, wherein: said first passivation layer comprises an inorganic dielec-tric layer; said second passivation layer comprises an inorganic dielectric layer or an organic dielectric layer; and said field plate is embedded between said first passivation layer and said second passivation layer.
The device according to claim 1, wherein said field plate and said cap portion of said T-shaped gate contact have the same thickness.
The device according to claim 1, wherein said field plate has a first thickness, said cap portion of said T-shaped gate contact has a second thickness, and the first thickness is smaller than the second thickness.
The device according to claim 1, wherein said field plate has a first thickness, said cap portion of said T-shaped gate contact has a second thickness, and the first thickness is greater than the second thickness.
The device according to claim 1, wherein: said cap portion of said T-shaped gate contact is formed on said first passivation layer; and said field plate is formed on said surface of said first passivation layer.
The device according to claim 1, wherein: said cap portion of said T-shaped gate contact is formed on said first passivation layer; and a portion or all of said field plate is embedded within a recess in said first passivation layer.
The device according to claim 1, wherein: said cap portion of said T-shaped gate contact is formed on said first passivation layer; and said field plate is disposed above and the bottom surface of the entire field plate is uniformly separated from said surface of said first passivation layer by a second distance ranging from about 0.05 µm to about 0.5 µm, and is completely embedded in said second passivation layer.
The device according to claim 1, wherein: said cap portion of said T-shaped gate contact is formed on said first passivation layer; and said field plate is disposed above and the bottom surface of the entire field plate is uniformly separated from said surface of said first passivation layer by a second distance ranging from about 0.05 µm to about 0.5 µm, and is partially embedded in said second passivation layer.
The device according to claim 1, wherein: said field plate is formed on said first passivation layer; said cap portion of said T-shaped gate contact is separated from said first passivation layer by a portion of said second passivation layer; and said column portion of said T-shaped gate contact extends through said portion of said second passivation layer and through said first passivation layer.
The device according to claim 1, wherein: said plurality of semiconductor layers include said barrier layer and said channel layer forming a heterojunction; said barrier layer comprises at least one of an aluminum gallium nitride (AlGaN) epi layer, an indium aluminum nitride (InAlN) epi layer, and an aluminum nitride (AlN) epi layer; said channel layer comprises a gallium nitride (GaN) epi layer; and said epi layers are grown on a substrate comprising at least one of silicon, silicon carbide (SiC), Sapphire, and Diamond.
A device comprising: 30 a semiconductor die including a plurality of semiconduc-tor layers disposed on an insulating substrate; a source contact and a drain contact electrically coupled to a channel formed in the semiconductor layers and defining an active area of the device; 35 a barrier layer formed on a channel layer of said semiconductor die within said active area of the device; a cap layer formed on said barrier layer of said semicon-ductor die within said active area of the device; a first passivation layer formed on a surface of said cap layer of said semiconductor die within said active area of the device; a T-shaped gate contact disposed within said active area of the device, wherein (i) said T-shaped gate contact is electrically separated from said channel and comprises 45 a column portion and a cap portion, (ii) said column portion extends from a bottom surface of said cap portion, through an opening in said first passivation layer, and contacts said surface of said cap layer of said semiconductor die, and (111) said bottom surface of said cap portion contacts a surface of said first passivation layer; a first source connected field plate formed on said first passivation layer within said active area of the device, wherein the entire first source connected field plate is laterally separated from a drain edge of said bottom surface of said cap portion of said T-shaped gate contact by a distance ranging from about 0.1 µm to about 1 µm, a bottom surface of the entire field plate is uniformly separated from said surface of said cap layer B₁ by at least said first passivation layer, and the entire first source connected field plate is non-overlapping of said cap portion of said T-shaped gate contact; a second passivation layer formed on said surface of said first passivation layer, upper surfaces of said cap por-tion of said T-shaped gate contact, and upper surfaces of said first source connected field plate; and a second source connected field plate disposed on said second passivation layer above said first source con-nected field plate and extending lateral toward said source contact such that said second source connected field plate overlaps said T-shaped gate contact.
A device comprising: a semiconductor die including a plurality of semiconduc-tor layers disposed on an insulating substrate; a source contact and a drain contact electrically coupled to a channel formed in the semiconductor layers and defining an active area of the device; a barrier layer formed on a channel layer of said semiconductor die within said active area of the device; a cap layer formed on said barrier layer of said semicon-ductor die within said active area of the device; a first passivation layer formed on a surface of said cap layer of said semiconductor die within said active area of the device; a T-shaped gate contact disposed within said active area of the device, wherein (i) said T-shaped gate contact is electrically separated from said channel and comprises a column portion and a cap portion, (ii) said column portion extends from a bottom surface of said cap portion, through an opening in said first passivation layer, and contacts said surface of said cap layer of said semiconductor die, and (111) said cap portion is formed on said first passivation layer; a second passivation layer covering said first passivation layer and said cap portion of said T-shaped gate con-tact; and a source connected field plate adjacent to and laterally separated from said cap portion of said T-shaped gate contact, wherein said source connected field plate has a first portion and a second portion, the first portion overlaps said cap portion of said T-shaped gate contact, the second portion has a bottom edge that is formed within a recess etched in at least one of said first passivation layer and said second passivation layer, the entire second portion is laterally separated from a drain edge of said bottom surface of said cap portion of said T-shaped gate contact by a distance ranging from about 0.1 µm to about 1 µm, and the entire second portion is non-overlapping of said cap portion of said T-shaped gate contact.
The device according to claim 18, wherein a vertical position of said bottom edge of said second portion of said source connected field plate is lower than said bottom surface of said cap portion of said T shaped gate contact.
The device according to claim 18, wherein said bottom edge of said second portion of said source connected field plate and said bottom surface of said cap portion of said T shaped gate contact are at the same level. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT with embedded non-overlapping source field plate
GaN HEMT with first and second source connected field plates
GaN HEMT with recessed source connected field plate having overlapping first portion and non-overlapping second portion
HEMT 100 (described embodiment)
Materials described outside the worked examples.
gallium nitride
GaN
barrier layer material
first passivation layer (inorganic dielectric)
cap layer
second passivation layer (inorganic or organic dielectric)
aluminum gallium nitride
AlGaN
indium aluminum nitride
InAlN
aluminum nitride
AlN
silicon
Si
silicon carbide
SiC
sapphire
diamond
nucleation layer
AlzGa₁-zN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 12 is a graph showing 2D TCAD simulations illus- trating an impact of embedded, non-overlapping source field plate in accordance with an example embodiment …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.1–1 µm | — |
Thickness | 50–500 nm | — |
Thickness | 10–1000 nm | — |
Thickness | 0.2–2 um | — |
Thickness | 0.5–2 µm | — |
Thickness | 0.05–0.5 µm | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 8
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Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a sectional view of a HEMT in accordance with an example embodiment of the invention.
FIG. 2 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 3 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 4 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 5 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 6 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 7 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 8 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 9 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 10 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 11 is a sectional view of a HEMT in accordance with another example embodiment of the invention.
FIG. 12 is a graph showing 2D TCAD simulations illus- trating an impact of embedded, non-overlapping source field plate in accordance with an example embodiment …
FIG. 20 1, having many features that are similar to those in the HEMT 100, and for those similar features the same refer- ence numbers are used in describing …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device comprising: 45 a semiconductor die including a plurality of semiconduc-tor layers disposed on an insulating substrate; a source contact and a drain contact electrically coupled to a channel formed in the semiconductor layers and defining an active area of the device; 50 a barrier layer formed on a channel layer of said semiconductor die within said active area of the device; a cap layer formed on said barrier layer of said semicon-ductor die within said active area of the device; a first passivation layer formed on a surface of said cap layer of said semiconductor die within said active area of the device; a T-shaped gate contact disposed within said active area of the device, wherein (i) said T-shaped gate contact is electrically separated from said channel and comprises 60 a column portion and a cap portion, (ii) said column portion extends from a bottom surface of said cap portion, through an opening in said first passivation layer, and contacts said surface of said cap layer of said semiconductor die, and (111) said bottom surface of said cap portion contacts a surface of said first passivation layer; a field plate disposed above said first passivation layer within said active area of the device, wherein the entire field plate is laterally separated from a drain edge of said bottom surface of said cap portion of said T-shaped gate contact by a first distance ranging from about 0.1 µm to about 1 µm, a bottom surface of the entire field plate is uniformly separated from said surface of said cap layer by at least said first passivation layer, and the entire field plate is non-overlapping of said cap portion of said T-shaped gate contact; and a second passivation layer formed on said surface of said first passivation layer, upper surfaces of said cap por-tion of said T-shaped gate contact, and upper surfaces of said field plate.
The device according to claim 1, wherein said device comprises at least one of a gallium nitride (GaN) transistor, a metal oxide semiconductor field effect transistor (MOS-FET), and a metal insulator semiconductor high electron mobility transistor (MIS-HEMT).
The device according to claim 1, wherein said device comprises a Nitrogen polar (n-polar) or Gallium polar (Ga-polar) device structure.
The device according to claim 1, wherein said field plate comprises a source connected field plate.
The device according to claim 1, wherein said device comprises a high electron mobility transistor (HEMT) hav-ing a source connected field plate.
The device according to claim 1, wherein said field plate comprises multiple fingers.
The device according to claim 1, wherein: said first passivation layer comprises an inorganic dielec-tric layer; said second passivation layer comprises an inorganic dielectric layer or an organic dielectric layer; and said field plate is embedded between said first passivation layer and said second passivation layer.
The device according to claim 1, wherein said field plate and said cap portion of said T-shaped gate contact have the same thickness.
The device according to claim 1, wherein said field plate has a first thickness, said cap portion of said T-shaped gate contact has a second thickness, and the first thickness is smaller than the second thickness.
The device according to claim 1, wherein said field plate has a first thickness, said cap portion of said T-shaped gate contact has a second thickness, and the first thickness is greater than the second thickness.
The device according to claim 1, wherein: said cap portion of said T-shaped gate contact is formed on said first passivation layer; and said field plate is formed on said surface of said first passivation layer.
The device according to claim 1, wherein: said cap portion of said T-shaped gate contact is formed on said first passivation layer; and a portion or all of said field plate is embedded within a recess in said first passivation layer.
The device according to claim 1, wherein: said cap portion of said T-shaped gate contact is formed on said first passivation layer; and said field plate is disposed above and the bottom surface of the entire field plate is uniformly separated from said surface of said first passivation layer by a second distance ranging from about 0.05 µm to about 0.5 µm, and is completely embedded in said second passivation layer.
The device according to claim 1, wherein: said cap portion of said T-shaped gate contact is formed on said first passivation layer; and said field plate is disposed above and the bottom surface of the entire field plate is uniformly separated from said surface of said first passivation layer by a second distance ranging from about 0.05 µm to about 0.5 µm, and is partially embedded in said second passivation layer.
The device according to claim 1, wherein: said field plate is formed on said first passivation layer; said cap portion of said T-shaped gate contact is separated from said first passivation layer by a portion of said second passivation layer; and said column portion of said T-shaped gate contact extends through said portion of said second passivation layer and through said first passivation layer.
The device according to claim 1, wherein: said plurality of semiconductor layers include said barrier layer and said channel layer forming a heterojunction; said barrier layer comprises at least one of an aluminum gallium nitride (AlGaN) epi layer, an indium aluminum nitride (InAlN) epi layer, and an aluminum nitride (AlN) epi layer; said channel layer comprises a gallium nitride (GaN) epi layer; and said epi layers are grown on a substrate comprising at least one of silicon, silicon carbide (SiC), Sapphire, and Diamond.
A device comprising: 30 a semiconductor die including a plurality of semiconduc-tor layers disposed on an insulating substrate; a source contact and a drain contact electrically coupled to a channel formed in the semiconductor layers and defining an active area of the device; 35 a barrier layer formed on a channel layer of said semiconductor die within said active area of the device; a cap layer formed on said barrier layer of said semicon-ductor die within said active area of the device; a first passivation layer formed on a surface of said cap layer of said semiconductor die within said active area of the device; a T-shaped gate contact disposed within said active area of the device, wherein (i) said T-shaped gate contact is electrically separated from said channel and comprises 45 a column portion and a cap portion, (ii) said column portion extends from a bottom surface of said cap portion, through an opening in said first passivation layer, and contacts said surface of said cap layer of said semiconductor die, and (111) said bottom surface of said cap portion contacts a surface of said first passivation layer; a first source connected field plate formed on said first passivation layer within said active area of the device, wherein the entire first source connected field plate is laterally separated from a drain edge of said bottom surface of said cap portion of said T-shaped gate contact by a distance ranging from about 0.1 µm to about 1 µm, a bottom surface of the entire field plate is uniformly separated from said surface of said cap layer B₁ by at least said first passivation layer, and the entire first source connected field plate is non-overlapping of said cap portion of said T-shaped gate contact; a second passivation layer formed on said surface of said first passivation layer, upper surfaces of said cap por-tion of said T-shaped gate contact, and upper surfaces of said first source connected field plate; and a second source connected field plate disposed on said second passivation layer above said first source con-nected field plate and extending lateral toward said source contact such that said second source connected field plate overlaps said T-shaped gate contact.
A device comprising: a semiconductor die including a plurality of semiconduc-tor layers disposed on an insulating substrate; a source contact and a drain contact electrically coupled to a channel formed in the semiconductor layers and defining an active area of the device; a barrier layer formed on a channel layer of said semiconductor die within said active area of the device; a cap layer formed on said barrier layer of said semicon-ductor die within said active area of the device; a first passivation layer formed on a surface of said cap layer of said semiconductor die within said active area of the device; a T-shaped gate contact disposed within said active area of the device, wherein (i) said T-shaped gate contact is electrically separated from said channel and comprises a column portion and a cap portion, (ii) said column portion extends from a bottom surface of said cap portion, through an opening in said first passivation layer, and contacts said surface of said cap layer of said semiconductor die, and (111) said cap portion is formed on said first passivation layer; a second passivation layer covering said first passivation layer and said cap portion of said T-shaped gate con-tact; and a source connected field plate adjacent to and laterally separated from said cap portion of said T-shaped gate contact, wherein said source connected field plate has a first portion and a second portion, the first portion overlaps said cap portion of said T-shaped gate contact, the second portion has a bottom edge that is formed within a recess etched in at least one of said first passivation layer and said second passivation layer, the entire second portion is laterally separated from a drain edge of said bottom surface of said cap portion of said T-shaped gate contact by a distance ranging from about 0.1 µm to about 1 µm, and the entire second portion is non-overlapping of said cap portion of said T-shaped gate contact.
The device according to claim 18, wherein a vertical position of said bottom edge of said second portion of said source connected field plate is lower than said bottom surface of said cap portion of said T shaped gate contact.
The device according to claim 18, wherein said bottom edge of said second portion of said source connected field plate and said bottom surface of said cap portion of said T shaped gate contact are at the same level. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN HEMT with embedded non-overlapping source field plate
GaN HEMT with first and second source connected field plates
GaN HEMT with recessed source connected field plate having overlapping first portion and non-overlapping second portion
HEMT 100 (described embodiment)
Materials described outside the worked examples.
gallium nitride
GaN
barrier layer material
first passivation layer (inorganic dielectric)
cap layer
second passivation layer (inorganic or organic dielectric)
aluminum gallium nitride
AlGaN
indium aluminum nitride
InAlN
aluminum nitride
AlN
silicon
Si
silicon carbide
SiC
sapphire
diamond
nucleation layer
AlzGa₁-zN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 12 is a graph showing 2D TCAD simulations illus- trating an impact of embedded, non-overlapping source field plate in accordance with an example embodiment …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.1–1 µm | — |
Thickness | 50–500 nm | — |
Thickness | 10–1000 nm | — |
Thickness | 0.2–2 um | — |
Thickness | 0.5–2 µm | — |
Thickness | 0.05–0.5 µm | — |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 8
Related documents with shared materials, methods, properties, or citations.
NOVEL BUFFER LAYER STRUCTURE TO IMPROVE GAN SEMICONDUCTORS
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