Patent
US 11,776,815 B2ASYMMETRICAL PLUG TECHNIQUE FOR GAN DEVICES
Alexey Kudymov, LinLin Liu, Jamal Ramdani
Power Integrations, Inc., San Jose, CA (US)·Oct. 3, 2023·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,776,815 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1B is a cross-sectional side view of another example 50 semiconductor device which may use an asymmetrical plug interconnect structure, in accordance with …
FIG. 2 is a cross-sectional side view of an example semiconductor device with an asymmetric plug interconnect 55 structure, in accordance with an embodiment of …
FIG. 3A is a top down view of an example layout of a semiconductor device with an asymmetric plug interconnect structure and alternating via/plug layout, in …
FIG. 4 is a top down view of an example layout of a semiconductor device with an asymmetric plug interconnect B₂ structure and alternating via/plug layout, in …
FIG. 5 is a top down view of an example layout of a semiconductor device with an asymmetric plug interconnect structure and alternating via/plug layout, in …
FIG. 6 is an example process flow for fabricating a semiconductor device with an asymmetric plug interconnect structure, in accordance with an embodiment of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high-voltage field effect transistor (high-voltage FET), comprising: a first active layer including a first semiconductor material having a first bandgap; and 15 a second active layer including a second semiconductor material having a second bandgap; a gate dielectric disposed proximate to the second active layer, wherein the second active layer is disposed between the first active layer and the gate dielectric; and a plurality of contact regions of a contact footprint of a source region or a drain region of the high-voltage FET, each contact region including: a contact coupled to supply or withdraw charge from the high-voltage FET; a passivation layer disposed proximate to the contact and the gate dielectric, wherein at least part of the contact is disposed between the passivation layer and the second active layer; an interconnect extending through the passivation layer and coupled to the contact at a via footprint region, wherein a first portion of the interconnect is disposed on the passivation layer so that the passivation layer is disposed between the first portion of the intercon-nect and the second active layer; and a plurality of plugs coupled to the first portion of the interconnect, wherein, for individual contact regions, a location of the plurality of plugs with respect to their corre-sponding via footprint region alternates along a same contact footprint from one contact region to another contact region, wherein, in a vertical direction, the location of the plurality of plugs is orthogonally offset from their corresponding via footprint region.
The high-voltage FET of claim 1, wherein a location of the via footprint region and the location of the plurality of plugs alternate in different lateral directions.
The high-voltage FET of claim 1, wherein the first portion of the interconnect includes a wing structure dis-posed off of a center axis of the interconnect.
The high-voltage FET of claim 1, further comprising an interlayer dielectric disposed proximate to the interconnect, wherein the first portion of the interconnect is disposed between the interlayer dielectric and the passivation layer.
The high-voltage FET of claim 1, further comprising a layer of electrical charge formed proximate to the first active layer and the second active layer in response to a difference in bandgap energy between the first bandgap and the second bandgap.
The high-voltage FET of claim 1, wherein the passi-vation layer is disposed between the contact and the first portion of the interconnect, and wherein the first portion of the interconnect is substantially laterally coextensive with a first side of the contact.
The high-voltage FET of claim 1, wherein a second portion of the interconnect extends through the passivation layer, and the first portion of the interconnect is substantially coplanar with the passivation layer.
The high-voltage FET of claim 1, wherein the plural-ity of contact regions comprises: a first contact region included in the source region of the high-voltage FET, and a second contact region included in the drain region of the high-voltage FET, wherein a footprint of the second contact region is wider than a footprint of the first contact region.
A high-voltage field effect transistor (high-voltage FET), comprising: a first active layer including a first semiconductor material having a first bandgap; and a second active layer including a second semiconductor material having a second bandgap; a gate dielectric disposed proximate to the second active layer, wherein the second active layer is disposed between the first active layer and the gate dielectric; and a plurality of contact regions of a contact footprint of a source region or a drain region of the high-voltage FET, each contact region including: a contact coupled to supply or withdraw charge from the high-voltage FET; a passivation layer disposed proximate to the contact and the gate dielectric, wherein at least part of the contact is disposed between the passivation layer and the second active layer; interconnecting means extending through the passiva-tion layer and coupled to the contact at a via footprint region, wherein a first portion of the interconnecting means is disposed on the passivation layer so that the passivation layer is disposed between the first por-tion of the interconnecting means and the second active layer; and a plurality of plugs coupled to the first portion of the interconnecting means, wherein, for individual contact regions, a location of the plurality of plugs with respect to their corre-sponding via footprint region alternates along a same contact footprint from one contact region to another contact region, and wherein, in a vertical direction, the location of the plurality of plugs is orthogonally offset from their corresponding via footprint region.
The high-voltage FET of claim 15, wherein a location of the via footprint region and the location of the plurality of plugs alternate in different lateral directions.
The high-voltage FET of claim 15, wherein the first portion of the interconnecting means includes a wing struc-ture disposed off of a center axis of the interconnecting means.
The high-voltage FET of claim 15, wherein a second portion of the interconnecting means extends through the passivation layer, and the first portion of the interconnecting means is substantially coplanar with the passivation layer.
The high-voltage FET of claim 15, wherein center axes of individual plugs of the plurality of plugs are disposed away from a center axis of the via footprint region.
The high-voltage FET of claim 15, wherein the plurality of contact regions comprises: a first contact region included in the source region of the high-voltage FET, and a second contact region included in the drain region of the high-voltage FET, wherein a footprint of the second contact region is wider than a footprint of the first contact region.
Layer stacks claimed or described, ordered top of device to substrate.
high-voltage heterostructure field effect transistor (HFET/HEMT) with asymmetrical plug interconnect
Materials described outside the worked examples.
first semiconductor material (channel layer)
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 2–10 µm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 16
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,776,815 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1B is a cross-sectional side view of another example 50 semiconductor device which may use an asymmetrical plug interconnect structure, in accordance with …
FIG. 2 is a cross-sectional side view of an example semiconductor device with an asymmetric plug interconnect 55 structure, in accordance with an embodiment of …
FIG. 3A is a top down view of an example layout of a semiconductor device with an asymmetric plug interconnect structure and alternating via/plug layout, in …
FIG. 4 is a top down view of an example layout of a semiconductor device with an asymmetric plug interconnect B₂ structure and alternating via/plug layout, in …
FIG. 5 is a top down view of an example layout of a semiconductor device with an asymmetric plug interconnect structure and alternating via/plug layout, in …
FIG. 6 is an example process flow for fabricating a semiconductor device with an asymmetric plug interconnect structure, in accordance with an embodiment of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high-voltage field effect transistor (high-voltage FET), comprising: a first active layer including a first semiconductor material having a first bandgap; and 15 a second active layer including a second semiconductor material having a second bandgap; a gate dielectric disposed proximate to the second active layer, wherein the second active layer is disposed between the first active layer and the gate dielectric; and a plurality of contact regions of a contact footprint of a source region or a drain region of the high-voltage FET, each contact region including: a contact coupled to supply or withdraw charge from the high-voltage FET; a passivation layer disposed proximate to the contact and the gate dielectric, wherein at least part of the contact is disposed between the passivation layer and the second active layer; an interconnect extending through the passivation layer and coupled to the contact at a via footprint region, wherein a first portion of the interconnect is disposed on the passivation layer so that the passivation layer is disposed between the first portion of the intercon-nect and the second active layer; and a plurality of plugs coupled to the first portion of the interconnect, wherein, for individual contact regions, a location of the plurality of plugs with respect to their corre-sponding via footprint region alternates along a same contact footprint from one contact region to another contact region, wherein, in a vertical direction, the location of the plurality of plugs is orthogonally offset from their corresponding via footprint region.
The high-voltage FET of claim 1, wherein a location of the via footprint region and the location of the plurality of plugs alternate in different lateral directions.
The high-voltage FET of claim 1, wherein the first portion of the interconnect includes a wing structure dis-posed off of a center axis of the interconnect.
The high-voltage FET of claim 1, further comprising an interlayer dielectric disposed proximate to the interconnect, wherein the first portion of the interconnect is disposed between the interlayer dielectric and the passivation layer.
The high-voltage FET of claim 1, further comprising a layer of electrical charge formed proximate to the first active layer and the second active layer in response to a difference in bandgap energy between the first bandgap and the second bandgap.
The high-voltage FET of claim 1, wherein the passi-vation layer is disposed between the contact and the first portion of the interconnect, and wherein the first portion of the interconnect is substantially laterally coextensive with a first side of the contact.
The high-voltage FET of claim 1, wherein a second portion of the interconnect extends through the passivation layer, and the first portion of the interconnect is substantially coplanar with the passivation layer.
The high-voltage FET of claim 1, wherein the plural-ity of contact regions comprises: a first contact region included in the source region of the high-voltage FET, and a second contact region included in the drain region of the high-voltage FET, wherein a footprint of the second contact region is wider than a footprint of the first contact region.
A high-voltage field effect transistor (high-voltage FET), comprising: a first active layer including a first semiconductor material having a first bandgap; and a second active layer including a second semiconductor material having a second bandgap; a gate dielectric disposed proximate to the second active layer, wherein the second active layer is disposed between the first active layer and the gate dielectric; and a plurality of contact regions of a contact footprint of a source region or a drain region of the high-voltage FET, each contact region including: a contact coupled to supply or withdraw charge from the high-voltage FET; a passivation layer disposed proximate to the contact and the gate dielectric, wherein at least part of the contact is disposed between the passivation layer and the second active layer; interconnecting means extending through the passiva-tion layer and coupled to the contact at a via footprint region, wherein a first portion of the interconnecting means is disposed on the passivation layer so that the passivation layer is disposed between the first por-tion of the interconnecting means and the second active layer; and a plurality of plugs coupled to the first portion of the interconnecting means, wherein, for individual contact regions, a location of the plurality of plugs with respect to their corre-sponding via footprint region alternates along a same contact footprint from one contact region to another contact region, and wherein, in a vertical direction, the location of the plurality of plugs is orthogonally offset from their corresponding via footprint region.
The high-voltage FET of claim 15, wherein a location of the via footprint region and the location of the plurality of plugs alternate in different lateral directions.
The high-voltage FET of claim 15, wherein the first portion of the interconnecting means includes a wing struc-ture disposed off of a center axis of the interconnecting means.
The high-voltage FET of claim 15, wherein a second portion of the interconnecting means extends through the passivation layer, and the first portion of the interconnecting means is substantially coplanar with the passivation layer.
The high-voltage FET of claim 15, wherein center axes of individual plugs of the plurality of plugs are disposed away from a center axis of the via footprint region.
The high-voltage FET of claim 15, wherein the plurality of contact regions comprises: a first contact region included in the source region of the high-voltage FET, and a second contact region included in the drain region of the high-voltage FET, wherein a footprint of the second contact region is wider than a footprint of the first contact region.
Layer stacks claimed or described, ordered top of device to substrate.
high-voltage heterostructure field effect transistor (HFET/HEMT) with asymmetrical plug interconnect
Materials described outside the worked examples.
first semiconductor material (channel layer)
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 2–10 µm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 16
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,776,815 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1B is a cross-sectional side view of another example 50 semiconductor device which may use an asymmetrical plug interconnect structure, in accordance with …
FIG. 2 is a cross-sectional side view of an example semiconductor device with an asymmetric plug interconnect 55 structure, in accordance with an embodiment of …
FIG. 3A is a top down view of an example layout of a semiconductor device with an asymmetric plug interconnect structure and alternating via/plug layout, in …
FIG. 4 is a top down view of an example layout of a semiconductor device with an asymmetric plug interconnect B₂ structure and alternating via/plug layout, in …
FIG. 5 is a top down view of an example layout of a semiconductor device with an asymmetric plug interconnect structure and alternating via/plug layout, in …
FIG. 6 is an example process flow for fabricating a semiconductor device with an asymmetric plug interconnect structure, in accordance with an embodiment of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high-voltage field effect transistor (high-voltage FET), comprising: a first active layer including a first semiconductor material having a first bandgap; and 15 a second active layer including a second semiconductor material having a second bandgap; a gate dielectric disposed proximate to the second active layer, wherein the second active layer is disposed between the first active layer and the gate dielectric; and a plurality of contact regions of a contact footprint of a source region or a drain region of the high-voltage FET, each contact region including: a contact coupled to supply or withdraw charge from the high-voltage FET; a passivation layer disposed proximate to the contact and the gate dielectric, wherein at least part of the contact is disposed between the passivation layer and the second active layer; an interconnect extending through the passivation layer and coupled to the contact at a via footprint region, wherein a first portion of the interconnect is disposed on the passivation layer so that the passivation layer is disposed between the first portion of the intercon-nect and the second active layer; and a plurality of plugs coupled to the first portion of the interconnect, wherein, for individual contact regions, a location of the plurality of plugs with respect to their corre-sponding via footprint region alternates along a same contact footprint from one contact region to another contact region, wherein, in a vertical direction, the location of the plurality of plugs is orthogonally offset from their corresponding via footprint region.
The high-voltage FET of claim 1, wherein a location of the via footprint region and the location of the plurality of plugs alternate in different lateral directions.
The high-voltage FET of claim 1, wherein the first portion of the interconnect includes a wing structure dis-posed off of a center axis of the interconnect.
The high-voltage FET of claim 1, further comprising an interlayer dielectric disposed proximate to the interconnect, wherein the first portion of the interconnect is disposed between the interlayer dielectric and the passivation layer.
The high-voltage FET of claim 1, further comprising a layer of electrical charge formed proximate to the first active layer and the second active layer in response to a difference in bandgap energy between the first bandgap and the second bandgap.
The high-voltage FET of claim 1, wherein the passi-vation layer is disposed between the contact and the first portion of the interconnect, and wherein the first portion of the interconnect is substantially laterally coextensive with a first side of the contact.
The high-voltage FET of claim 1, wherein a second portion of the interconnect extends through the passivation layer, and the first portion of the interconnect is substantially coplanar with the passivation layer.
The high-voltage FET of claim 1, wherein the plural-ity of contact regions comprises: a first contact region included in the source region of the high-voltage FET, and a second contact region included in the drain region of the high-voltage FET, wherein a footprint of the second contact region is wider than a footprint of the first contact region.
A high-voltage field effect transistor (high-voltage FET), comprising: a first active layer including a first semiconductor material having a first bandgap; and a second active layer including a second semiconductor material having a second bandgap; a gate dielectric disposed proximate to the second active layer, wherein the second active layer is disposed between the first active layer and the gate dielectric; and a plurality of contact regions of a contact footprint of a source region or a drain region of the high-voltage FET, each contact region including: a contact coupled to supply or withdraw charge from the high-voltage FET; a passivation layer disposed proximate to the contact and the gate dielectric, wherein at least part of the contact is disposed between the passivation layer and the second active layer; interconnecting means extending through the passiva-tion layer and coupled to the contact at a via footprint region, wherein a first portion of the interconnecting means is disposed on the passivation layer so that the passivation layer is disposed between the first por-tion of the interconnecting means and the second active layer; and a plurality of plugs coupled to the first portion of the interconnecting means, wherein, for individual contact regions, a location of the plurality of plugs with respect to their corre-sponding via footprint region alternates along a same contact footprint from one contact region to another contact region, and wherein, in a vertical direction, the location of the plurality of plugs is orthogonally offset from their corresponding via footprint region.
The high-voltage FET of claim 15, wherein a location of the via footprint region and the location of the plurality of plugs alternate in different lateral directions.
The high-voltage FET of claim 15, wherein the first portion of the interconnecting means includes a wing struc-ture disposed off of a center axis of the interconnecting means.
The high-voltage FET of claim 15, wherein a second portion of the interconnecting means extends through the passivation layer, and the first portion of the interconnecting means is substantially coplanar with the passivation layer.
The high-voltage FET of claim 15, wherein center axes of individual plugs of the plurality of plugs are disposed away from a center axis of the via footprint region.
The high-voltage FET of claim 15, wherein the plurality of contact regions comprises: a first contact region included in the source region of the high-voltage FET, and a second contact region included in the drain region of the high-voltage FET, wherein a footprint of the second contact region is wider than a footprint of the first contact region.
Layer stacks claimed or described, ordered top of device to substrate.
high-voltage heterostructure field effect transistor (HFET/HEMT) with asymmetrical plug interconnect
Materials described outside the worked examples.
first semiconductor material (channel layer)
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 2–10 µm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 16
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,776,815 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1B is a cross-sectional side view of another example 50 semiconductor device which may use an asymmetrical plug interconnect structure, in accordance with …
FIG. 2 is a cross-sectional side view of an example semiconductor device with an asymmetric plug interconnect 55 structure, in accordance with an embodiment of …
FIG. 3A is a top down view of an example layout of a semiconductor device with an asymmetric plug interconnect structure and alternating via/plug layout, in …
FIG. 4 is a top down view of an example layout of a semiconductor device with an asymmetric plug interconnect B₂ structure and alternating via/plug layout, in …
FIG. 5 is a top down view of an example layout of a semiconductor device with an asymmetric plug interconnect structure and alternating via/plug layout, in …
FIG. 6 is an example process flow for fabricating a semiconductor device with an asymmetric plug interconnect structure, in accordance with an embodiment of the …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A high-voltage field effect transistor (high-voltage FET), comprising: a first active layer including a first semiconductor material having a first bandgap; and 15 a second active layer including a second semiconductor material having a second bandgap; a gate dielectric disposed proximate to the second active layer, wherein the second active layer is disposed between the first active layer and the gate dielectric; and a plurality of contact regions of a contact footprint of a source region or a drain region of the high-voltage FET, each contact region including: a contact coupled to supply or withdraw charge from the high-voltage FET; a passivation layer disposed proximate to the contact and the gate dielectric, wherein at least part of the contact is disposed between the passivation layer and the second active layer; an interconnect extending through the passivation layer and coupled to the contact at a via footprint region, wherein a first portion of the interconnect is disposed on the passivation layer so that the passivation layer is disposed between the first portion of the intercon-nect and the second active layer; and a plurality of plugs coupled to the first portion of the interconnect, wherein, for individual contact regions, a location of the plurality of plugs with respect to their corre-sponding via footprint region alternates along a same contact footprint from one contact region to another contact region, wherein, in a vertical direction, the location of the plurality of plugs is orthogonally offset from their corresponding via footprint region.
The high-voltage FET of claim 1, wherein a location of the via footprint region and the location of the plurality of plugs alternate in different lateral directions.
The high-voltage FET of claim 1, wherein the first portion of the interconnect includes a wing structure dis-posed off of a center axis of the interconnect.
The high-voltage FET of claim 1, further comprising an interlayer dielectric disposed proximate to the interconnect, wherein the first portion of the interconnect is disposed between the interlayer dielectric and the passivation layer.
The high-voltage FET of claim 1, further comprising a layer of electrical charge formed proximate to the first active layer and the second active layer in response to a difference in bandgap energy between the first bandgap and the second bandgap.
The high-voltage FET of claim 1, wherein the passi-vation layer is disposed between the contact and the first portion of the interconnect, and wherein the first portion of the interconnect is substantially laterally coextensive with a first side of the contact.
The high-voltage FET of claim 1, wherein a second portion of the interconnect extends through the passivation layer, and the first portion of the interconnect is substantially coplanar with the passivation layer.
The high-voltage FET of claim 1, wherein the plural-ity of contact regions comprises: a first contact region included in the source region of the high-voltage FET, and a second contact region included in the drain region of the high-voltage FET, wherein a footprint of the second contact region is wider than a footprint of the first contact region.
A high-voltage field effect transistor (high-voltage FET), comprising: a first active layer including a first semiconductor material having a first bandgap; and a second active layer including a second semiconductor material having a second bandgap; a gate dielectric disposed proximate to the second active layer, wherein the second active layer is disposed between the first active layer and the gate dielectric; and a plurality of contact regions of a contact footprint of a source region or a drain region of the high-voltage FET, each contact region including: a contact coupled to supply or withdraw charge from the high-voltage FET; a passivation layer disposed proximate to the contact and the gate dielectric, wherein at least part of the contact is disposed between the passivation layer and the second active layer; interconnecting means extending through the passiva-tion layer and coupled to the contact at a via footprint region, wherein a first portion of the interconnecting means is disposed on the passivation layer so that the passivation layer is disposed between the first por-tion of the interconnecting means and the second active layer; and a plurality of plugs coupled to the first portion of the interconnecting means, wherein, for individual contact regions, a location of the plurality of plugs with respect to their corre-sponding via footprint region alternates along a same contact footprint from one contact region to another contact region, and wherein, in a vertical direction, the location of the plurality of plugs is orthogonally offset from their corresponding via footprint region.
The high-voltage FET of claim 15, wherein a location of the via footprint region and the location of the plurality of plugs alternate in different lateral directions.
The high-voltage FET of claim 15, wherein the first portion of the interconnecting means includes a wing struc-ture disposed off of a center axis of the interconnecting means.
The high-voltage FET of claim 15, wherein a second portion of the interconnecting means extends through the passivation layer, and the first portion of the interconnecting means is substantially coplanar with the passivation layer.
The high-voltage FET of claim 15, wherein center axes of individual plugs of the plurality of plugs are disposed away from a center axis of the via footprint region.
The high-voltage FET of claim 15, wherein the plurality of contact regions comprises: a first contact region included in the source region of the high-voltage FET, and a second contact region included in the drain region of the high-voltage FET, wherein a footprint of the second contact region is wider than a footprint of the first contact region.
Layer stacks claimed or described, ordered top of device to substrate.
high-voltage heterostructure field effect transistor (HFET/HEMT) with asymmetrical plug interconnect
Materials described outside the worked examples.
first semiconductor material (channel layer)
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 2–10 µm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 16
Related documents with shared materials, methods, properties, or citations.
second semiconductor material (barrier/donor layer)
AlGaN
AlInN
AlInGaN
gate dielectric
silicon nitride
SiN
silicon nitride
Si₃N₄
interlayer dielectric
two-dimensional electron gas (2DEG)
substrate
sapphire
Al₂O₃
silicon
Si
silicon carbide
SiC
tungsten plug
W
| — |
Cited non-patent literature · 2
second semiconductor material (barrier/donor layer)
AlGaN
AlInN
AlInGaN
gate dielectric
silicon nitride
SiN
silicon nitride
Si₃N₄
interlayer dielectric
two-dimensional electron gas (2DEG)
substrate
sapphire
Al₂O₃
silicon
Si
silicon carbide
SiC
tungsten plug
W
| — |
Cited non-patent literature · 2
second semiconductor material (barrier/donor layer)
AlGaN
AlInN
AlInGaN
gate dielectric
silicon nitride
SiN
silicon nitride
Si₃N₄
interlayer dielectric
two-dimensional electron gas (2DEG)
substrate
sapphire
Al₂O₃
silicon
Si
silicon carbide
SiC
tungsten plug
W
| — |
Cited non-patent literature · 2
second semiconductor material (barrier/donor layer)
AlGaN
AlInN
AlInGaN
gate dielectric
silicon nitride
SiN
silicon nitride
Si₃N₄
interlayer dielectric
two-dimensional electron gas (2DEG)
substrate
sapphire
Al₂O₃
silicon
Si
silicon carbide
SiC
tungsten plug
W
| — |
Cited non-patent literature · 2