Patent
US 12,604,502 B2NANOCHANNEL GALLIUM NITRIDE-BASED DEVICE AND MANUFACTURING METHOD THEREOF
Jiejie Zhu, Xiaohua Ma, Yue Hao, Jingshu Guo
Xidian University, Xi’an (CN)·Apr. 14, 2026·US
Copyright © 2026 Matter42. All rights reserved.
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Atlas literature
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US 12,604,502 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1.
FIG. 2 illustrates a cross-sectional view of an A-A plane illustrated in
FIG. 3 illustrates a cross-sectional view of a B-B plane illustrated in
FIG. 4 illustrates a cross-sectional view of a C-C plane 10 illustrated in
FIG. 5 illustrates a cross-sectional view of a D-D plane illustrated in
FIGS. 6A-6L illustrate schematic process diagrams of a manufacturing method of the nanochannel GaN-based 15 device according to an embodiment of the disclosure.
FIG. 7 illustrates a top view corresponding to
FIGS. 65 6G-6H. Step S₅ specifically includes following steps S₅₁- S53. B₂ S51, a rectangular region between the source arrayed pattern region and the drain …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A nanochannel gallium nitride (GaN)-based device, comprising: a substrate layer (1), a nucleation layer (2), a buffer layer (3), a channel region (4), an insertion layer (5), a barrier layer (6), a cap layer (7), a first n+-doped material layer (8), a second n+-doped material layer (9), a source electrode (10), a drain electrode (11), and a gate elec-trode (12); wherein the substrate layer (1), the nucleation layer (2), the buffer layer (3), the channel region (4), the insertion layer (5), the barrier layer (6) and the cap layer (7) are sequentially stacked in that order; wherein the first n+-doped material layer (8) is disposed in a source electrode region, and penetrates through the cap layer (7), the barrier layer (6), and the insertion layer (5), a bottom of the first n+-doped material layer (8) is disposed under channels of the channel region (4), the first n+-doped material layer (8) comprises a first arrayed pattern edge (81) facing towards the drain electrode (11), and the source electrode (10) is disposed on the first n+-doped material layer (8); wherein the second n+-doped material layer (9) is dis-posed in a drain electrode region and penetrates through the cap layer (7), the barrier layer (6), and the insertion layer (5), a bottom of the second n+-doped material layer (9) is disposed under the channels of the channel region (4), the second n+-doped material layer (9) comprises a second arrayed pattern edge (91) facing towards the source electrode (10), and the drain elec-trode (11) is disposed on the second n+-doped material layer (9); wherein a part of the channel region (4), the insertion layer (5), the barrier layer (6) and the cap layer (7) B₂ together form an arrayed nanochannel structure (71) between the source electrode region and the drain electrode region, the first arrayed pattern edge (81) is interdigitated with an end of the arrayed nanochannel structure (71), and the second arrayed pattern edge (91) is interdigitated with another end of the arrayed nanochannel structure (71); and wherein the gate electrode (12) is disposed between the first n+-doped material layer (8) and the second n+-doped material layer (9), on the arrayed nanochan-nel structure (71) and in recesses (72) defined by the arrayed nanochannel structure (71), to form a three-dimensional gate-all-around structure.
The nanochannel GaN-based device as claimed in claim 1, wherein a material of the substrate layer (1) comprises one or more selected from the group consisting of sapphire, silicon carbide and silicon; and wherein a material of the barrier layer (6) comprises one or more selected from the group consisting of alumi-num nitride (AlN), indium aluminum nitride (InAlN), scandium aluminum nitride (ScAlN), and aluminum gallium nitride (AlGaN).
The nanochannel GaN-based device as claimed in claim 1, wherein a material of each of the first n+-doped material layer (8) and the second n+-doped material layer (9) comprises at least one of n+-GaN and n+-InGaN.
The nanochannel GaN-based device as claimed in claim 1, wherein the first arrayed pattern edge (81) com-prises a plurality of first rectangular structures (811), and the plurality of first rectangular structures (811) are disposed evenly along an edge of the first n+-doped material layer (8); and wherein the second arrayed pattern edge (91) comprises a plurality of second rectangular structures (911), and the plurality of second rectangular structures (911) are disposed evenly along an edge of the second n+-doped material layer (9).
The nanochannel GaN-based device as claimed in claim 1, wherein the arrayed nanochannel structure (71) comprises at least one nanochannel (73), and the at least one nanochannel (73) is disposed evenly along a gate width direction of the gate electrode (12).
Layer stacks claimed or described, ordered top of device to substrate.
nanochannel GaN-based HEMT with gate-all-around structure
Materials described outside the worked examples.
GaN channel region
GaN
nucleation layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–1500 nm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 5
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,604,502 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1.
FIG. 2 illustrates a cross-sectional view of an A-A plane illustrated in
FIG. 3 illustrates a cross-sectional view of a B-B plane illustrated in
FIG. 4 illustrates a cross-sectional view of a C-C plane 10 illustrated in
FIG. 5 illustrates a cross-sectional view of a D-D plane illustrated in
FIGS. 6A-6L illustrate schematic process diagrams of a manufacturing method of the nanochannel GaN-based 15 device according to an embodiment of the disclosure.
FIG. 7 illustrates a top view corresponding to
FIGS. 65 6G-6H. Step S₅ specifically includes following steps S₅₁- S53. B₂ S51, a rectangular region between the source arrayed pattern region and the drain …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A nanochannel gallium nitride (GaN)-based device, comprising: a substrate layer (1), a nucleation layer (2), a buffer layer (3), a channel region (4), an insertion layer (5), a barrier layer (6), a cap layer (7), a first n+-doped material layer (8), a second n+-doped material layer (9), a source electrode (10), a drain electrode (11), and a gate elec-trode (12); wherein the substrate layer (1), the nucleation layer (2), the buffer layer (3), the channel region (4), the insertion layer (5), the barrier layer (6) and the cap layer (7) are sequentially stacked in that order; wherein the first n+-doped material layer (8) is disposed in a source electrode region, and penetrates through the cap layer (7), the barrier layer (6), and the insertion layer (5), a bottom of the first n+-doped material layer (8) is disposed under channels of the channel region (4), the first n+-doped material layer (8) comprises a first arrayed pattern edge (81) facing towards the drain electrode (11), and the source electrode (10) is disposed on the first n+-doped material layer (8); wherein the second n+-doped material layer (9) is dis-posed in a drain electrode region and penetrates through the cap layer (7), the barrier layer (6), and the insertion layer (5), a bottom of the second n+-doped material layer (9) is disposed under the channels of the channel region (4), the second n+-doped material layer (9) comprises a second arrayed pattern edge (91) facing towards the source electrode (10), and the drain elec-trode (11) is disposed on the second n+-doped material layer (9); wherein a part of the channel region (4), the insertion layer (5), the barrier layer (6) and the cap layer (7) B₂ together form an arrayed nanochannel structure (71) between the source electrode region and the drain electrode region, the first arrayed pattern edge (81) is interdigitated with an end of the arrayed nanochannel structure (71), and the second arrayed pattern edge (91) is interdigitated with another end of the arrayed nanochannel structure (71); and wherein the gate electrode (12) is disposed between the first n+-doped material layer (8) and the second n+-doped material layer (9), on the arrayed nanochan-nel structure (71) and in recesses (72) defined by the arrayed nanochannel structure (71), to form a three-dimensional gate-all-around structure.
The nanochannel GaN-based device as claimed in claim 1, wherein a material of the substrate layer (1) comprises one or more selected from the group consisting of sapphire, silicon carbide and silicon; and wherein a material of the barrier layer (6) comprises one or more selected from the group consisting of alumi-num nitride (AlN), indium aluminum nitride (InAlN), scandium aluminum nitride (ScAlN), and aluminum gallium nitride (AlGaN).
The nanochannel GaN-based device as claimed in claim 1, wherein a material of each of the first n+-doped material layer (8) and the second n+-doped material layer (9) comprises at least one of n+-GaN and n+-InGaN.
The nanochannel GaN-based device as claimed in claim 1, wherein the first arrayed pattern edge (81) com-prises a plurality of first rectangular structures (811), and the plurality of first rectangular structures (811) are disposed evenly along an edge of the first n+-doped material layer (8); and wherein the second arrayed pattern edge (91) comprises a plurality of second rectangular structures (911), and the plurality of second rectangular structures (911) are disposed evenly along an edge of the second n+-doped material layer (9).
The nanochannel GaN-based device as claimed in claim 1, wherein the arrayed nanochannel structure (71) comprises at least one nanochannel (73), and the at least one nanochannel (73) is disposed evenly along a gate width direction of the gate electrode (12).
Layer stacks claimed or described, ordered top of device to substrate.
nanochannel GaN-based HEMT with gate-all-around structure
Materials described outside the worked examples.
GaN channel region
GaN
nucleation layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–1500 nm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 5
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,604,502 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1.
FIG. 2 illustrates a cross-sectional view of an A-A plane illustrated in
FIG. 3 illustrates a cross-sectional view of a B-B plane illustrated in
FIG. 4 illustrates a cross-sectional view of a C-C plane 10 illustrated in
FIG. 5 illustrates a cross-sectional view of a D-D plane illustrated in
FIGS. 6A-6L illustrate schematic process diagrams of a manufacturing method of the nanochannel GaN-based 15 device according to an embodiment of the disclosure.
FIG. 7 illustrates a top view corresponding to
FIGS. 65 6G-6H. Step S₅ specifically includes following steps S₅₁- S53. B₂ S51, a rectangular region between the source arrayed pattern region and the drain …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A nanochannel gallium nitride (GaN)-based device, comprising: a substrate layer (1), a nucleation layer (2), a buffer layer (3), a channel region (4), an insertion layer (5), a barrier layer (6), a cap layer (7), a first n+-doped material layer (8), a second n+-doped material layer (9), a source electrode (10), a drain electrode (11), and a gate elec-trode (12); wherein the substrate layer (1), the nucleation layer (2), the buffer layer (3), the channel region (4), the insertion layer (5), the barrier layer (6) and the cap layer (7) are sequentially stacked in that order; wherein the first n+-doped material layer (8) is disposed in a source electrode region, and penetrates through the cap layer (7), the barrier layer (6), and the insertion layer (5), a bottom of the first n+-doped material layer (8) is disposed under channels of the channel region (4), the first n+-doped material layer (8) comprises a first arrayed pattern edge (81) facing towards the drain electrode (11), and the source electrode (10) is disposed on the first n+-doped material layer (8); wherein the second n+-doped material layer (9) is dis-posed in a drain electrode region and penetrates through the cap layer (7), the barrier layer (6), and the insertion layer (5), a bottom of the second n+-doped material layer (9) is disposed under the channels of the channel region (4), the second n+-doped material layer (9) comprises a second arrayed pattern edge (91) facing towards the source electrode (10), and the drain elec-trode (11) is disposed on the second n+-doped material layer (9); wherein a part of the channel region (4), the insertion layer (5), the barrier layer (6) and the cap layer (7) B₂ together form an arrayed nanochannel structure (71) between the source electrode region and the drain electrode region, the first arrayed pattern edge (81) is interdigitated with an end of the arrayed nanochannel structure (71), and the second arrayed pattern edge (91) is interdigitated with another end of the arrayed nanochannel structure (71); and wherein the gate electrode (12) is disposed between the first n+-doped material layer (8) and the second n+-doped material layer (9), on the arrayed nanochan-nel structure (71) and in recesses (72) defined by the arrayed nanochannel structure (71), to form a three-dimensional gate-all-around structure.
The nanochannel GaN-based device as claimed in claim 1, wherein a material of the substrate layer (1) comprises one or more selected from the group consisting of sapphire, silicon carbide and silicon; and wherein a material of the barrier layer (6) comprises one or more selected from the group consisting of alumi-num nitride (AlN), indium aluminum nitride (InAlN), scandium aluminum nitride (ScAlN), and aluminum gallium nitride (AlGaN).
The nanochannel GaN-based device as claimed in claim 1, wherein a material of each of the first n+-doped material layer (8) and the second n+-doped material layer (9) comprises at least one of n+-GaN and n+-InGaN.
The nanochannel GaN-based device as claimed in claim 1, wherein the first arrayed pattern edge (81) com-prises a plurality of first rectangular structures (811), and the plurality of first rectangular structures (811) are disposed evenly along an edge of the first n+-doped material layer (8); and wherein the second arrayed pattern edge (91) comprises a plurality of second rectangular structures (911), and the plurality of second rectangular structures (911) are disposed evenly along an edge of the second n+-doped material layer (9).
The nanochannel GaN-based device as claimed in claim 1, wherein the arrayed nanochannel structure (71) comprises at least one nanochannel (73), and the at least one nanochannel (73) is disposed evenly along a gate width direction of the gate electrode (12).
Layer stacks claimed or described, ordered top of device to substrate.
nanochannel GaN-based HEMT with gate-all-around structure
Materials described outside the worked examples.
GaN channel region
GaN
nucleation layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–1500 nm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 5
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,604,502 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1.
FIG. 2 illustrates a cross-sectional view of an A-A plane illustrated in
FIG. 3 illustrates a cross-sectional view of a B-B plane illustrated in
FIG. 4 illustrates a cross-sectional view of a C-C plane 10 illustrated in
FIG. 5 illustrates a cross-sectional view of a D-D plane illustrated in
FIGS. 6A-6L illustrate schematic process diagrams of a manufacturing method of the nanochannel GaN-based 15 device according to an embodiment of the disclosure.
FIG. 7 illustrates a top view corresponding to
FIGS. 65 6G-6H. Step S₅ specifically includes following steps S₅₁- S53. B₂ S51, a rectangular region between the source arrayed pattern region and the drain …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A nanochannel gallium nitride (GaN)-based device, comprising: a substrate layer (1), a nucleation layer (2), a buffer layer (3), a channel region (4), an insertion layer (5), a barrier layer (6), a cap layer (7), a first n+-doped material layer (8), a second n+-doped material layer (9), a source electrode (10), a drain electrode (11), and a gate elec-trode (12); wherein the substrate layer (1), the nucleation layer (2), the buffer layer (3), the channel region (4), the insertion layer (5), the barrier layer (6) and the cap layer (7) are sequentially stacked in that order; wherein the first n+-doped material layer (8) is disposed in a source electrode region, and penetrates through the cap layer (7), the barrier layer (6), and the insertion layer (5), a bottom of the first n+-doped material layer (8) is disposed under channels of the channel region (4), the first n+-doped material layer (8) comprises a first arrayed pattern edge (81) facing towards the drain electrode (11), and the source electrode (10) is disposed on the first n+-doped material layer (8); wherein the second n+-doped material layer (9) is dis-posed in a drain electrode region and penetrates through the cap layer (7), the barrier layer (6), and the insertion layer (5), a bottom of the second n+-doped material layer (9) is disposed under the channels of the channel region (4), the second n+-doped material layer (9) comprises a second arrayed pattern edge (91) facing towards the source electrode (10), and the drain elec-trode (11) is disposed on the second n+-doped material layer (9); wherein a part of the channel region (4), the insertion layer (5), the barrier layer (6) and the cap layer (7) B₂ together form an arrayed nanochannel structure (71) between the source electrode region and the drain electrode region, the first arrayed pattern edge (81) is interdigitated with an end of the arrayed nanochannel structure (71), and the second arrayed pattern edge (91) is interdigitated with another end of the arrayed nanochannel structure (71); and wherein the gate electrode (12) is disposed between the first n+-doped material layer (8) and the second n+-doped material layer (9), on the arrayed nanochan-nel structure (71) and in recesses (72) defined by the arrayed nanochannel structure (71), to form a three-dimensional gate-all-around structure.
The nanochannel GaN-based device as claimed in claim 1, wherein a material of the substrate layer (1) comprises one or more selected from the group consisting of sapphire, silicon carbide and silicon; and wherein a material of the barrier layer (6) comprises one or more selected from the group consisting of alumi-num nitride (AlN), indium aluminum nitride (InAlN), scandium aluminum nitride (ScAlN), and aluminum gallium nitride (AlGaN).
The nanochannel GaN-based device as claimed in claim 1, wherein a material of each of the first n+-doped material layer (8) and the second n+-doped material layer (9) comprises at least one of n+-GaN and n+-InGaN.
The nanochannel GaN-based device as claimed in claim 1, wherein the first arrayed pattern edge (81) com-prises a plurality of first rectangular structures (811), and the plurality of first rectangular structures (811) are disposed evenly along an edge of the first n+-doped material layer (8); and wherein the second arrayed pattern edge (91) comprises a plurality of second rectangular structures (911), and the plurality of second rectangular structures (911) are disposed evenly along an edge of the second n+-doped material layer (9).
The nanochannel GaN-based device as claimed in claim 1, wherein the arrayed nanochannel structure (71) comprises at least one nanochannel (73), and the at least one nanochannel (73) is disposed evenly along a gate width direction of the gate electrode (12).
Layer stacks claimed or described, ordered top of device to substrate.
nanochannel GaN-based HEMT with gate-all-around structure
Materials described outside the worked examples.
GaN channel region
GaN
nucleation layer
Additional fabrication and treatment steps described in the patent.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 20–1500 nm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 5
Related documents with shared materials, methods, properties, or citations.
buffer layer
insertion layer
cap layer
sapphire
silicon carbide
SiC
silicon
Si
aluminum nitride
AlN
indium aluminum nitride
InAlN
scandium aluminum nitride
ScAlN
aluminum gallium nitride
AlGaN
n+-GaN
n+-InGaN
silica mask layer
SiO₂
| 20–2000 nm |
| — |
Thickness | 40–400 nm | — |
Cited non-patent literature · 1
buffer layer
insertion layer
cap layer
sapphire
silicon carbide
SiC
silicon
Si
aluminum nitride
AlN
indium aluminum nitride
InAlN
scandium aluminum nitride
ScAlN
aluminum gallium nitride
AlGaN
n+-GaN
n+-InGaN
silica mask layer
SiO₂
| 20–2000 nm |
| — |
Thickness | 40–400 nm | — |
Cited non-patent literature · 1
buffer layer
insertion layer
cap layer
sapphire
silicon carbide
SiC
silicon
Si
aluminum nitride
AlN
indium aluminum nitride
InAlN
scandium aluminum nitride
ScAlN
aluminum gallium nitride
AlGaN
n+-GaN
n+-InGaN
silica mask layer
SiO₂
| 20–2000 nm |
| — |
Thickness | 40–400 nm | — |
Cited non-patent literature · 1
buffer layer
insertion layer
cap layer
sapphire
silicon carbide
SiC
silicon
Si
aluminum nitride
AlN
indium aluminum nitride
InAlN
scandium aluminum nitride
ScAlN
aluminum gallium nitride
AlGaN
n+-GaN
n+-InGaN
silica mask layer
SiO₂
| 20–2000 nm |
| — |
Thickness | 40–400 nm | — |
Cited non-patent literature · 1