Patent
Atlas literature
Patent
US 12,451,398 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a block diagram of a GaN-based inte- 40 grated circuit, in accordance with various embodiments.
FIG. 2 illustrates an example arrangement of a GaN-based device and plural test structures of the GaN-based integrated circuit of
FIG. 3 illustrates a cross-sectional view of a GaN-based 45 device, in accordance with various embodiments.
FIGS. 4, 5, 6, 7, 8, and 9 illustrate various arrangements of a test structure emulating a GaN-based device, respec- tively, in accordance with various …
FIG. 5, the first conductive 65 pattern includes a base portion 510 and a plural number of protruding portions 512 extending away from the base B₂ portion 510, …
FIG. 6, the first conductive pattern includes a base portion 610 and a plural number of circular portions, 612A, 612B, and 612C, coupled to the base portion …
FIG. 7). In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a transistor comprising: a plurality …
FIG. 8, the first conductive pattern includes a base portion 810 and the second conduc- tive pattern includes a base portion 820, wherein the base portion 810 …
FIG. 9, the first conductive 15 pattern includes a base portion 910 and the second conduc- tive pattern includes a base portion 920, wherein the base portion …
FIG. 10 illustrates a block diagram of a test system for 50 identifying defects of a GaN-based device, in accordance with various embodiments.
FIG. 11 illustrates a circuit diagram of a high-voltage charge pump, in accordance with various embodiments.
FIG. 12 illustrates a circuit diagram of a high-voltage 55 clock generator operatively coupled to the charge pump of
FIG. 13 illustrates a cross-sectional view of a diode- connected transistor implemented by the charge pump of
FIG. 14 illustrates an example flow chart of a method for identifying defects of a GaN-based device, in accordance with various embodiments.
FIG. 15 illustrates an example flow chart of a method for fabricating a GaN-based device and its one or more corre- 65 sponding test structures, in accordance …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a transistor comprising: a plurality of layers, wherein each of the plurality of layers has at least one Group III-V compound mate-rial; 30 a gate electrode operatively coupled to at least one of the plurality of layers; a source electrode disposed on a first side of the gate electrode; a drain electrode disposed on a second side of the gate electrode; a field plate disposed between the gate electrode and the drain electrode; and a plurality of conductive lines disposed above the gate electrode, the source electrode, and the drain elec-trode; and a plurality of test structures, wherein each of the test structures, including a first metal pattern and a second metal pattern, emulates at least one of the gate elec-trode, the source electrode, the drain electrode, the field plate, or at least one of the plurality of conductive lines.
The semiconductor device of claim 1, wherein the plurality of test structures are each disposed immediately next to the transistor.
The semiconductor device of claim 1, wherein the first metal pattern includes a first base portion and a plurality of first protruding portions extending away from the first base portion, and the second metal pattern includes a second base portion and a plurality of second protruding portions extend-ing away from the second base portion.
The semiconductor device of claim 1, wherein the first metal pattern includes a first plate and the second metal pattern includes a second plate, and wherein at least a first portion of the first plate and at least a second portion of the second plate are vertically overlapped with each other.
The semiconductor device of claim 1, wherein the transistor occupies a first area on a substrate and each of the plurality of test structures occupies a second area on the substrate, and wherein a ratio of the second area to the first area is equal to or less than 10%.
The semiconductor device of claim 1, wherein each of the test structures is configured to detect whether a defect is present in the transistor based on whether the corresponding first metal pattern and the corresponding second metal pattern form a short circuit.
The semiconductor device of claim 1, further compris-ing: a charge pump connected to one of the corresponding first metal pattern or the corresponding second metal pattern of at least a first one of the test structures; wherein the charge pump is formed of at least one Group III-V compound material and configured to provide the connected first metal pattern or the connected second metal pattern with a voltage equal to or greater than 650 volts (V).
A semiconductor device, comprising: a transistor comprising: a plurality of layers, wherein each of the plurality of layers has at least one Group III-V compound mate-rial; a gate electrode operatively coupled to at least one of the plurality of layers; a source electrode disposed on a first side of the gate electrode; a drain electrode disposed on a second side of the gate electrode; a field plate disposed between the gate electrode and the drain electrode; and a plurality of conductive lines disposed above the gate electrode, the source electrode, and the drain elec-trode; and a plurality of test structures, wherein each of the test structures is configured to emulate at least one of the gate electrode, the source electrode, the drain electrode, the field plate, or at least one of the plurality of conductive lines.
The semiconductor device of claim 11, wherein the plurality of test structures are each disposed immediately next to the transistor.
The semiconductor device of claim 11, wherein each of the test structures includes a first metal pattern and a second metal pattern, wherein the first metal pattern includes a first base portion and a plurality of first protruding portions extending away from the first base portion, and the second metal pattern includes a second base portion and a plurality of second protruding portions extending away from the second base portion.
The semiconductor device of claim 11, wherein the transistor occupies a first area on a substrate and each of the plurality of test structures occupies a second area on the substrate, and wherein a ratio of the second area to the first area is equal to or less than 10%.
A semiconductor device, comprising: a transistor comprising: a plurality of layers, wherein each of the plurality of layers has at least one Group III-V compound mate-rial; a gate electrode operatively coupled to at least one of the plurality of layers; a source electrode disposed on a first side of the gate electrode; a drain electrode disposed on a second side of the gate electrode; a field plate disposed between the gate electrode and the drain electrode; and 15 a plurality of conductive lines disposed above the gate electrode, the source electrode, and the drain elec-trode; a plurality of test structures, wherein each of the test structures, each including a first metal pattern and a 20 second metal pattern, is configured to emulate at least B₂ one of the gate electrode, the source electrode, the drain electrode, the field plate, or at least one of the plurality of conductive lines; and a charge pump connected to one of the corresponding first metal pattern or the corresponding second metal pattern of at least one of the test structures.
The semiconductor device of claim 17, wherein the charge pump is formed of at least one Group III-V com-pound material and configured to provide the connected first metal pattern or the connected second metal pattern with a voltage equal to or greater than 650 volts (V).
The semiconductor device of claim 17, wherein the plurality of test structures are each disposed immediately next to the transistor.
The semiconductor device of claim 17, wherein the first metal pattern includes a first base portion and a plurality of first protruding portions extending away from the first base portion, and the second metal pattern includes a second base portion and a plurality of second protruding portions extending away from the second base portion. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based transistor with test structures
Materials described outside the worked examples.
Group III-V compound material
gallium nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7). In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a transistor comprising: a plurality …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.25–6 µm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 18
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Patent
Atlas literature
Patent
US 12,451,398 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a block diagram of a GaN-based inte- 40 grated circuit, in accordance with various embodiments.
FIG. 2 illustrates an example arrangement of a GaN-based device and plural test structures of the GaN-based integrated circuit of
FIG. 3 illustrates a cross-sectional view of a GaN-based 45 device, in accordance with various embodiments.
FIGS. 4, 5, 6, 7, 8, and 9 illustrate various arrangements of a test structure emulating a GaN-based device, respec- tively, in accordance with various …
FIG. 5, the first conductive 65 pattern includes a base portion 510 and a plural number of protruding portions 512 extending away from the base B₂ portion 510, …
FIG. 6, the first conductive pattern includes a base portion 610 and a plural number of circular portions, 612A, 612B, and 612C, coupled to the base portion …
FIG. 7). In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a transistor comprising: a plurality …
FIG. 8, the first conductive pattern includes a base portion 810 and the second conduc- tive pattern includes a base portion 820, wherein the base portion 810 …
FIG. 9, the first conductive 15 pattern includes a base portion 910 and the second conduc- tive pattern includes a base portion 920, wherein the base portion …
FIG. 10 illustrates a block diagram of a test system for 50 identifying defects of a GaN-based device, in accordance with various embodiments.
FIG. 11 illustrates a circuit diagram of a high-voltage charge pump, in accordance with various embodiments.
FIG. 12 illustrates a circuit diagram of a high-voltage 55 clock generator operatively coupled to the charge pump of
FIG. 13 illustrates a cross-sectional view of a diode- connected transistor implemented by the charge pump of
FIG. 14 illustrates an example flow chart of a method for identifying defects of a GaN-based device, in accordance with various embodiments.
FIG. 15 illustrates an example flow chart of a method for fabricating a GaN-based device and its one or more corre- 65 sponding test structures, in accordance …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a transistor comprising: a plurality of layers, wherein each of the plurality of layers has at least one Group III-V compound mate-rial; 30 a gate electrode operatively coupled to at least one of the plurality of layers; a source electrode disposed on a first side of the gate electrode; a drain electrode disposed on a second side of the gate electrode; a field plate disposed between the gate electrode and the drain electrode; and a plurality of conductive lines disposed above the gate electrode, the source electrode, and the drain elec-trode; and a plurality of test structures, wherein each of the test structures, including a first metal pattern and a second metal pattern, emulates at least one of the gate elec-trode, the source electrode, the drain electrode, the field plate, or at least one of the plurality of conductive lines.
The semiconductor device of claim 1, wherein the plurality of test structures are each disposed immediately next to the transistor.
The semiconductor device of claim 1, wherein the first metal pattern includes a first base portion and a plurality of first protruding portions extending away from the first base portion, and the second metal pattern includes a second base portion and a plurality of second protruding portions extend-ing away from the second base portion.
The semiconductor device of claim 1, wherein the first metal pattern includes a first plate and the second metal pattern includes a second plate, and wherein at least a first portion of the first plate and at least a second portion of the second plate are vertically overlapped with each other.
The semiconductor device of claim 1, wherein the transistor occupies a first area on a substrate and each of the plurality of test structures occupies a second area on the substrate, and wherein a ratio of the second area to the first area is equal to or less than 10%.
The semiconductor device of claim 1, wherein each of the test structures is configured to detect whether a defect is present in the transistor based on whether the corresponding first metal pattern and the corresponding second metal pattern form a short circuit.
The semiconductor device of claim 1, further compris-ing: a charge pump connected to one of the corresponding first metal pattern or the corresponding second metal pattern of at least a first one of the test structures; wherein the charge pump is formed of at least one Group III-V compound material and configured to provide the connected first metal pattern or the connected second metal pattern with a voltage equal to or greater than 650 volts (V).
A semiconductor device, comprising: a transistor comprising: a plurality of layers, wherein each of the plurality of layers has at least one Group III-V compound mate-rial; a gate electrode operatively coupled to at least one of the plurality of layers; a source electrode disposed on a first side of the gate electrode; a drain electrode disposed on a second side of the gate electrode; a field plate disposed between the gate electrode and the drain electrode; and a plurality of conductive lines disposed above the gate electrode, the source electrode, and the drain elec-trode; and a plurality of test structures, wherein each of the test structures is configured to emulate at least one of the gate electrode, the source electrode, the drain electrode, the field plate, or at least one of the plurality of conductive lines.
The semiconductor device of claim 11, wherein the plurality of test structures are each disposed immediately next to the transistor.
The semiconductor device of claim 11, wherein each of the test structures includes a first metal pattern and a second metal pattern, wherein the first metal pattern includes a first base portion and a plurality of first protruding portions extending away from the first base portion, and the second metal pattern includes a second base portion and a plurality of second protruding portions extending away from the second base portion.
The semiconductor device of claim 11, wherein the transistor occupies a first area on a substrate and each of the plurality of test structures occupies a second area on the substrate, and wherein a ratio of the second area to the first area is equal to or less than 10%.
A semiconductor device, comprising: a transistor comprising: a plurality of layers, wherein each of the plurality of layers has at least one Group III-V compound mate-rial; a gate electrode operatively coupled to at least one of the plurality of layers; a source electrode disposed on a first side of the gate electrode; a drain electrode disposed on a second side of the gate electrode; a field plate disposed between the gate electrode and the drain electrode; and 15 a plurality of conductive lines disposed above the gate electrode, the source electrode, and the drain elec-trode; a plurality of test structures, wherein each of the test structures, each including a first metal pattern and a 20 second metal pattern, is configured to emulate at least B₂ one of the gate electrode, the source electrode, the drain electrode, the field plate, or at least one of the plurality of conductive lines; and a charge pump connected to one of the corresponding first metal pattern or the corresponding second metal pattern of at least one of the test structures.
The semiconductor device of claim 17, wherein the charge pump is formed of at least one Group III-V com-pound material and configured to provide the connected first metal pattern or the connected second metal pattern with a voltage equal to or greater than 650 volts (V).
The semiconductor device of claim 17, wherein the plurality of test structures are each disposed immediately next to the transistor.
The semiconductor device of claim 17, wherein the first metal pattern includes a first base portion and a plurality of first protruding portions extending away from the first base portion, and the second metal pattern includes a second base portion and a plurality of second protruding portions extending away from the second base portion. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based transistor with test structures
Materials described outside the worked examples.
Group III-V compound material
gallium nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7). In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a transistor comprising: a plurality …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.25–6 µm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 18
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,451,398 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a block diagram of a GaN-based inte- 40 grated circuit, in accordance with various embodiments.
FIG. 2 illustrates an example arrangement of a GaN-based device and plural test structures of the GaN-based integrated circuit of
FIG. 3 illustrates a cross-sectional view of a GaN-based 45 device, in accordance with various embodiments.
FIGS. 4, 5, 6, 7, 8, and 9 illustrate various arrangements of a test structure emulating a GaN-based device, respec- tively, in accordance with various …
FIG. 5, the first conductive 65 pattern includes a base portion 510 and a plural number of protruding portions 512 extending away from the base B₂ portion 510, …
FIG. 6, the first conductive pattern includes a base portion 610 and a plural number of circular portions, 612A, 612B, and 612C, coupled to the base portion …
FIG. 7). In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a transistor comprising: a plurality …
FIG. 8, the first conductive pattern includes a base portion 810 and the second conduc- tive pattern includes a base portion 820, wherein the base portion 810 …
FIG. 9, the first conductive 15 pattern includes a base portion 910 and the second conduc- tive pattern includes a base portion 920, wherein the base portion …
FIG. 10 illustrates a block diagram of a test system for 50 identifying defects of a GaN-based device, in accordance with various embodiments.
FIG. 11 illustrates a circuit diagram of a high-voltage charge pump, in accordance with various embodiments.
FIG. 12 illustrates a circuit diagram of a high-voltage 55 clock generator operatively coupled to the charge pump of
FIG. 13 illustrates a cross-sectional view of a diode- connected transistor implemented by the charge pump of
FIG. 14 illustrates an example flow chart of a method for identifying defects of a GaN-based device, in accordance with various embodiments.
FIG. 15 illustrates an example flow chart of a method for fabricating a GaN-based device and its one or more corre- 65 sponding test structures, in accordance …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a transistor comprising: a plurality of layers, wherein each of the plurality of layers has at least one Group III-V compound mate-rial; 30 a gate electrode operatively coupled to at least one of the plurality of layers; a source electrode disposed on a first side of the gate electrode; a drain electrode disposed on a second side of the gate electrode; a field plate disposed between the gate electrode and the drain electrode; and a plurality of conductive lines disposed above the gate electrode, the source electrode, and the drain elec-trode; and a plurality of test structures, wherein each of the test structures, including a first metal pattern and a second metal pattern, emulates at least one of the gate elec-trode, the source electrode, the drain electrode, the field plate, or at least one of the plurality of conductive lines.
The semiconductor device of claim 1, wherein the plurality of test structures are each disposed immediately next to the transistor.
The semiconductor device of claim 1, wherein the first metal pattern includes a first base portion and a plurality of first protruding portions extending away from the first base portion, and the second metal pattern includes a second base portion and a plurality of second protruding portions extend-ing away from the second base portion.
The semiconductor device of claim 1, wherein the first metal pattern includes a first plate and the second metal pattern includes a second plate, and wherein at least a first portion of the first plate and at least a second portion of the second plate are vertically overlapped with each other.
The semiconductor device of claim 1, wherein the transistor occupies a first area on a substrate and each of the plurality of test structures occupies a second area on the substrate, and wherein a ratio of the second area to the first area is equal to or less than 10%.
The semiconductor device of claim 1, wherein each of the test structures is configured to detect whether a defect is present in the transistor based on whether the corresponding first metal pattern and the corresponding second metal pattern form a short circuit.
The semiconductor device of claim 1, further compris-ing: a charge pump connected to one of the corresponding first metal pattern or the corresponding second metal pattern of at least a first one of the test structures; wherein the charge pump is formed of at least one Group III-V compound material and configured to provide the connected first metal pattern or the connected second metal pattern with a voltage equal to or greater than 650 volts (V).
A semiconductor device, comprising: a transistor comprising: a plurality of layers, wherein each of the plurality of layers has at least one Group III-V compound mate-rial; a gate electrode operatively coupled to at least one of the plurality of layers; a source electrode disposed on a first side of the gate electrode; a drain electrode disposed on a second side of the gate electrode; a field plate disposed between the gate electrode and the drain electrode; and a plurality of conductive lines disposed above the gate electrode, the source electrode, and the drain elec-trode; and a plurality of test structures, wherein each of the test structures is configured to emulate at least one of the gate electrode, the source electrode, the drain electrode, the field plate, or at least one of the plurality of conductive lines.
The semiconductor device of claim 11, wherein the plurality of test structures are each disposed immediately next to the transistor.
The semiconductor device of claim 11, wherein each of the test structures includes a first metal pattern and a second metal pattern, wherein the first metal pattern includes a first base portion and a plurality of first protruding portions extending away from the first base portion, and the second metal pattern includes a second base portion and a plurality of second protruding portions extending away from the second base portion.
The semiconductor device of claim 11, wherein the transistor occupies a first area on a substrate and each of the plurality of test structures occupies a second area on the substrate, and wherein a ratio of the second area to the first area is equal to or less than 10%.
A semiconductor device, comprising: a transistor comprising: a plurality of layers, wherein each of the plurality of layers has at least one Group III-V compound mate-rial; a gate electrode operatively coupled to at least one of the plurality of layers; a source electrode disposed on a first side of the gate electrode; a drain electrode disposed on a second side of the gate electrode; a field plate disposed between the gate electrode and the drain electrode; and 15 a plurality of conductive lines disposed above the gate electrode, the source electrode, and the drain elec-trode; a plurality of test structures, wherein each of the test structures, each including a first metal pattern and a 20 second metal pattern, is configured to emulate at least B₂ one of the gate electrode, the source electrode, the drain electrode, the field plate, or at least one of the plurality of conductive lines; and a charge pump connected to one of the corresponding first metal pattern or the corresponding second metal pattern of at least one of the test structures.
The semiconductor device of claim 17, wherein the charge pump is formed of at least one Group III-V com-pound material and configured to provide the connected first metal pattern or the connected second metal pattern with a voltage equal to or greater than 650 volts (V).
The semiconductor device of claim 17, wherein the plurality of test structures are each disposed immediately next to the transistor.
The semiconductor device of claim 17, wherein the first metal pattern includes a first base portion and a plurality of first protruding portions extending away from the first base portion, and the second metal pattern includes a second base portion and a plurality of second protruding portions extending away from the second base portion. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based transistor with test structures
Materials described outside the worked examples.
Group III-V compound material
gallium nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7). In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a transistor comprising: a plurality …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.25–6 µm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 18
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,451,398 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a block diagram of a GaN-based inte- 40 grated circuit, in accordance with various embodiments.
FIG. 2 illustrates an example arrangement of a GaN-based device and plural test structures of the GaN-based integrated circuit of
FIG. 3 illustrates a cross-sectional view of a GaN-based 45 device, in accordance with various embodiments.
FIGS. 4, 5, 6, 7, 8, and 9 illustrate various arrangements of a test structure emulating a GaN-based device, respec- tively, in accordance with various …
FIG. 5, the first conductive 65 pattern includes a base portion 510 and a plural number of protruding portions 512 extending away from the base B₂ portion 510, …
FIG. 6, the first conductive pattern includes a base portion 610 and a plural number of circular portions, 612A, 612B, and 612C, coupled to the base portion …
FIG. 7). In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a transistor comprising: a plurality …
FIG. 8, the first conductive pattern includes a base portion 810 and the second conduc- tive pattern includes a base portion 820, wherein the base portion 810 …
FIG. 9, the first conductive 15 pattern includes a base portion 910 and the second conduc- tive pattern includes a base portion 920, wherein the base portion …
FIG. 10 illustrates a block diagram of a test system for 50 identifying defects of a GaN-based device, in accordance with various embodiments.
FIG. 11 illustrates a circuit diagram of a high-voltage charge pump, in accordance with various embodiments.
FIG. 12 illustrates a circuit diagram of a high-voltage 55 clock generator operatively coupled to the charge pump of
FIG. 13 illustrates a cross-sectional view of a diode- connected transistor implemented by the charge pump of
FIG. 14 illustrates an example flow chart of a method for identifying defects of a GaN-based device, in accordance with various embodiments.
FIG. 15 illustrates an example flow chart of a method for fabricating a GaN-based device and its one or more corre- 65 sponding test structures, in accordance …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a transistor comprising: a plurality of layers, wherein each of the plurality of layers has at least one Group III-V compound mate-rial; 30 a gate electrode operatively coupled to at least one of the plurality of layers; a source electrode disposed on a first side of the gate electrode; a drain electrode disposed on a second side of the gate electrode; a field plate disposed between the gate electrode and the drain electrode; and a plurality of conductive lines disposed above the gate electrode, the source electrode, and the drain elec-trode; and a plurality of test structures, wherein each of the test structures, including a first metal pattern and a second metal pattern, emulates at least one of the gate elec-trode, the source electrode, the drain electrode, the field plate, or at least one of the plurality of conductive lines.
The semiconductor device of claim 1, wherein the plurality of test structures are each disposed immediately next to the transistor.
The semiconductor device of claim 1, wherein the first metal pattern includes a first base portion and a plurality of first protruding portions extending away from the first base portion, and the second metal pattern includes a second base portion and a plurality of second protruding portions extend-ing away from the second base portion.
The semiconductor device of claim 1, wherein the first metal pattern includes a first plate and the second metal pattern includes a second plate, and wherein at least a first portion of the first plate and at least a second portion of the second plate are vertically overlapped with each other.
The semiconductor device of claim 1, wherein the transistor occupies a first area on a substrate and each of the plurality of test structures occupies a second area on the substrate, and wherein a ratio of the second area to the first area is equal to or less than 10%.
The semiconductor device of claim 1, wherein each of the test structures is configured to detect whether a defect is present in the transistor based on whether the corresponding first metal pattern and the corresponding second metal pattern form a short circuit.
The semiconductor device of claim 1, further compris-ing: a charge pump connected to one of the corresponding first metal pattern or the corresponding second metal pattern of at least a first one of the test structures; wherein the charge pump is formed of at least one Group III-V compound material and configured to provide the connected first metal pattern or the connected second metal pattern with a voltage equal to or greater than 650 volts (V).
A semiconductor device, comprising: a transistor comprising: a plurality of layers, wherein each of the plurality of layers has at least one Group III-V compound mate-rial; a gate electrode operatively coupled to at least one of the plurality of layers; a source electrode disposed on a first side of the gate electrode; a drain electrode disposed on a second side of the gate electrode; a field plate disposed between the gate electrode and the drain electrode; and a plurality of conductive lines disposed above the gate electrode, the source electrode, and the drain elec-trode; and a plurality of test structures, wherein each of the test structures is configured to emulate at least one of the gate electrode, the source electrode, the drain electrode, the field plate, or at least one of the plurality of conductive lines.
The semiconductor device of claim 11, wherein the plurality of test structures are each disposed immediately next to the transistor.
The semiconductor device of claim 11, wherein each of the test structures includes a first metal pattern and a second metal pattern, wherein the first metal pattern includes a first base portion and a plurality of first protruding portions extending away from the first base portion, and the second metal pattern includes a second base portion and a plurality of second protruding portions extending away from the second base portion.
The semiconductor device of claim 11, wherein the transistor occupies a first area on a substrate and each of the plurality of test structures occupies a second area on the substrate, and wherein a ratio of the second area to the first area is equal to or less than 10%.
A semiconductor device, comprising: a transistor comprising: a plurality of layers, wherein each of the plurality of layers has at least one Group III-V compound mate-rial; a gate electrode operatively coupled to at least one of the plurality of layers; a source electrode disposed on a first side of the gate electrode; a drain electrode disposed on a second side of the gate electrode; a field plate disposed between the gate electrode and the drain electrode; and 15 a plurality of conductive lines disposed above the gate electrode, the source electrode, and the drain elec-trode; a plurality of test structures, wherein each of the test structures, each including a first metal pattern and a 20 second metal pattern, is configured to emulate at least B₂ one of the gate electrode, the source electrode, the drain electrode, the field plate, or at least one of the plurality of conductive lines; and a charge pump connected to one of the corresponding first metal pattern or the corresponding second metal pattern of at least one of the test structures.
The semiconductor device of claim 17, wherein the charge pump is formed of at least one Group III-V com-pound material and configured to provide the connected first metal pattern or the connected second metal pattern with a voltage equal to or greater than 650 volts (V).
The semiconductor device of claim 17, wherein the plurality of test structures are each disposed immediately next to the transistor.
The semiconductor device of claim 17, wherein the first metal pattern includes a first base portion and a plurality of first protruding portions extending away from the first base portion, and the second metal pattern includes a second base portion and a plurality of second protruding portions extending away from the second base portion. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
GaN-based transistor with test structures
Materials described outside the worked examples.
Group III-V compound material
gallium nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 7). In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device includes a transistor comprising: a plurality …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0.25–6 µm | — |
Thickness |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 18
Related documents with shared materials, methods, properties, or citations.
aluminum gallium nitride (AlGaN)
AlGaN
indium gallium nitride (InGaN)
InGaN
aluminum indium gallium nitride (AlInGaN)
AlInGaN
silicon
Si
sapphire
silicon carbide
SiC
FIG. 13 illustrates a cross-sectional view of a diode- connected transistor implemented by the charge pump of
| 300–3000 Å |
| — |
Temperature | 800–900 °C | — |
Thickness | 100–1200 Å | — |
Thickness | 500–5000 Å | — |
Thickness | 100–1000 Å | — |
Thickness | 2000–5000 Å | — |
Thickness | ≤ 0.25 µm | — |
GALLIUM NITRIDE SUPERJUNCTION TRANSISTOR
aluminum gallium nitride (AlGaN)
AlGaN
indium gallium nitride (InGaN)
InGaN
aluminum indium gallium nitride (AlInGaN)
AlInGaN
silicon
Si
sapphire
silicon carbide
SiC
FIG. 13 illustrates a cross-sectional view of a diode- connected transistor implemented by the charge pump of
| 300–3000 Å |
| — |
Temperature | 800–900 °C | — |
Thickness | 100–1200 Å | — |
Thickness | 500–5000 Å | — |
Thickness | 100–1000 Å | — |
Thickness | 2000–5000 Å | — |
Thickness | ≤ 0.25 µm | — |
GALLIUM NITRIDE SUPERJUNCTION TRANSISTOR
aluminum gallium nitride (AlGaN)
AlGaN
indium gallium nitride (InGaN)
InGaN
aluminum indium gallium nitride (AlInGaN)
AlInGaN
silicon
Si
sapphire
silicon carbide
SiC
FIG. 13 illustrates a cross-sectional view of a diode- connected transistor implemented by the charge pump of
| 300–3000 Å |
| — |
Temperature | 800–900 °C | — |
Thickness | 100–1200 Å | — |
Thickness | 500–5000 Å | — |
Thickness | 100–1000 Å | — |
Thickness | 2000–5000 Å | — |
Thickness | ≤ 0.25 µm | — |
GALLIUM NITRIDE SUPERJUNCTION TRANSISTOR
aluminum gallium nitride (AlGaN)
AlGaN
indium gallium nitride (InGaN)
InGaN
aluminum indium gallium nitride (AlInGaN)
AlInGaN
silicon
Si
sapphire
silicon carbide
SiC
FIG. 13 illustrates a cross-sectional view of a diode- connected transistor implemented by the charge pump of
| 300–3000 Å |
| — |
Temperature | 800–900 °C | — |
Thickness | 100–1200 Å | — |
Thickness | 500–5000 Å | — |
Thickness | 100–1000 Å | — |
Thickness | 2000–5000 Å | — |
Thickness | ≤ 0.25 µm | — |
