Patent
US 12,635,158 B2GALLIUM NITRIDE SUPERJUNCTION TRANSISTOR
James G. Fiorenza, Guanghai Ding, Daniel Piedra
Analog Devices, Inc., Wilmington, MA (US)·May 19, 2026·US
Copyright © 2026 Matter42. All rights reserved.
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US 12,635,158 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts a cross-sectional diagram of an example of a compound semiconductor heterostructure transistor device having multiple two-dimensional electron …
FIG. 2 depicts a cross-sectional diagram of another example of a compound semiconductor heterostructure tran- 5 sistor device having multiple two-dimensional …
FIG. 3 depicts a cross-sectional diagram of another example of a compound semiconductor heterostructure tran- 10 sistor device having multiple two-dimensional …
FIG. 4 depicts a cross-sectional diagram of another example of a compound semiconductor heterostructure tran- 15 sistor device having multiple two-dimensional …
FIG. 5 depicts a cross-sectional diagram of another example of a compound semiconductor heterostructure tran- 20 sistor device having multiple two-dimensional …
FIG. 6B.
FIG. 7A.
FIG. 8 is an example of a flow diagram of a method of forming a compound semiconductor heterostructure transis- 40 tor device, in accordance with various …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A compound semiconductor heterostructure transistor device having multiple two-dimensional electron gas chan-nels, the compound semiconductor heterostructure transistor device comprising: 50 a substrate; a first semiconductor material layer formed over the substrate; a second semiconductor material layer formed over the first semiconductor material to form a first compound semiconductor heterostructure having a buried first two-dimensional electron gas (2DEG) channel, wherein the buried first 2DEG channel is more electri-cally conductive than either the first semiconductor material layer or the second semiconductor material layer; a third semiconductor material layer formed over a fourth semiconductor material layer, wherein the fourth semiconductor material layer is formed over the substrate, to form a second compound semiconductor heterostructure having a topside second 2DEG channel, wherein the topside second 2DEG channel is more B₂ electrically conductive than either the third semicon-ductor material layer or the fourth semiconductor mate-rial layer; a drain electrode electrically coupled to the first semicon-ductor material layer; a source electrode electrically coupled to the topside second 2DEG channel; and a gate electrode formed over the third semiconductor material layer, wherein the gate electrode is associated with only the topside second 2DEG channel and not associated with the buried first 2DEG channel; and a conductive material extending vertically and electrically coupling 1) the buried first 2DEG channel and 2) the topside second 2DEG channel, wherein a current through the buried first 2DEG channel is approximately the same as a current through the topside second 2DEG channel.
The compound semiconductor heterostructure transis-tor device of claim 1, comprising: a first doped semiconductor material extending vertically between and electrically coupling the second semicon-ductor material layer and the third semiconductor mate-rial layer.
The compound semiconductor heterostructure transis-tor device of claim 1, wherein the third semiconductor material layer underlies completely between the source electrode and the drain electrode.
The compound semiconductor heterostructure transis-tor device of claim 1, wherein the third semiconductor material layer does not underlie completely between the source electrode and the drain electrode.
The compound semiconductor heterostructure transis-tor device of claim 1, comprising: 20 a dopant layer implanted in the substrate, wherein the dopant layer includes a p-type material forming a first region.
The compound semiconductor heterostructure transis-tor device of claim 1, wherein the substrate includes silicon carbide.
A method of forming a compound semiconductor heterostructure transistor device, the method comprising: forming a first semiconductor material layer over a substrate; forming a second semiconductor material layer over the first semiconductor material layer to form a first com-pound semiconductor heterostructure having a buried first two-dimensional electron gas (2DEG) channel, wherein the buried first 2DEG channel is more electri-cally conductive than either the first semiconductor material layer or the second semiconductor material layer; forming a third semiconductor material layer over a fourth semiconductor material layer, wherein the fourth semiconductor material layer is formed over the substrate, to form a second compound semiconductor heterostructure having a topside second 2DEG channel, wherein the topside second 2DEG channel is more electrically conductive than either the third semicon-ductor material layer or the fourth semiconductor mate-rial layer; forming a drain electrode electrically coupled to the first semiconductor material layer; forming a source electrode electrically coupled to only the topside second 2DEG channel; and forming a gate electrode over the third semiconductor material layer; and forming a conductive material that extends vertically and electrically couples 1) the buried first 2DEG channel and 2) the topside second 2DEG channel, wherein a current through the buried first 2DEG channel is approximately the same as a current through the topside second 2DEG channel.
The method of claim 13, comprising: forming a first doped semiconductor material that extends vertically between and electrically couples the second semiconductor material layer and the third semicon-ductor material layer.
The method of claim 13, further comprising: forming a fifth semiconductor material layer over the second semiconductor material layer; forming a sixth semiconductor material layer formed over the fifth semiconductor material layer to form a third compound semiconductor heterostructure having a bur-ied third 2DEG channel, wherein the buried third 2DEG channel is more electrically conductive than either the fifth semiconductor material layer or the sixth semiconductor material layer; and wherein the forming a conductive material that extends vertically between and electrically couples the 1) bur-ied first 2DEG channel and the buried third 2DEG channel, and 2) the topside second 2DEG channel with the 3) the buried third 2DEG channel.
Layer stacks claimed or described, ordered top of device to substrate.
GaN superjunction transistor with dual 2DEG channels (two-heterostructure)
Materials described outside the worked examples.
first semiconductor material layer
gallium nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 depicts a cross-sectional diagram of an example of a compound semiconductor heterostructure transistor device having multiple two-dimensional electron …
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 7
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,635,158 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts a cross-sectional diagram of an example of a compound semiconductor heterostructure transistor device having multiple two-dimensional electron …
FIG. 2 depicts a cross-sectional diagram of another example of a compound semiconductor heterostructure tran- 5 sistor device having multiple two-dimensional …
FIG. 3 depicts a cross-sectional diagram of another example of a compound semiconductor heterostructure tran- 10 sistor device having multiple two-dimensional …
FIG. 4 depicts a cross-sectional diagram of another example of a compound semiconductor heterostructure tran- 15 sistor device having multiple two-dimensional …
FIG. 5 depicts a cross-sectional diagram of another example of a compound semiconductor heterostructure tran- 20 sistor device having multiple two-dimensional …
FIG. 6B.
FIG. 7A.
FIG. 8 is an example of a flow diagram of a method of forming a compound semiconductor heterostructure transis- 40 tor device, in accordance with various …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A compound semiconductor heterostructure transistor device having multiple two-dimensional electron gas chan-nels, the compound semiconductor heterostructure transistor device comprising: 50 a substrate; a first semiconductor material layer formed over the substrate; a second semiconductor material layer formed over the first semiconductor material to form a first compound semiconductor heterostructure having a buried first two-dimensional electron gas (2DEG) channel, wherein the buried first 2DEG channel is more electri-cally conductive than either the first semiconductor material layer or the second semiconductor material layer; a third semiconductor material layer formed over a fourth semiconductor material layer, wherein the fourth semiconductor material layer is formed over the substrate, to form a second compound semiconductor heterostructure having a topside second 2DEG channel, wherein the topside second 2DEG channel is more B₂ electrically conductive than either the third semicon-ductor material layer or the fourth semiconductor mate-rial layer; a drain electrode electrically coupled to the first semicon-ductor material layer; a source electrode electrically coupled to the topside second 2DEG channel; and a gate electrode formed over the third semiconductor material layer, wherein the gate electrode is associated with only the topside second 2DEG channel and not associated with the buried first 2DEG channel; and a conductive material extending vertically and electrically coupling 1) the buried first 2DEG channel and 2) the topside second 2DEG channel, wherein a current through the buried first 2DEG channel is approximately the same as a current through the topside second 2DEG channel.
The compound semiconductor heterostructure transis-tor device of claim 1, comprising: a first doped semiconductor material extending vertically between and electrically coupling the second semicon-ductor material layer and the third semiconductor mate-rial layer.
The compound semiconductor heterostructure transis-tor device of claim 1, wherein the third semiconductor material layer underlies completely between the source electrode and the drain electrode.
The compound semiconductor heterostructure transis-tor device of claim 1, wherein the third semiconductor material layer does not underlie completely between the source electrode and the drain electrode.
The compound semiconductor heterostructure transis-tor device of claim 1, comprising: 20 a dopant layer implanted in the substrate, wherein the dopant layer includes a p-type material forming a first region.
The compound semiconductor heterostructure transis-tor device of claim 1, wherein the substrate includes silicon carbide.
A method of forming a compound semiconductor heterostructure transistor device, the method comprising: forming a first semiconductor material layer over a substrate; forming a second semiconductor material layer over the first semiconductor material layer to form a first com-pound semiconductor heterostructure having a buried first two-dimensional electron gas (2DEG) channel, wherein the buried first 2DEG channel is more electri-cally conductive than either the first semiconductor material layer or the second semiconductor material layer; forming a third semiconductor material layer over a fourth semiconductor material layer, wherein the fourth semiconductor material layer is formed over the substrate, to form a second compound semiconductor heterostructure having a topside second 2DEG channel, wherein the topside second 2DEG channel is more electrically conductive than either the third semicon-ductor material layer or the fourth semiconductor mate-rial layer; forming a drain electrode electrically coupled to the first semiconductor material layer; forming a source electrode electrically coupled to only the topside second 2DEG channel; and forming a gate electrode over the third semiconductor material layer; and forming a conductive material that extends vertically and electrically couples 1) the buried first 2DEG channel and 2) the topside second 2DEG channel, wherein a current through the buried first 2DEG channel is approximately the same as a current through the topside second 2DEG channel.
The method of claim 13, comprising: forming a first doped semiconductor material that extends vertically between and electrically couples the second semiconductor material layer and the third semicon-ductor material layer.
The method of claim 13, further comprising: forming a fifth semiconductor material layer over the second semiconductor material layer; forming a sixth semiconductor material layer formed over the fifth semiconductor material layer to form a third compound semiconductor heterostructure having a bur-ied third 2DEG channel, wherein the buried third 2DEG channel is more electrically conductive than either the fifth semiconductor material layer or the sixth semiconductor material layer; and wherein the forming a conductive material that extends vertically between and electrically couples the 1) bur-ied first 2DEG channel and the buried third 2DEG channel, and 2) the topside second 2DEG channel with the 3) the buried third 2DEG channel.
Layer stacks claimed or described, ordered top of device to substrate.
GaN superjunction transistor with dual 2DEG channels (two-heterostructure)
Materials described outside the worked examples.
first semiconductor material layer
gallium nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 depicts a cross-sectional diagram of an example of a compound semiconductor heterostructure transistor device having multiple two-dimensional electron …
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 7
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,635,158 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts a cross-sectional diagram of an example of a compound semiconductor heterostructure transistor device having multiple two-dimensional electron …
FIG. 2 depicts a cross-sectional diagram of another example of a compound semiconductor heterostructure tran- 5 sistor device having multiple two-dimensional …
FIG. 3 depicts a cross-sectional diagram of another example of a compound semiconductor heterostructure tran- 10 sistor device having multiple two-dimensional …
FIG. 4 depicts a cross-sectional diagram of another example of a compound semiconductor heterostructure tran- 15 sistor device having multiple two-dimensional …
FIG. 5 depicts a cross-sectional diagram of another example of a compound semiconductor heterostructure tran- 20 sistor device having multiple two-dimensional …
FIG. 6B.
FIG. 7A.
FIG. 8 is an example of a flow diagram of a method of forming a compound semiconductor heterostructure transis- 40 tor device, in accordance with various …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A compound semiconductor heterostructure transistor device having multiple two-dimensional electron gas chan-nels, the compound semiconductor heterostructure transistor device comprising: 50 a substrate; a first semiconductor material layer formed over the substrate; a second semiconductor material layer formed over the first semiconductor material to form a first compound semiconductor heterostructure having a buried first two-dimensional electron gas (2DEG) channel, wherein the buried first 2DEG channel is more electri-cally conductive than either the first semiconductor material layer or the second semiconductor material layer; a third semiconductor material layer formed over a fourth semiconductor material layer, wherein the fourth semiconductor material layer is formed over the substrate, to form a second compound semiconductor heterostructure having a topside second 2DEG channel, wherein the topside second 2DEG channel is more B₂ electrically conductive than either the third semicon-ductor material layer or the fourth semiconductor mate-rial layer; a drain electrode electrically coupled to the first semicon-ductor material layer; a source electrode electrically coupled to the topside second 2DEG channel; and a gate electrode formed over the third semiconductor material layer, wherein the gate electrode is associated with only the topside second 2DEG channel and not associated with the buried first 2DEG channel; and a conductive material extending vertically and electrically coupling 1) the buried first 2DEG channel and 2) the topside second 2DEG channel, wherein a current through the buried first 2DEG channel is approximately the same as a current through the topside second 2DEG channel.
The compound semiconductor heterostructure transis-tor device of claim 1, comprising: a first doped semiconductor material extending vertically between and electrically coupling the second semicon-ductor material layer and the third semiconductor mate-rial layer.
The compound semiconductor heterostructure transis-tor device of claim 1, wherein the third semiconductor material layer underlies completely between the source electrode and the drain electrode.
The compound semiconductor heterostructure transis-tor device of claim 1, wherein the third semiconductor material layer does not underlie completely between the source electrode and the drain electrode.
The compound semiconductor heterostructure transis-tor device of claim 1, comprising: 20 a dopant layer implanted in the substrate, wherein the dopant layer includes a p-type material forming a first region.
The compound semiconductor heterostructure transis-tor device of claim 1, wherein the substrate includes silicon carbide.
A method of forming a compound semiconductor heterostructure transistor device, the method comprising: forming a first semiconductor material layer over a substrate; forming a second semiconductor material layer over the first semiconductor material layer to form a first com-pound semiconductor heterostructure having a buried first two-dimensional electron gas (2DEG) channel, wherein the buried first 2DEG channel is more electri-cally conductive than either the first semiconductor material layer or the second semiconductor material layer; forming a third semiconductor material layer over a fourth semiconductor material layer, wherein the fourth semiconductor material layer is formed over the substrate, to form a second compound semiconductor heterostructure having a topside second 2DEG channel, wherein the topside second 2DEG channel is more electrically conductive than either the third semicon-ductor material layer or the fourth semiconductor mate-rial layer; forming a drain electrode electrically coupled to the first semiconductor material layer; forming a source electrode electrically coupled to only the topside second 2DEG channel; and forming a gate electrode over the third semiconductor material layer; and forming a conductive material that extends vertically and electrically couples 1) the buried first 2DEG channel and 2) the topside second 2DEG channel, wherein a current through the buried first 2DEG channel is approximately the same as a current through the topside second 2DEG channel.
The method of claim 13, comprising: forming a first doped semiconductor material that extends vertically between and electrically couples the second semiconductor material layer and the third semicon-ductor material layer.
The method of claim 13, further comprising: forming a fifth semiconductor material layer over the second semiconductor material layer; forming a sixth semiconductor material layer formed over the fifth semiconductor material layer to form a third compound semiconductor heterostructure having a bur-ied third 2DEG channel, wherein the buried third 2DEG channel is more electrically conductive than either the fifth semiconductor material layer or the sixth semiconductor material layer; and wherein the forming a conductive material that extends vertically between and electrically couples the 1) bur-ied first 2DEG channel and the buried third 2DEG channel, and 2) the topside second 2DEG channel with the 3) the buried third 2DEG channel.
Layer stacks claimed or described, ordered top of device to substrate.
GaN superjunction transistor with dual 2DEG channels (two-heterostructure)
Materials described outside the worked examples.
first semiconductor material layer
gallium nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 depicts a cross-sectional diagram of an example of a compound semiconductor heterostructure transistor device having multiple two-dimensional electron …
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 7
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 12,635,158 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 depicts a cross-sectional diagram of an example of a compound semiconductor heterostructure transistor device having multiple two-dimensional electron …
FIG. 2 depicts a cross-sectional diagram of another example of a compound semiconductor heterostructure tran- 5 sistor device having multiple two-dimensional …
FIG. 3 depicts a cross-sectional diagram of another example of a compound semiconductor heterostructure tran- 10 sistor device having multiple two-dimensional …
FIG. 4 depicts a cross-sectional diagram of another example of a compound semiconductor heterostructure tran- 15 sistor device having multiple two-dimensional …
FIG. 5 depicts a cross-sectional diagram of another example of a compound semiconductor heterostructure tran- 20 sistor device having multiple two-dimensional …
FIG. 6B.
FIG. 7A.
FIG. 8 is an example of a flow diagram of a method of forming a compound semiconductor heterostructure transis- 40 tor device, in accordance with various …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A compound semiconductor heterostructure transistor device having multiple two-dimensional electron gas chan-nels, the compound semiconductor heterostructure transistor device comprising: 50 a substrate; a first semiconductor material layer formed over the substrate; a second semiconductor material layer formed over the first semiconductor material to form a first compound semiconductor heterostructure having a buried first two-dimensional electron gas (2DEG) channel, wherein the buried first 2DEG channel is more electri-cally conductive than either the first semiconductor material layer or the second semiconductor material layer; a third semiconductor material layer formed over a fourth semiconductor material layer, wherein the fourth semiconductor material layer is formed over the substrate, to form a second compound semiconductor heterostructure having a topside second 2DEG channel, wherein the topside second 2DEG channel is more B₂ electrically conductive than either the third semicon-ductor material layer or the fourth semiconductor mate-rial layer; a drain electrode electrically coupled to the first semicon-ductor material layer; a source electrode electrically coupled to the topside second 2DEG channel; and a gate electrode formed over the third semiconductor material layer, wherein the gate electrode is associated with only the topside second 2DEG channel and not associated with the buried first 2DEG channel; and a conductive material extending vertically and electrically coupling 1) the buried first 2DEG channel and 2) the topside second 2DEG channel, wherein a current through the buried first 2DEG channel is approximately the same as a current through the topside second 2DEG channel.
The compound semiconductor heterostructure transis-tor device of claim 1, comprising: a first doped semiconductor material extending vertically between and electrically coupling the second semicon-ductor material layer and the third semiconductor mate-rial layer.
The compound semiconductor heterostructure transis-tor device of claim 1, wherein the third semiconductor material layer underlies completely between the source electrode and the drain electrode.
The compound semiconductor heterostructure transis-tor device of claim 1, wherein the third semiconductor material layer does not underlie completely between the source electrode and the drain electrode.
The compound semiconductor heterostructure transis-tor device of claim 1, comprising: 20 a dopant layer implanted in the substrate, wherein the dopant layer includes a p-type material forming a first region.
The compound semiconductor heterostructure transis-tor device of claim 1, wherein the substrate includes silicon carbide.
A method of forming a compound semiconductor heterostructure transistor device, the method comprising: forming a first semiconductor material layer over a substrate; forming a second semiconductor material layer over the first semiconductor material layer to form a first com-pound semiconductor heterostructure having a buried first two-dimensional electron gas (2DEG) channel, wherein the buried first 2DEG channel is more electri-cally conductive than either the first semiconductor material layer or the second semiconductor material layer; forming a third semiconductor material layer over a fourth semiconductor material layer, wherein the fourth semiconductor material layer is formed over the substrate, to form a second compound semiconductor heterostructure having a topside second 2DEG channel, wherein the topside second 2DEG channel is more electrically conductive than either the third semicon-ductor material layer or the fourth semiconductor mate-rial layer; forming a drain electrode electrically coupled to the first semiconductor material layer; forming a source electrode electrically coupled to only the topside second 2DEG channel; and forming a gate electrode over the third semiconductor material layer; and forming a conductive material that extends vertically and electrically couples 1) the buried first 2DEG channel and 2) the topside second 2DEG channel, wherein a current through the buried first 2DEG channel is approximately the same as a current through the topside second 2DEG channel.
The method of claim 13, comprising: forming a first doped semiconductor material that extends vertically between and electrically couples the second semiconductor material layer and the third semicon-ductor material layer.
The method of claim 13, further comprising: forming a fifth semiconductor material layer over the second semiconductor material layer; forming a sixth semiconductor material layer formed over the fifth semiconductor material layer to form a third compound semiconductor heterostructure having a bur-ied third 2DEG channel, wherein the buried third 2DEG channel is more electrically conductive than either the fifth semiconductor material layer or the sixth semiconductor material layer; and wherein the forming a conductive material that extends vertically between and electrically couples the 1) bur-ied first 2DEG channel and the buried third 2DEG channel, and 2) the topside second 2DEG channel with the 3) the buried third 2DEG channel.
Layer stacks claimed or described, ordered top of device to substrate.
GaN superjunction transistor with dual 2DEG channels (two-heterostructure)
Materials described outside the worked examples.
first semiconductor material layer
gallium nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 depicts a cross-sectional diagram of an example of a compound semiconductor heterostructure transistor device having multiple two-dimensional electron …
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 7
Related documents with shared materials, methods, properties, or citations.
GaN superjunction transistor with three 2DEG channels (three-heterostructure)
second semiconductor material layer
aluminum gallium nitride (AlGaN)
AlGaN
third semiconductor material layer
fourth semiconductor material layer
first doped semiconductor material
fifth semiconductor material layer
sixth semiconductor material layer
silicon
Si
p-type dopant layer implanted in substrate
silicon carbide
SiC
aluminum nitride (AlN)
AlN
AlN/GaN/AlN heterostructure
InAlN/GaN heterostructure
AlGaN/GaN heterostructure
FIG. 6B.
FIG. 7A.
Cited non-patent literature · 1
GaN superjunction transistor with three 2DEG channels (three-heterostructure)
second semiconductor material layer
aluminum gallium nitride (AlGaN)
AlGaN
third semiconductor material layer
fourth semiconductor material layer
first doped semiconductor material
fifth semiconductor material layer
sixth semiconductor material layer
silicon
Si
p-type dopant layer implanted in substrate
silicon carbide
SiC
aluminum nitride (AlN)
AlN
AlN/GaN/AlN heterostructure
InAlN/GaN heterostructure
AlGaN/GaN heterostructure
FIG. 6B.
FIG. 7A.
Cited non-patent literature · 1
GaN superjunction transistor with three 2DEG channels (three-heterostructure)
second semiconductor material layer
aluminum gallium nitride (AlGaN)
AlGaN
third semiconductor material layer
fourth semiconductor material layer
first doped semiconductor material
fifth semiconductor material layer
sixth semiconductor material layer
silicon
Si
p-type dopant layer implanted in substrate
silicon carbide
SiC
aluminum nitride (AlN)
AlN
AlN/GaN/AlN heterostructure
InAlN/GaN heterostructure
AlGaN/GaN heterostructure
FIG. 6B.
FIG. 7A.
Cited non-patent literature · 1
GaN superjunction transistor with three 2DEG channels (three-heterostructure)
second semiconductor material layer
aluminum gallium nitride (AlGaN)
AlGaN
third semiconductor material layer
fourth semiconductor material layer
first doped semiconductor material
fifth semiconductor material layer
sixth semiconductor material layer
silicon
Si
p-type dopant layer implanted in substrate
silicon carbide
SiC
aluminum nitride (AlN)
AlN
AlN/GaN/AlN heterostructure
InAlN/GaN heterostructure
AlGaN/GaN heterostructure
FIG. 6B.
FIG. 7A.
Cited non-patent literature · 1