Patent
US 8,344,420ENHANCEMENT-MODE GALLIUM NITRIDE HIGH ELECTRON MOBILITY TRANSISTOR
Jose Jimenez
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 8,344,420Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a conduction band diagram of a related-art gallium nitride high electron mobility transistor.
Figure 2 is a cross-sectional view of a heterostructure that may be used for forming an E-mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 3 is a conduction band diagram of an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 4 is a cross-sectional view of an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 5 is a cross-sectional view of another E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 6 is a cross-sectional view of another E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 7 is a simulated transfer curve for an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 8 is a simulated lo-V₀ curve for an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 9 is a cross-sectional view of an E -mode gallium nitride high electron mobility transistor and a D-mode gallium nitride high electron mobility transistor formed from the same heterostructure accordance with various embodiments.
Figure 10 is a block diagram of a system incorporating an E -mode gallium nitride high electron mobility transistor structure in accordance with various embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An apparatus comprising: a first barrier layer including aluminum; a gallium nitride channel layer on the first barrier layer; and a second barrier layer including a first aluminum gallium nitride sublayer directly on the gallium nitride channel layer, a-seee n dan aluminum-free gallium nitride sublayer directly on the first sublayer, and a thi rd- second aluminum gallium nitride sublayer directl y on the seeend aluminum-free gallium nitride sublayer, wherein each of the first aluminum gallium nitride sublayer and the third-second aluminum gallium nitride sublayer including aluminum at a concentration greater than a concentration of aluminum of the first barrier layer and wherei- the
The apparatus of claim 1, wherein the first barrier layer is aluminum gallium nitride,, al u m inu m gallium nitr- ide, and wherein the gallium nitride channel la v er is directly on the first barrier layer.
The apparatus of claim 1, further comprising a substrate, wherein the first barrier layer is directly on the substrate, and wherein the substrate comprises silicon carbide, gallium nitride, aluminum nitride, or silicon.
The apparatus of claim 1, further comprising a gate electrode recessed into the thi-d- second aluminum gallium nitride sublayer.
The apparatus of claim 1, wherein the first sublayer is on the gallium nitride channel layer, and wherein the HEM T further comprises an etch stop layer between the second sublayer and the third sublayer. withdrawn
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A method comprising: forming a first barrier layer including aluminum; forming a gallium nitride channel layer on the first barrier layer; a nd forming a first aluminum gallium nitride sublayer directl y on the gallium nitride channel layer; forming a-seee n dan aluminum-free gallium nitride sublayer directly on the first aluminum gallium nitride sublayer; and forming a third- second aluminum gallium nitride sublayer directl y on the seeend aluminum-free gallium nitride sublayer, wherein the first aluminum gallium nitride sublayer and the th i r d second aluminum gallium nitride sublayer each include aluminum at a concentration greater than a concentration of aluminum of the first barrier layer nitr- ide.
The method of claim 15, wherein the first barrier layer is aluminum gallium nitride, and wherein the gallium nitride channel la y er is directly on the first barrier layer.
The method of claim 15, further comprising forming a first gate electrode recessed into the third sublayer.
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Layer stacks claimed or described, ordered top of device to substrate.
enhancement-mode GaN HEMT
Materials described outside the worked examples.
aluminum gallium nitride (first barrier layer)
AlGaN
gallium nitride channel layer
GaN
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 is a conduction band diagram of a related-art gallium nitride high electron mobility transistor.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
first sublayer (AlGaN) thickness | 150 Angstrom | AlGaN |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,344,420Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a conduction band diagram of a related-art gallium nitride high electron mobility transistor.
Figure 2 is a cross-sectional view of a heterostructure that may be used for forming an E-mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 3 is a conduction band diagram of an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 4 is a cross-sectional view of an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 5 is a cross-sectional view of another E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 6 is a cross-sectional view of another E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 7 is a simulated transfer curve for an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 8 is a simulated lo-V₀ curve for an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 9 is a cross-sectional view of an E -mode gallium nitride high electron mobility transistor and a D-mode gallium nitride high electron mobility transistor formed from the same heterostructure accordance with various embodiments.
Figure 10 is a block diagram of a system incorporating an E -mode gallium nitride high electron mobility transistor structure in accordance with various embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An apparatus comprising: a first barrier layer including aluminum; a gallium nitride channel layer on the first barrier layer; and a second barrier layer including a first aluminum gallium nitride sublayer directly on the gallium nitride channel layer, a-seee n dan aluminum-free gallium nitride sublayer directly on the first sublayer, and a thi rd- second aluminum gallium nitride sublayer directl y on the seeend aluminum-free gallium nitride sublayer, wherein each of the first aluminum gallium nitride sublayer and the third-second aluminum gallium nitride sublayer including aluminum at a concentration greater than a concentration of aluminum of the first barrier layer and wherei- the
The apparatus of claim 1, wherein the first barrier layer is aluminum gallium nitride,, al u m inu m gallium nitr- ide, and wherein the gallium nitride channel la v er is directly on the first barrier layer.
The apparatus of claim 1, further comprising a substrate, wherein the first barrier layer is directly on the substrate, and wherein the substrate comprises silicon carbide, gallium nitride, aluminum nitride, or silicon.
The apparatus of claim 1, further comprising a gate electrode recessed into the thi-d- second aluminum gallium nitride sublayer.
The apparatus of claim 1, wherein the first sublayer is on the gallium nitride channel layer, and wherein the HEM T further comprises an etch stop layer between the second sublayer and the third sublayer. withdrawn
canceled
canceled
12-14. canceled
canceled
canceled
A method comprising: forming a first barrier layer including aluminum; forming a gallium nitride channel layer on the first barrier layer; a nd forming a first aluminum gallium nitride sublayer directl y on the gallium nitride channel layer; forming a-seee n dan aluminum-free gallium nitride sublayer directly on the first aluminum gallium nitride sublayer; and forming a third- second aluminum gallium nitride sublayer directl y on the seeend aluminum-free gallium nitride sublayer, wherein the first aluminum gallium nitride sublayer and the th i r d second aluminum gallium nitride sublayer each include aluminum at a concentration greater than a concentration of aluminum of the first barrier layer nitr- ide.
The method of claim 15, wherein the first barrier layer is aluminum gallium nitride, and wherein the gallium nitride channel la y er is directly on the first barrier layer.
The method of claim 15, further comprising forming a first gate electrode recessed into the third sublayer.
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2 1-26. canceled
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Layer stacks claimed or described, ordered top of device to substrate.
enhancement-mode GaN HEMT
Materials described outside the worked examples.
aluminum gallium nitride (first barrier layer)
AlGaN
gallium nitride channel layer
GaN
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 is a conduction band diagram of a related-art gallium nitride high electron mobility transistor.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
first sublayer (AlGaN) thickness | 150 Angstrom | AlGaN |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,344,420Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a conduction band diagram of a related-art gallium nitride high electron mobility transistor.
Figure 2 is a cross-sectional view of a heterostructure that may be used for forming an E-mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 3 is a conduction band diagram of an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 4 is a cross-sectional view of an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 5 is a cross-sectional view of another E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 6 is a cross-sectional view of another E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 7 is a simulated transfer curve for an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 8 is a simulated lo-V₀ curve for an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 9 is a cross-sectional view of an E -mode gallium nitride high electron mobility transistor and a D-mode gallium nitride high electron mobility transistor formed from the same heterostructure accordance with various embodiments.
Figure 10 is a block diagram of a system incorporating an E -mode gallium nitride high electron mobility transistor structure in accordance with various embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An apparatus comprising: a first barrier layer including aluminum; a gallium nitride channel layer on the first barrier layer; and a second barrier layer including a first aluminum gallium nitride sublayer directly on the gallium nitride channel layer, a-seee n dan aluminum-free gallium nitride sublayer directly on the first sublayer, and a thi rd- second aluminum gallium nitride sublayer directl y on the seeend aluminum-free gallium nitride sublayer, wherein each of the first aluminum gallium nitride sublayer and the third-second aluminum gallium nitride sublayer including aluminum at a concentration greater than a concentration of aluminum of the first barrier layer and wherei- the
The apparatus of claim 1, wherein the first barrier layer is aluminum gallium nitride,, al u m inu m gallium nitr- ide, and wherein the gallium nitride channel la v er is directly on the first barrier layer.
The apparatus of claim 1, further comprising a substrate, wherein the first barrier layer is directly on the substrate, and wherein the substrate comprises silicon carbide, gallium nitride, aluminum nitride, or silicon.
The apparatus of claim 1, further comprising a gate electrode recessed into the thi-d- second aluminum gallium nitride sublayer.
The apparatus of claim 1, wherein the first sublayer is on the gallium nitride channel layer, and wherein the HEM T further comprises an etch stop layer between the second sublayer and the third sublayer. withdrawn
canceled
canceled
12-14. canceled
canceled
canceled
A method comprising: forming a first barrier layer including aluminum; forming a gallium nitride channel layer on the first barrier layer; a nd forming a first aluminum gallium nitride sublayer directl y on the gallium nitride channel layer; forming a-seee n dan aluminum-free gallium nitride sublayer directly on the first aluminum gallium nitride sublayer; and forming a third- second aluminum gallium nitride sublayer directl y on the seeend aluminum-free gallium nitride sublayer, wherein the first aluminum gallium nitride sublayer and the th i r d second aluminum gallium nitride sublayer each include aluminum at a concentration greater than a concentration of aluminum of the first barrier layer nitr- ide.
The method of claim 15, wherein the first barrier layer is aluminum gallium nitride, and wherein the gallium nitride channel la y er is directly on the first barrier layer.
The method of claim 15, further comprising forming a first gate electrode recessed into the third sublayer.
canceled
2 1-26. canceled
canceled
canceled
canceled
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canceled
Layer stacks claimed or described, ordered top of device to substrate.
enhancement-mode GaN HEMT
Materials described outside the worked examples.
aluminum gallium nitride (first barrier layer)
AlGaN
gallium nitride channel layer
GaN
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 is a conduction band diagram of a related-art gallium nitride high electron mobility transistor.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
first sublayer (AlGaN) thickness | 150 Angstrom | AlGaN |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 8,344,420Patent drawings and their descriptions. Click a drawing to enlarge it.
Figure 1 is a conduction band diagram of a related-art gallium nitride high electron mobility transistor.
Figure 2 is a cross-sectional view of a heterostructure that may be used for forming an E-mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 3 is a conduction band diagram of an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 4 is a cross-sectional view of an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 5 is a cross-sectional view of another E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 6 is a cross-sectional view of another E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 7 is a simulated transfer curve for an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 8 is a simulated lo-V₀ curve for an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 9 is a cross-sectional view of an E -mode gallium nitride high electron mobility transistor and a D-mode gallium nitride high electron mobility transistor formed from the same heterostructure accordance with various embodiments.
Figure 10 is a block diagram of a system incorporating an E -mode gallium nitride high electron mobility transistor structure in accordance with various embodiments.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An apparatus comprising: a first barrier layer including aluminum; a gallium nitride channel layer on the first barrier layer; and a second barrier layer including a first aluminum gallium nitride sublayer directly on the gallium nitride channel layer, a-seee n dan aluminum-free gallium nitride sublayer directly on the first sublayer, and a thi rd- second aluminum gallium nitride sublayer directl y on the seeend aluminum-free gallium nitride sublayer, wherein each of the first aluminum gallium nitride sublayer and the third-second aluminum gallium nitride sublayer including aluminum at a concentration greater than a concentration of aluminum of the first barrier layer and wherei- the
The apparatus of claim 1, wherein the first barrier layer is aluminum gallium nitride,, al u m inu m gallium nitr- ide, and wherein the gallium nitride channel la v er is directly on the first barrier layer.
The apparatus of claim 1, further comprising a substrate, wherein the first barrier layer is directly on the substrate, and wherein the substrate comprises silicon carbide, gallium nitride, aluminum nitride, or silicon.
The apparatus of claim 1, further comprising a gate electrode recessed into the thi-d- second aluminum gallium nitride sublayer.
The apparatus of claim 1, wherein the first sublayer is on the gallium nitride channel layer, and wherein the HEM T further comprises an etch stop layer between the second sublayer and the third sublayer. withdrawn
canceled
canceled
12-14. canceled
canceled
canceled
A method comprising: forming a first barrier layer including aluminum; forming a gallium nitride channel layer on the first barrier layer; a nd forming a first aluminum gallium nitride sublayer directl y on the gallium nitride channel layer; forming a-seee n dan aluminum-free gallium nitride sublayer directly on the first aluminum gallium nitride sublayer; and forming a third- second aluminum gallium nitride sublayer directl y on the seeend aluminum-free gallium nitride sublayer, wherein the first aluminum gallium nitride sublayer and the th i r d second aluminum gallium nitride sublayer each include aluminum at a concentration greater than a concentration of aluminum of the first barrier layer nitr- ide.
The method of claim 15, wherein the first barrier layer is aluminum gallium nitride, and wherein the gallium nitride channel la y er is directly on the first barrier layer.
The method of claim 15, further comprising forming a first gate electrode recessed into the third sublayer.
canceled
2 1-26. canceled
canceled
canceled
canceled
canceled
canceled
Layer stacks claimed or described, ordered top of device to substrate.
enhancement-mode GaN HEMT
Materials described outside the worked examples.
aluminum gallium nitride (first barrier layer)
AlGaN
gallium nitride channel layer
GaN
Measurements and analyses referenced in the patent, with their drawing references.
Figure 1 is a conduction band diagram of a related-art gallium nitride high electron mobility transistor.
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
first sublayer (AlGaN) thickness | 150 Angstrom | AlGaN |
Related documents with shared materials, methods, properties, or citations.
depletion-mode GaN HEMT (integrated with enhancement-mode)
silicon carbide substrate
SiC
aluminum nitride substrate
AlN
silicon substrate
Si
Al0.2Ga0.8N first and third sublayers
Al0.2Ga0.8N
Al0.06Ga0.94N first barrier layer
Al0.06Ga0.94N
Figure 2 is a cross-sectional view of a heterostructure that may be used for forming an E-mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 3 is a conduction band diagram of an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 4 is a cross-sectional view of an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 5 is a cross-sectional view of another E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 6 is a cross-sectional view of another E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 7 is a simulated transfer curve for an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 8 is a simulated lo-V₀ curve for an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 9 is a cross-sectional view of an E -mode gallium nitride high electron mobility transistor and a D-mode gallium nitride high electron mobility transistor formed from the same heterostructure accordance with various embodiments.
Figure 10 is a block diagram of a system incorporating an E -mode gallium nitride high electron mobility transistor structure in accordance with various embodiments.
| 150 Angstrom |
AlGaN |
second sublayer (GaN) thickness | 100 Angstrom | GaN |
first barrier layer (AlGaN) thickness | 1.5 micrometer | Al0.06Ga0.94N |
GaN channel layer thickness | 400 Angstrom | GaN |
depletion-mode GaN HEMT (integrated with enhancement-mode)
silicon carbide substrate
SiC
aluminum nitride substrate
AlN
silicon substrate
Si
Al0.2Ga0.8N first and third sublayers
Al0.2Ga0.8N
Al0.06Ga0.94N first barrier layer
Al0.06Ga0.94N
Figure 2 is a cross-sectional view of a heterostructure that may be used for forming an E-mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 3 is a conduction band diagram of an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 4 is a cross-sectional view of an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 5 is a cross-sectional view of another E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 6 is a cross-sectional view of another E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 7 is a simulated transfer curve for an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 8 is a simulated lo-V₀ curve for an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 9 is a cross-sectional view of an E -mode gallium nitride high electron mobility transistor and a D-mode gallium nitride high electron mobility transistor formed from the same heterostructure accordance with various embodiments.
Figure 10 is a block diagram of a system incorporating an E -mode gallium nitride high electron mobility transistor structure in accordance with various embodiments.
| 150 Angstrom |
AlGaN |
second sublayer (GaN) thickness | 100 Angstrom | GaN |
first barrier layer (AlGaN) thickness | 1.5 micrometer | Al0.06Ga0.94N |
GaN channel layer thickness | 400 Angstrom | GaN |
depletion-mode GaN HEMT (integrated with enhancement-mode)
silicon carbide substrate
SiC
aluminum nitride substrate
AlN
silicon substrate
Si
Al0.2Ga0.8N first and third sublayers
Al0.2Ga0.8N
Al0.06Ga0.94N first barrier layer
Al0.06Ga0.94N
Figure 2 is a cross-sectional view of a heterostructure that may be used for forming an E-mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 3 is a conduction band diagram of an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 4 is a cross-sectional view of an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 5 is a cross-sectional view of another E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 6 is a cross-sectional view of another E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 7 is a simulated transfer curve for an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 8 is a simulated lo-V₀ curve for an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 9 is a cross-sectional view of an E -mode gallium nitride high electron mobility transistor and a D-mode gallium nitride high electron mobility transistor formed from the same heterostructure accordance with various embodiments.
Figure 10 is a block diagram of a system incorporating an E -mode gallium nitride high electron mobility transistor structure in accordance with various embodiments.
| 150 Angstrom |
AlGaN |
second sublayer (GaN) thickness | 100 Angstrom | GaN |
first barrier layer (AlGaN) thickness | 1.5 micrometer | Al0.06Ga0.94N |
GaN channel layer thickness | 400 Angstrom | GaN |
depletion-mode GaN HEMT (integrated with enhancement-mode)
silicon carbide substrate
SiC
aluminum nitride substrate
AlN
silicon substrate
Si
Al0.2Ga0.8N first and third sublayers
Al0.2Ga0.8N
Al0.06Ga0.94N first barrier layer
Al0.06Ga0.94N
Figure 2 is a cross-sectional view of a heterostructure that may be used for forming an E-mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 3 is a conduction band diagram of an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 4 is a cross-sectional view of an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 5 is a cross-sectional view of another E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 6 is a cross-sectional view of another E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 7 is a simulated transfer curve for an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 8 is a simulated lo-V₀ curve for an E -mode gallium nitride high electron mobility transistor in accordance with various embodiments.
Figure 9 is a cross-sectional view of an E -mode gallium nitride high electron mobility transistor and a D-mode gallium nitride high electron mobility transistor formed from the same heterostructure accordance with various embodiments.
Figure 10 is a block diagram of a system incorporating an E -mode gallium nitride high electron mobility transistor structure in accordance with various embodiments.
| 150 Angstrom |
AlGaN |
second sublayer (GaN) thickness | 100 Angstrom | GaN |
first barrier layer (AlGaN) thickness | 1.5 micrometer | Al0.06Ga0.94N |
GaN channel layer thickness | 400 Angstrom | GaN |