Patent
US 10,367,247PREPARATION METHOD FOR GaAs/Ge/GaAs HETEROGENEOUS SPiN DIODE FOR LOOP ANTENNA
XIAOXUE YIN
US
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Patent
Atlas literature
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US 10,367,247Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1- is a structural schematic view of a rec o nfigurable loop antenna according to an embodiment of the disclosure. [0045] FI G. 2 is a flowchart of a …
FIG. 2. Speci f ica l ly, t h e Ga As/Ge/GaAs h eter o gene ou s S P iN di o de.is prepared on a GeOI substrate 301, a nd a P regi on 3 04 and a n N region 3 …
FIG. 3 is a st ru ctural schemati c view of a se ii icond u ctor substrate o f a GeOI base frequency reco n figur a ble coupling ty pe feeding loop antenna b …
FIG. 4 is a struc tural schematic view of a dielectric plate of a l oop antenna provided by an embodiment of the discl osu re. [0048]
FIG. 5 is a structural schematic view of a GaAs/Ge/GaAs based heterogeneous SPiN diode provided by an embodiment of the disclosure. [0049]
FIG. 6 is a str u ctural schematic view of a GaAs/Ge/GaAs based heterogeneous SPiN diode string provided by an embodiment of the disclosure. [0050]
FIGS. 7A to 7R are schematic views of a preparation method f o r a GaAs/Ge/GaAs heterogeneous SP iN di o de according to an e mbodiment of the disclosure. On …
FIG. 8 is a structural schematic view of another GaAs/Ge/GaAs based heterogeneous SP i N diode according to an embodiment of the disclosure. DETAILED DESCRIPTI …
FIG. 70, depositing a Si O 2 1501 with a thickness of 800 nm on the surface by a CVD method; and [00 118] (4h) at 1000 degrees Celsius, annealing f o r 1 …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A preparation method for a GaAs/Ge/GaAs heterogeneous spintronic (SPiN) diode for a loop antenna, wherein the loop antenna comprises: a semiconductor substrate; a dielectric plate; a first SPiN diode ring, a second SPiN diode ring, first direct current (DC) bias wires and second DC bias wires, disposed on the semiconductor substrate; and a coupling type feed source, disposed on the dielectric plate; wherein,, the first DC bias wires and the second DC bias wires are formed on the semiconductor substrate by heavily doping process; wherein the preparation method for the SPiN diode comprises following steps of: (a) selecting a germanium-on-insulator (Ge O I) substrate; (b) etching a top Ge layer of the Ge O I substrate to form a first trench and a second trench in the top Ge layer; (c) depositing a gallium arsenide (GaAs) material in the first trench and the second trench; (d) performing P-type ion implantation into the GaAs material in the first trench to form a P-type active region and performing an N-type ion implantation into the GaAs material in the second trench to form an N-type active region, by ion implantation process; and (e) forming lead holes on surfaces of the P-type active region and the N-type active region and then sputtering a metal, to form the GaAs/Ge/GaAs heterogeneous SPiN diode. Currently amended
The preparation method according to claim 1, before the step (b), further comprising: (x1) preparing a silicon oxide (SiO₂) material on a surface of the Ge O I substrate to form a first SiO₂ layer; (x2) preparing a silicon nitride (SiN) material on a surface of the first SiO₂ layer to form a first SiN layer, to thereby form a first protective layer; (x3) etching the first protective layer and the Ge O I substrate by dry etching with a first mask, to form isolation trenches in the Ge O I substrate; (x4) filling the isolation trenches with an isolation material by a chemical vapor deposition (CVD) process; and (x5) removing the first protective layer and the isolation material outside the isolation trenches by a chemical mechanical polishing (CMP) process, to form an isolation region of the GaAs/Ge/GaAs heterogeneous SPiN diode. Original
The preparation method according to claim 1, wherein the step (b) comprises: (b1) preparing a SiO₂ material on a surface of the Ge O I substrate to form a second SiO₂ layer; (b2) preparing a SiN material on a surface of the second Si O₂ layer to form a second SiN layer, and thereby forming a second protective layer; and (b3) etching the second protective layer and the top Ge layer by anisotropic etching with a second mask, to form the first trench and the second trench in the top Ge layer. Original
The preparation method according to claim 1, before the step (c), further comprising: (yl) at 800-900 degrees Celsius, oxidizing the first trench and the second trench to form oxide layers on inner walls of the first trench and the second trench; and (y2) etching the oxide layers on the inner walls of the first trench and the second trench by a wet etching process to planarize the inner walls of first trench and the second trench. Original
The preparation method according to claim 1, wherein the step (c) comprises: (cl) depositing the GaAs material in the first trench and the second trenches by a metal- organic chemical vapor deposition (MOCVD) process; (c2) removing the GaAs material of a certain thickness outside the first trench and the second trench by a CMP process to planarize the first trench and the second trench. Original
The preparation method according to claim 1, wherein the step (d) comprises: (dl) performing a boron (B) ion implantation into the GaAs material in the first trench by an ion implantation process with a third mask, to form the P-type active region; (d2) performing a phosphorus (P) ion implantation into the GaAs material in the second trench by an ion implantation process with a fourth mask, to form the N-type active region; (d3) depositing a SiO₂ material on surfaces of the P-type active region and the N-type active region and activating impurities of the P-type active region and the N-type active region by an annealing process; and (d4) removing the SiO₂ material. Original
The preparation method according to claim 1, wherein the step (e) comprises: (el) depositing a SiO₂ material on an entire surface of the Ge O I substrate; (e2) etching off the SiO₂ material in part of positions in surfaces of the P-type active region and the N-type active region by an anisotropic etching process with a fifth mask, to form the lead holes; (e3) sputtering a metal material in the lead holes; and (e4) performing a passivation treatment and forming PAD s by photolithography, to form the GaAs/Ge/GaAs heterogeneous SPiN diode. Original
The preparation method according to claim 1, wherein the first SPiN diode ring comprises first SPiN diode strings, the second SPiN diode ring comprises second SPiN diode strings, and a perimeter of each of the first SPiN diode ring and the second SPiN diode ring is equal to an electromagnetic wavelength of a signal to be received. Original
The preparation method according to claim 1, wherein the coupling type feed source is formed on the dielectric plate; and the dielectric plate is provided with a metal microstrip patch on an upper surface and a metal grounding plate on a lower surface. Original
Layer stacks claimed or described, ordered top of device to substrate.
GaAs/Ge/GaAs heterogeneous SPiN diode
Materials described outside the worked examples.
gallium arsenide
GaAs
germanium
Ge
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 7A to 7R are schematic views of a preparation method f o r a GaAs/Ge/GaAs heterogeneous SP iN di o de according to an e mbodiment of the disclosure. On …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0–500 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,367,247Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1- is a structural schematic view of a rec o nfigurable loop antenna according to an embodiment of the disclosure. [0045] FI G. 2 is a flowchart of a …
FIG. 2. Speci f ica l ly, t h e Ga As/Ge/GaAs h eter o gene ou s S P iN di o de.is prepared on a GeOI substrate 301, a nd a P regi on 3 04 and a n N region 3 …
FIG. 3 is a st ru ctural schemati c view of a se ii icond u ctor substrate o f a GeOI base frequency reco n figur a ble coupling ty pe feeding loop antenna b …
FIG. 4 is a struc tural schematic view of a dielectric plate of a l oop antenna provided by an embodiment of the discl osu re. [0048]
FIG. 5 is a structural schematic view of a GaAs/Ge/GaAs based heterogeneous SPiN diode provided by an embodiment of the disclosure. [0049]
FIG. 6 is a str u ctural schematic view of a GaAs/Ge/GaAs based heterogeneous SPiN diode string provided by an embodiment of the disclosure. [0050]
FIGS. 7A to 7R are schematic views of a preparation method f o r a GaAs/Ge/GaAs heterogeneous SP iN di o de according to an e mbodiment of the disclosure. On …
FIG. 8 is a structural schematic view of another GaAs/Ge/GaAs based heterogeneous SP i N diode according to an embodiment of the disclosure. DETAILED DESCRIPTI …
FIG. 70, depositing a Si O 2 1501 with a thickness of 800 nm on the surface by a CVD method; and [00 118] (4h) at 1000 degrees Celsius, annealing f o r 1 …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A preparation method for a GaAs/Ge/GaAs heterogeneous spintronic (SPiN) diode for a loop antenna, wherein the loop antenna comprises: a semiconductor substrate; a dielectric plate; a first SPiN diode ring, a second SPiN diode ring, first direct current (DC) bias wires and second DC bias wires, disposed on the semiconductor substrate; and a coupling type feed source, disposed on the dielectric plate; wherein,, the first DC bias wires and the second DC bias wires are formed on the semiconductor substrate by heavily doping process; wherein the preparation method for the SPiN diode comprises following steps of: (a) selecting a germanium-on-insulator (Ge O I) substrate; (b) etching a top Ge layer of the Ge O I substrate to form a first trench and a second trench in the top Ge layer; (c) depositing a gallium arsenide (GaAs) material in the first trench and the second trench; (d) performing P-type ion implantation into the GaAs material in the first trench to form a P-type active region and performing an N-type ion implantation into the GaAs material in the second trench to form an N-type active region, by ion implantation process; and (e) forming lead holes on surfaces of the P-type active region and the N-type active region and then sputtering a metal, to form the GaAs/Ge/GaAs heterogeneous SPiN diode. Currently amended
The preparation method according to claim 1, before the step (b), further comprising: (x1) preparing a silicon oxide (SiO₂) material on a surface of the Ge O I substrate to form a first SiO₂ layer; (x2) preparing a silicon nitride (SiN) material on a surface of the first SiO₂ layer to form a first SiN layer, to thereby form a first protective layer; (x3) etching the first protective layer and the Ge O I substrate by dry etching with a first mask, to form isolation trenches in the Ge O I substrate; (x4) filling the isolation trenches with an isolation material by a chemical vapor deposition (CVD) process; and (x5) removing the first protective layer and the isolation material outside the isolation trenches by a chemical mechanical polishing (CMP) process, to form an isolation region of the GaAs/Ge/GaAs heterogeneous SPiN diode. Original
The preparation method according to claim 1, wherein the step (b) comprises: (b1) preparing a SiO₂ material on a surface of the Ge O I substrate to form a second SiO₂ layer; (b2) preparing a SiN material on a surface of the second Si O₂ layer to form a second SiN layer, and thereby forming a second protective layer; and (b3) etching the second protective layer and the top Ge layer by anisotropic etching with a second mask, to form the first trench and the second trench in the top Ge layer. Original
The preparation method according to claim 1, before the step (c), further comprising: (yl) at 800-900 degrees Celsius, oxidizing the first trench and the second trench to form oxide layers on inner walls of the first trench and the second trench; and (y2) etching the oxide layers on the inner walls of the first trench and the second trench by a wet etching process to planarize the inner walls of first trench and the second trench. Original
The preparation method according to claim 1, wherein the step (c) comprises: (cl) depositing the GaAs material in the first trench and the second trenches by a metal- organic chemical vapor deposition (MOCVD) process; (c2) removing the GaAs material of a certain thickness outside the first trench and the second trench by a CMP process to planarize the first trench and the second trench. Original
The preparation method according to claim 1, wherein the step (d) comprises: (dl) performing a boron (B) ion implantation into the GaAs material in the first trench by an ion implantation process with a third mask, to form the P-type active region; (d2) performing a phosphorus (P) ion implantation into the GaAs material in the second trench by an ion implantation process with a fourth mask, to form the N-type active region; (d3) depositing a SiO₂ material on surfaces of the P-type active region and the N-type active region and activating impurities of the P-type active region and the N-type active region by an annealing process; and (d4) removing the SiO₂ material. Original
The preparation method according to claim 1, wherein the step (e) comprises: (el) depositing a SiO₂ material on an entire surface of the Ge O I substrate; (e2) etching off the SiO₂ material in part of positions in surfaces of the P-type active region and the N-type active region by an anisotropic etching process with a fifth mask, to form the lead holes; (e3) sputtering a metal material in the lead holes; and (e4) performing a passivation treatment and forming PAD s by photolithography, to form the GaAs/Ge/GaAs heterogeneous SPiN diode. Original
The preparation method according to claim 1, wherein the first SPiN diode ring comprises first SPiN diode strings, the second SPiN diode ring comprises second SPiN diode strings, and a perimeter of each of the first SPiN diode ring and the second SPiN diode ring is equal to an electromagnetic wavelength of a signal to be received. Original
The preparation method according to claim 1, wherein the coupling type feed source is formed on the dielectric plate; and the dielectric plate is provided with a metal microstrip patch on an upper surface and a metal grounding plate on a lower surface. Original
Layer stacks claimed or described, ordered top of device to substrate.
GaAs/Ge/GaAs heterogeneous SPiN diode
Materials described outside the worked examples.
gallium arsenide
GaAs
germanium
Ge
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 7A to 7R are schematic views of a preparation method f o r a GaAs/Ge/GaAs heterogeneous SP iN di o de according to an e mbodiment of the disclosure. On …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0–500 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,367,247Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1- is a structural schematic view of a rec o nfigurable loop antenna according to an embodiment of the disclosure. [0045] FI G. 2 is a flowchart of a …
FIG. 2. Speci f ica l ly, t h e Ga As/Ge/GaAs h eter o gene ou s S P iN di o de.is prepared on a GeOI substrate 301, a nd a P regi on 3 04 and a n N region 3 …
FIG. 3 is a st ru ctural schemati c view of a se ii icond u ctor substrate o f a GeOI base frequency reco n figur a ble coupling ty pe feeding loop antenna b …
FIG. 4 is a struc tural schematic view of a dielectric plate of a l oop antenna provided by an embodiment of the discl osu re. [0048]
FIG. 5 is a structural schematic view of a GaAs/Ge/GaAs based heterogeneous SPiN diode provided by an embodiment of the disclosure. [0049]
FIG. 6 is a str u ctural schematic view of a GaAs/Ge/GaAs based heterogeneous SPiN diode string provided by an embodiment of the disclosure. [0050]
FIGS. 7A to 7R are schematic views of a preparation method f o r a GaAs/Ge/GaAs heterogeneous SP iN di o de according to an e mbodiment of the disclosure. On …
FIG. 8 is a structural schematic view of another GaAs/Ge/GaAs based heterogeneous SP i N diode according to an embodiment of the disclosure. DETAILED DESCRIPTI …
FIG. 70, depositing a Si O 2 1501 with a thickness of 800 nm on the surface by a CVD method; and [00 118] (4h) at 1000 degrees Celsius, annealing f o r 1 …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A preparation method for a GaAs/Ge/GaAs heterogeneous spintronic (SPiN) diode for a loop antenna, wherein the loop antenna comprises: a semiconductor substrate; a dielectric plate; a first SPiN diode ring, a second SPiN diode ring, first direct current (DC) bias wires and second DC bias wires, disposed on the semiconductor substrate; and a coupling type feed source, disposed on the dielectric plate; wherein,, the first DC bias wires and the second DC bias wires are formed on the semiconductor substrate by heavily doping process; wherein the preparation method for the SPiN diode comprises following steps of: (a) selecting a germanium-on-insulator (Ge O I) substrate; (b) etching a top Ge layer of the Ge O I substrate to form a first trench and a second trench in the top Ge layer; (c) depositing a gallium arsenide (GaAs) material in the first trench and the second trench; (d) performing P-type ion implantation into the GaAs material in the first trench to form a P-type active region and performing an N-type ion implantation into the GaAs material in the second trench to form an N-type active region, by ion implantation process; and (e) forming lead holes on surfaces of the P-type active region and the N-type active region and then sputtering a metal, to form the GaAs/Ge/GaAs heterogeneous SPiN diode. Currently amended
The preparation method according to claim 1, before the step (b), further comprising: (x1) preparing a silicon oxide (SiO₂) material on a surface of the Ge O I substrate to form a first SiO₂ layer; (x2) preparing a silicon nitride (SiN) material on a surface of the first SiO₂ layer to form a first SiN layer, to thereby form a first protective layer; (x3) etching the first protective layer and the Ge O I substrate by dry etching with a first mask, to form isolation trenches in the Ge O I substrate; (x4) filling the isolation trenches with an isolation material by a chemical vapor deposition (CVD) process; and (x5) removing the first protective layer and the isolation material outside the isolation trenches by a chemical mechanical polishing (CMP) process, to form an isolation region of the GaAs/Ge/GaAs heterogeneous SPiN diode. Original
The preparation method according to claim 1, wherein the step (b) comprises: (b1) preparing a SiO₂ material on a surface of the Ge O I substrate to form a second SiO₂ layer; (b2) preparing a SiN material on a surface of the second Si O₂ layer to form a second SiN layer, and thereby forming a second protective layer; and (b3) etching the second protective layer and the top Ge layer by anisotropic etching with a second mask, to form the first trench and the second trench in the top Ge layer. Original
The preparation method according to claim 1, before the step (c), further comprising: (yl) at 800-900 degrees Celsius, oxidizing the first trench and the second trench to form oxide layers on inner walls of the first trench and the second trench; and (y2) etching the oxide layers on the inner walls of the first trench and the second trench by a wet etching process to planarize the inner walls of first trench and the second trench. Original
The preparation method according to claim 1, wherein the step (c) comprises: (cl) depositing the GaAs material in the first trench and the second trenches by a metal- organic chemical vapor deposition (MOCVD) process; (c2) removing the GaAs material of a certain thickness outside the first trench and the second trench by a CMP process to planarize the first trench and the second trench. Original
The preparation method according to claim 1, wherein the step (d) comprises: (dl) performing a boron (B) ion implantation into the GaAs material in the first trench by an ion implantation process with a third mask, to form the P-type active region; (d2) performing a phosphorus (P) ion implantation into the GaAs material in the second trench by an ion implantation process with a fourth mask, to form the N-type active region; (d3) depositing a SiO₂ material on surfaces of the P-type active region and the N-type active region and activating impurities of the P-type active region and the N-type active region by an annealing process; and (d4) removing the SiO₂ material. Original
The preparation method according to claim 1, wherein the step (e) comprises: (el) depositing a SiO₂ material on an entire surface of the Ge O I substrate; (e2) etching off the SiO₂ material in part of positions in surfaces of the P-type active region and the N-type active region by an anisotropic etching process with a fifth mask, to form the lead holes; (e3) sputtering a metal material in the lead holes; and (e4) performing a passivation treatment and forming PAD s by photolithography, to form the GaAs/Ge/GaAs heterogeneous SPiN diode. Original
The preparation method according to claim 1, wherein the first SPiN diode ring comprises first SPiN diode strings, the second SPiN diode ring comprises second SPiN diode strings, and a perimeter of each of the first SPiN diode ring and the second SPiN diode ring is equal to an electromagnetic wavelength of a signal to be received. Original
The preparation method according to claim 1, wherein the coupling type feed source is formed on the dielectric plate; and the dielectric plate is provided with a metal microstrip patch on an upper surface and a metal grounding plate on a lower surface. Original
Layer stacks claimed or described, ordered top of device to substrate.
GaAs/Ge/GaAs heterogeneous SPiN diode
Materials described outside the worked examples.
gallium arsenide
GaAs
germanium
Ge
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 7A to 7R are schematic views of a preparation method f o r a GaAs/Ge/GaAs heterogeneous SP iN di o de according to an e mbodiment of the disclosure. On …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0–500 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,367,247Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1- is a structural schematic view of a rec o nfigurable loop antenna according to an embodiment of the disclosure. [0045] FI G. 2 is a flowchart of a …
FIG. 2. Speci f ica l ly, t h e Ga As/Ge/GaAs h eter o gene ou s S P iN di o de.is prepared on a GeOI substrate 301, a nd a P regi on 3 04 and a n N region 3 …
FIG. 3 is a st ru ctural schemati c view of a se ii icond u ctor substrate o f a GeOI base frequency reco n figur a ble coupling ty pe feeding loop antenna b …
FIG. 4 is a struc tural schematic view of a dielectric plate of a l oop antenna provided by an embodiment of the discl osu re. [0048]
FIG. 5 is a structural schematic view of a GaAs/Ge/GaAs based heterogeneous SPiN diode provided by an embodiment of the disclosure. [0049]
FIG. 6 is a str u ctural schematic view of a GaAs/Ge/GaAs based heterogeneous SPiN diode string provided by an embodiment of the disclosure. [0050]
FIGS. 7A to 7R are schematic views of a preparation method f o r a GaAs/Ge/GaAs heterogeneous SP iN di o de according to an e mbodiment of the disclosure. On …
FIG. 8 is a structural schematic view of another GaAs/Ge/GaAs based heterogeneous SP i N diode according to an embodiment of the disclosure. DETAILED DESCRIPTI …
FIG. 70, depositing a Si O 2 1501 with a thickness of 800 nm on the surface by a CVD method; and [00 118] (4h) at 1000 degrees Celsius, annealing f o r 1 …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A preparation method for a GaAs/Ge/GaAs heterogeneous spintronic (SPiN) diode for a loop antenna, wherein the loop antenna comprises: a semiconductor substrate; a dielectric plate; a first SPiN diode ring, a second SPiN diode ring, first direct current (DC) bias wires and second DC bias wires, disposed on the semiconductor substrate; and a coupling type feed source, disposed on the dielectric plate; wherein,, the first DC bias wires and the second DC bias wires are formed on the semiconductor substrate by heavily doping process; wherein the preparation method for the SPiN diode comprises following steps of: (a) selecting a germanium-on-insulator (Ge O I) substrate; (b) etching a top Ge layer of the Ge O I substrate to form a first trench and a second trench in the top Ge layer; (c) depositing a gallium arsenide (GaAs) material in the first trench and the second trench; (d) performing P-type ion implantation into the GaAs material in the first trench to form a P-type active region and performing an N-type ion implantation into the GaAs material in the second trench to form an N-type active region, by ion implantation process; and (e) forming lead holes on surfaces of the P-type active region and the N-type active region and then sputtering a metal, to form the GaAs/Ge/GaAs heterogeneous SPiN diode. Currently amended
The preparation method according to claim 1, before the step (b), further comprising: (x1) preparing a silicon oxide (SiO₂) material on a surface of the Ge O I substrate to form a first SiO₂ layer; (x2) preparing a silicon nitride (SiN) material on a surface of the first SiO₂ layer to form a first SiN layer, to thereby form a first protective layer; (x3) etching the first protective layer and the Ge O I substrate by dry etching with a first mask, to form isolation trenches in the Ge O I substrate; (x4) filling the isolation trenches with an isolation material by a chemical vapor deposition (CVD) process; and (x5) removing the first protective layer and the isolation material outside the isolation trenches by a chemical mechanical polishing (CMP) process, to form an isolation region of the GaAs/Ge/GaAs heterogeneous SPiN diode. Original
The preparation method according to claim 1, wherein the step (b) comprises: (b1) preparing a SiO₂ material on a surface of the Ge O I substrate to form a second SiO₂ layer; (b2) preparing a SiN material on a surface of the second Si O₂ layer to form a second SiN layer, and thereby forming a second protective layer; and (b3) etching the second protective layer and the top Ge layer by anisotropic etching with a second mask, to form the first trench and the second trench in the top Ge layer. Original
The preparation method according to claim 1, before the step (c), further comprising: (yl) at 800-900 degrees Celsius, oxidizing the first trench and the second trench to form oxide layers on inner walls of the first trench and the second trench; and (y2) etching the oxide layers on the inner walls of the first trench and the second trench by a wet etching process to planarize the inner walls of first trench and the second trench. Original
The preparation method according to claim 1, wherein the step (c) comprises: (cl) depositing the GaAs material in the first trench and the second trenches by a metal- organic chemical vapor deposition (MOCVD) process; (c2) removing the GaAs material of a certain thickness outside the first trench and the second trench by a CMP process to planarize the first trench and the second trench. Original
The preparation method according to claim 1, wherein the step (d) comprises: (dl) performing a boron (B) ion implantation into the GaAs material in the first trench by an ion implantation process with a third mask, to form the P-type active region; (d2) performing a phosphorus (P) ion implantation into the GaAs material in the second trench by an ion implantation process with a fourth mask, to form the N-type active region; (d3) depositing a SiO₂ material on surfaces of the P-type active region and the N-type active region and activating impurities of the P-type active region and the N-type active region by an annealing process; and (d4) removing the SiO₂ material. Original
The preparation method according to claim 1, wherein the step (e) comprises: (el) depositing a SiO₂ material on an entire surface of the Ge O I substrate; (e2) etching off the SiO₂ material in part of positions in surfaces of the P-type active region and the N-type active region by an anisotropic etching process with a fifth mask, to form the lead holes; (e3) sputtering a metal material in the lead holes; and (e4) performing a passivation treatment and forming PAD s by photolithography, to form the GaAs/Ge/GaAs heterogeneous SPiN diode. Original
The preparation method according to claim 1, wherein the first SPiN diode ring comprises first SPiN diode strings, the second SPiN diode ring comprises second SPiN diode strings, and a perimeter of each of the first SPiN diode ring and the second SPiN diode ring is equal to an electromagnetic wavelength of a signal to be received. Original
The preparation method according to claim 1, wherein the coupling type feed source is formed on the dielectric plate; and the dielectric plate is provided with a metal microstrip patch on an upper surface and a metal grounding plate on a lower surface. Original
Layer stacks claimed or described, ordered top of device to substrate.
GaAs/Ge/GaAs heterogeneous SPiN diode
Materials described outside the worked examples.
gallium arsenide
GaAs
germanium
Ge
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIGS. 7A to 7R are schematic views of a preparation method f o r a GaAs/Ge/GaAs heterogeneous SP iN di o de according to an e mbodiment of the disclosure. On …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 0–500 nm | — |
Related documents with shared materials, methods, properties, or citations.
germanium-on-insulator substrate
silicon oxide
SiO₂
silicon nitride
SiN
boron
B
phosphorus
P
metal
FIG. 70, depositing a Si O 2 1501 with a thickness of 800 nm on the surface by a CVD method; and [00 118] (4h) at 1000 degrees Celsius, annealing f o r 1 …
germanium-on-insulator substrate
silicon oxide
SiO₂
silicon nitride
SiN
boron
B
phosphorus
P
metal
FIG. 70, depositing a Si O 2 1501 with a thickness of 800 nm on the surface by a CVD method; and [00 118] (4h) at 1000 degrees Celsius, annealing f o r 1 …
germanium-on-insulator substrate
silicon oxide
SiO₂
silicon nitride
SiN
boron
B
phosphorus
P
metal
FIG. 70, depositing a Si O 2 1501 with a thickness of 800 nm on the surface by a CVD method; and [00 118] (4h) at 1000 degrees Celsius, annealing f o r 1 …
germanium-on-insulator substrate
silicon oxide
SiO₂
silicon nitride
SiN
boron
B
phosphorus
P
metal
FIG. 70, depositing a Si O 2 1501 with a thickness of 800 nm on the surface by a CVD method; and [00 118] (4h) at 1000 degrees Celsius, annealing f o r 1 …