Patent
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 2 is a cross-sectional view of the semiconductor structure after native oxide has been removed from the substrate according to one embodiment of the …
FIG. 3. In one embodiment, a monolayer of sulfur is formed on the treated surface 202 with a thickness of 0.4 nm. However, other thicknesses are applicable as …
FIG. 4. In other embodiments, the passivation layer 302 is removed from the top surface 202 using, for example, an acid etch or a planarization process. This …
FIG. 5. [0022] An optional capping/dielectric layer 602 is then formed on and in contact with the structure 100, as shown in FIG s. 6 to 8. In one embodiment, …
FIG. 6 shows that in an embodiment where the passivation layer 302 contacts the top surface 202 and sidewalls 304, 406 of the semiconductor material 104, the …
FIG. 8 shows that in an embodiment, where the passivation layer 302 has been removed from the top surface 202 of the semiconductor material 1 04 but remains in …
FIG. 9 is an operational flow diagram illustrating one process for fabricating a semiconductor structure comprising a thiourea-passivated surface according to …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a gallium arsenide substrate; a thiourea-based passivation layer in contact with the entire top surface of the gallium arsenide substrate and further in contact with and surrounding each sidewall of the gallium arsenide substrate; and a capping layer in contact with the top surface of the thiourea-based passivation layer and further in contact with and surrounding each sidewall of the thiourea-based passivation layer. Previously presented
The semiconductor structure of claim 1, wherein the capping layer comprises one of aluminum oxide or hafnium oxide. Original
The semiconductor structure of claim 1, wherein an interface between the thiourea-based passivation layer and the capping layer has been annealed. Original
The semiconductor structure of claim 1, wherein the thiourea-based passivation layer comprises sulfur. Original
Canceled
Canceled
Canceled
An integrated circuit comprising: at least one semiconductor structure, wherein the semiconductor structure comprises at least a gallium arsenide substrate; a thiourea-based passivation layer in contact with the entire top surface of the gallium arsenide substrate and each sidewall of the gallium arsenide substrate; and a capping layer in contact with a top surface of the thiourea-based passivation layer and further in contact with and surrounding each sidewall of the thiourea-based passivation layer. Previously presented
The integrated circuit of claim 8, wherein the capping layer comprises one of aluminum oxide or hafnium oxide. Original
The integrated circuit of claim 8, wherein an interface between the thiourea-based passivation layer and the capping layer has been annealed. Original
The integrated circuit of claim 8, wherein the thiourea-based passivation layer comprises sulfur. Original
Canceled
Canceled
Canceled
A semiconductor structure comprising: a gallium arsenide substrate; a thiourea-based passivation layer fully surrounding the entire top surface of the gallium arsenide substrate and each sidewall of the gallium arsenide substrate; and a capping layer in contact with and fully surrounding the thiourea-based passivation layer. Currently amended
The semiconductor structure of claim 15, wherein the capping layer comprises one of aluminum oxide or hafnium oxide. Previously presented
The semiconductor structure of claim 15, wherein an interface between the thiourea-based passivation layer and the capping layer has been annealed. Original
The semiconductor structure of claim 15, wherein the thiourea-based passivation layer comprises sulfur. Original
The semiconductor structure of claim 15, wherein the gallium arsenide substrate is free of a native oxide. Previously presented
Canceled
Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
passivated GaAs semiconductor structure (top and sidewall passivation)
integrated circuit with passivated GaAs semiconductor structure
Materials described outside the worked examples.
gallium arsenide substrate
GaAs
thiourea-based passivation layer
SC(NH₂)2
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3. In one embodiment, a monolayer of sulfur is formed on the treated surface 202 with a thickness of 0.4 nm. However, other thicknesses are applicable as …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 2–20 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 2 is a cross-sectional view of the semiconductor structure after native oxide has been removed from the substrate according to one embodiment of the …
FIG. 3. In one embodiment, a monolayer of sulfur is formed on the treated surface 202 with a thickness of 0.4 nm. However, other thicknesses are applicable as …
FIG. 4. In other embodiments, the passivation layer 302 is removed from the top surface 202 using, for example, an acid etch or a planarization process. This …
FIG. 5. [0022] An optional capping/dielectric layer 602 is then formed on and in contact with the structure 100, as shown in FIG s. 6 to 8. In one embodiment, …
FIG. 6 shows that in an embodiment where the passivation layer 302 contacts the top surface 202 and sidewalls 304, 406 of the semiconductor material 104, the …
FIG. 8 shows that in an embodiment, where the passivation layer 302 has been removed from the top surface 202 of the semiconductor material 1 04 but remains in …
FIG. 9 is an operational flow diagram illustrating one process for fabricating a semiconductor structure comprising a thiourea-passivated surface according to …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a gallium arsenide substrate; a thiourea-based passivation layer in contact with the entire top surface of the gallium arsenide substrate and further in contact with and surrounding each sidewall of the gallium arsenide substrate; and a capping layer in contact with the top surface of the thiourea-based passivation layer and further in contact with and surrounding each sidewall of the thiourea-based passivation layer. Previously presented
The semiconductor structure of claim 1, wherein the capping layer comprises one of aluminum oxide or hafnium oxide. Original
The semiconductor structure of claim 1, wherein an interface between the thiourea-based passivation layer and the capping layer has been annealed. Original
The semiconductor structure of claim 1, wherein the thiourea-based passivation layer comprises sulfur. Original
Canceled
Canceled
Canceled
An integrated circuit comprising: at least one semiconductor structure, wherein the semiconductor structure comprises at least a gallium arsenide substrate; a thiourea-based passivation layer in contact with the entire top surface of the gallium arsenide substrate and each sidewall of the gallium arsenide substrate; and a capping layer in contact with a top surface of the thiourea-based passivation layer and further in contact with and surrounding each sidewall of the thiourea-based passivation layer. Previously presented
The integrated circuit of claim 8, wherein the capping layer comprises one of aluminum oxide or hafnium oxide. Original
The integrated circuit of claim 8, wherein an interface between the thiourea-based passivation layer and the capping layer has been annealed. Original
The integrated circuit of claim 8, wherein the thiourea-based passivation layer comprises sulfur. Original
Canceled
Canceled
Canceled
A semiconductor structure comprising: a gallium arsenide substrate; a thiourea-based passivation layer fully surrounding the entire top surface of the gallium arsenide substrate and each sidewall of the gallium arsenide substrate; and a capping layer in contact with and fully surrounding the thiourea-based passivation layer. Currently amended
The semiconductor structure of claim 15, wherein the capping layer comprises one of aluminum oxide or hafnium oxide. Previously presented
The semiconductor structure of claim 15, wherein an interface between the thiourea-based passivation layer and the capping layer has been annealed. Original
The semiconductor structure of claim 15, wherein the thiourea-based passivation layer comprises sulfur. Original
The semiconductor structure of claim 15, wherein the gallium arsenide substrate is free of a native oxide. Previously presented
Canceled
Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
passivated GaAs semiconductor structure (top and sidewall passivation)
integrated circuit with passivated GaAs semiconductor structure
Materials described outside the worked examples.
gallium arsenide substrate
GaAs
thiourea-based passivation layer
SC(NH₂)2
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3. In one embodiment, a monolayer of sulfur is formed on the treated surface 202 with a thickness of 0.4 nm. However, other thicknesses are applicable as …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 2–20 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 2 is a cross-sectional view of the semiconductor structure after native oxide has been removed from the substrate according to one embodiment of the …
FIG. 3. In one embodiment, a monolayer of sulfur is formed on the treated surface 202 with a thickness of 0.4 nm. However, other thicknesses are applicable as …
FIG. 4. In other embodiments, the passivation layer 302 is removed from the top surface 202 using, for example, an acid etch or a planarization process. This …
FIG. 5. [0022] An optional capping/dielectric layer 602 is then formed on and in contact with the structure 100, as shown in FIG s. 6 to 8. In one embodiment, …
FIG. 6 shows that in an embodiment where the passivation layer 302 contacts the top surface 202 and sidewalls 304, 406 of the semiconductor material 104, the …
FIG. 8 shows that in an embodiment, where the passivation layer 302 has been removed from the top surface 202 of the semiconductor material 1 04 but remains in …
FIG. 9 is an operational flow diagram illustrating one process for fabricating a semiconductor structure comprising a thiourea-passivated surface according to …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a gallium arsenide substrate; a thiourea-based passivation layer in contact with the entire top surface of the gallium arsenide substrate and further in contact with and surrounding each sidewall of the gallium arsenide substrate; and a capping layer in contact with the top surface of the thiourea-based passivation layer and further in contact with and surrounding each sidewall of the thiourea-based passivation layer. Previously presented
The semiconductor structure of claim 1, wherein the capping layer comprises one of aluminum oxide or hafnium oxide. Original
The semiconductor structure of claim 1, wherein an interface between the thiourea-based passivation layer and the capping layer has been annealed. Original
The semiconductor structure of claim 1, wherein the thiourea-based passivation layer comprises sulfur. Original
Canceled
Canceled
Canceled
An integrated circuit comprising: at least one semiconductor structure, wherein the semiconductor structure comprises at least a gallium arsenide substrate; a thiourea-based passivation layer in contact with the entire top surface of the gallium arsenide substrate and each sidewall of the gallium arsenide substrate; and a capping layer in contact with a top surface of the thiourea-based passivation layer and further in contact with and surrounding each sidewall of the thiourea-based passivation layer. Previously presented
The integrated circuit of claim 8, wherein the capping layer comprises one of aluminum oxide or hafnium oxide. Original
The integrated circuit of claim 8, wherein an interface between the thiourea-based passivation layer and the capping layer has been annealed. Original
The integrated circuit of claim 8, wherein the thiourea-based passivation layer comprises sulfur. Original
Canceled
Canceled
Canceled
A semiconductor structure comprising: a gallium arsenide substrate; a thiourea-based passivation layer fully surrounding the entire top surface of the gallium arsenide substrate and each sidewall of the gallium arsenide substrate; and a capping layer in contact with and fully surrounding the thiourea-based passivation layer. Currently amended
The semiconductor structure of claim 15, wherein the capping layer comprises one of aluminum oxide or hafnium oxide. Previously presented
The semiconductor structure of claim 15, wherein an interface between the thiourea-based passivation layer and the capping layer has been annealed. Original
The semiconductor structure of claim 15, wherein the thiourea-based passivation layer comprises sulfur. Original
The semiconductor structure of claim 15, wherein the gallium arsenide substrate is free of a native oxide. Previously presented
Canceled
Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
passivated GaAs semiconductor structure (top and sidewall passivation)
integrated circuit with passivated GaAs semiconductor structure
Materials described outside the worked examples.
gallium arsenide substrate
GaAs
thiourea-based passivation layer
SC(NH₂)2
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3. In one embodiment, a monolayer of sulfur is formed on the treated surface 202 with a thickness of 0.4 nm. However, other thicknesses are applicable as …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 2–20 nm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 2 is a cross-sectional view of the semiconductor structure after native oxide has been removed from the substrate according to one embodiment of the …
FIG. 3. In one embodiment, a monolayer of sulfur is formed on the treated surface 202 with a thickness of 0.4 nm. However, other thicknesses are applicable as …
FIG. 4. In other embodiments, the passivation layer 302 is removed from the top surface 202 using, for example, an acid etch or a planarization process. This …
FIG. 5. [0022] An optional capping/dielectric layer 602 is then formed on and in contact with the structure 100, as shown in FIG s. 6 to 8. In one embodiment, …
FIG. 6 shows that in an embodiment where the passivation layer 302 contacts the top surface 202 and sidewalls 304, 406 of the semiconductor material 104, the …
FIG. 8 shows that in an embodiment, where the passivation layer 302 has been removed from the top surface 202 of the semiconductor material 1 04 but remains in …
FIG. 9 is an operational flow diagram illustrating one process for fabricating a semiconductor structure comprising a thiourea-passivated surface according to …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor structure comprising: a gallium arsenide substrate; a thiourea-based passivation layer in contact with the entire top surface of the gallium arsenide substrate and further in contact with and surrounding each sidewall of the gallium arsenide substrate; and a capping layer in contact with the top surface of the thiourea-based passivation layer and further in contact with and surrounding each sidewall of the thiourea-based passivation layer. Previously presented
The semiconductor structure of claim 1, wherein the capping layer comprises one of aluminum oxide or hafnium oxide. Original
The semiconductor structure of claim 1, wherein an interface between the thiourea-based passivation layer and the capping layer has been annealed. Original
The semiconductor structure of claim 1, wherein the thiourea-based passivation layer comprises sulfur. Original
Canceled
Canceled
Canceled
An integrated circuit comprising: at least one semiconductor structure, wherein the semiconductor structure comprises at least a gallium arsenide substrate; a thiourea-based passivation layer in contact with the entire top surface of the gallium arsenide substrate and each sidewall of the gallium arsenide substrate; and a capping layer in contact with a top surface of the thiourea-based passivation layer and further in contact with and surrounding each sidewall of the thiourea-based passivation layer. Previously presented
The integrated circuit of claim 8, wherein the capping layer comprises one of aluminum oxide or hafnium oxide. Original
The integrated circuit of claim 8, wherein an interface between the thiourea-based passivation layer and the capping layer has been annealed. Original
The integrated circuit of claim 8, wherein the thiourea-based passivation layer comprises sulfur. Original
Canceled
Canceled
Canceled
A semiconductor structure comprising: a gallium arsenide substrate; a thiourea-based passivation layer fully surrounding the entire top surface of the gallium arsenide substrate and each sidewall of the gallium arsenide substrate; and a capping layer in contact with and fully surrounding the thiourea-based passivation layer. Currently amended
The semiconductor structure of claim 15, wherein the capping layer comprises one of aluminum oxide or hafnium oxide. Previously presented
The semiconductor structure of claim 15, wherein an interface between the thiourea-based passivation layer and the capping layer has been annealed. Original
The semiconductor structure of claim 15, wherein the thiourea-based passivation layer comprises sulfur. Original
The semiconductor structure of claim 15, wherein the gallium arsenide substrate is free of a native oxide. Previously presented
Canceled
Canceled
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
passivated GaAs semiconductor structure (top and sidewall passivation)
integrated circuit with passivated GaAs semiconductor structure
Materials described outside the worked examples.
gallium arsenide substrate
GaAs
thiourea-based passivation layer
SC(NH₂)2
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3. In one embodiment, a monolayer of sulfur is formed on the treated surface 202 with a thickness of 0.4 nm. However, other thicknesses are applicable as …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Thickness | 2–20 nm | — |
Related documents with shared materials, methods, properties, or citations.
passivated GaAs semiconductor structure (fully surrounding passivation and capping)
capping layer
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
sulfur
S
ammonium hydroxide
NH₄OH
titanium oxide
TiO₂
gallium oxide
Ga₂O₃
gadolinium oxide
Gd₂O₃
FIG. 5. [0022] An optional capping/dielectric layer 602 is then formed on and in contact with the structure 100, as shown in FIG s. 6 to 8. In one embodiment, …
passivated GaAs semiconductor structure (fully surrounding passivation and capping)
capping layer
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
sulfur
S
ammonium hydroxide
NH₄OH
titanium oxide
TiO₂
gallium oxide
Ga₂O₃
gadolinium oxide
Gd₂O₃
FIG. 5. [0022] An optional capping/dielectric layer 602 is then formed on and in contact with the structure 100, as shown in FIG s. 6 to 8. In one embodiment, …
passivated GaAs semiconductor structure (fully surrounding passivation and capping)
capping layer
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
sulfur
S
ammonium hydroxide
NH₄OH
titanium oxide
TiO₂
gallium oxide
Ga₂O₃
gadolinium oxide
Gd₂O₃
FIG. 5. [0022] An optional capping/dielectric layer 602 is then formed on and in contact with the structure 100, as shown in FIG s. 6 to 8. In one embodiment, …
passivated GaAs semiconductor structure (fully surrounding passivation and capping)
capping layer
aluminum oxide
Al₂O₃
hafnium oxide
HfO₂
sulfur
S
ammonium hydroxide
NH₄OH
titanium oxide
TiO₂
gallium oxide
Ga₂O₃
gadolinium oxide
Gd₂O₃
FIG. 5. [0022] An optional capping/dielectric layer 602 is then formed on and in contact with the structure 100, as shown in FIG s. 6 to 8. In one embodiment, …