Patent
US 11,522,525RECONFIGURABLE GALLIUM NITRIDE (GAN) ROTATING COEFFICIENTS FIR FILTER FOR CO-SITE INTERFERENCE MITIGATION
Ajay Subramanian
US
Copyright © 2026 Matter42. All rights reserved.
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US 11,522,525Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a functional block diagram of a FIR filter 100 in accordance with aspects described herein. In one example, the FIR filter 100 includes a …
FIG. 2B illustrates examples of tap coefficients corresponding to different tap quantities that can be stored in the coefficient rotation table. In some examples, …
FIG. 3A illustrates a schematic diagram of a sample-and-hold circuit 300 in accordance with aspects described herein. In one example, the sample-and-hold …
FIG. 4 illustrates a schematic diagram of a multiplier circuit 400 in accordance with aspects described herein. In one example, the multiplier circuit 400 …
FIG. 5 illustrates a schematic diagram of an adder circuit 500 in accordance with aspects described herein. In one example, the adder circuit 500 corresponds …
FIG. 6A in accordance with aspects described herein; DETA I LED DESCRIPTION It is to be appreciated that embodiments of the methods and apparatuses discussed …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) A finite impulse response (FIR) filter comprising: an input of the FIR filter that receives an RF input signal; a clock input configured to receive a clock signal; an output of the FIR filter that provides a filtered output signal; a plurality of signal paths including a plurality of sample-and-hold circuits and [[a]] the plurality of multipliers a rr anged in parallel, each signal path including a respective sample-and- hold circuit and a respective multiplier being configured to receive the RF input signal and the clock signal to provide a modulated output signal, each respective signal path of the plurality of signal paths receiving the clock signal according to a respective clock signal delay, each clock signal delay different from each other clock signal delay, and each multiplier of each signal path receiving a respective tap coefficient signal having a respective tap coefficient delay corresponding to the respective signal path; an adder configured to receive n modulated output signals from the plurality of signal paths and combine the n modulated output signals to produce the filtered output signal; and a controller. Currently amended
The FIR filter of claim 1, further comprising a plurality of switches, each switch of the plurality of switches being coupled to the controller and configured to selectively connect and disconnect at least one signal path of the plurality of signal paths. Original
The FIR filter of claim 1, wherein the plurality of sample-and-hold circuits and the plurality of multipliers include one or more Gallium Nitride (GaN) devices configured to provide linear operation of the FIR filter. Original
Canceled
(Cu rr ently Amended) The FIR filter of claim [[5]] 1, wherein the plurality of sample-and-hold circuits are further configured to sample the RF input signal based on the respective clock signal delays of the signal paths to provide a plurality of sampled output signals. Currently amended
(Cu rr ently Amended) The FIR filter of claim 6, wherein the plurality of multipliers are configured to multiply the sampled output signals with a respective tap coefficient value of the respective tap coefficient signal to provide a plurality of modulated output signals. Currently amended
(Cu rr ently Amended) An analog cancellation module including a finite impulse response (FIR) filter for use in a transceiver system, the analog cancellation module comprising: an input of the analog cancellation module that receives an RF input signal, the RF input signal corresponding to a transmit signal provided to a transmit path of the transceiver system; an output of the analog cancellation module that provides a cancellation signal to a receive path of the transceiver system to cancel transmit signal interference; the FIR filter including a plurality of signal paths configured to provide a synthesized frequency response corresponding to the receive path and an adder, each signal path including a respective sample-and-hold circuit and a respective multiplier configured to receive the RF input signal and provide a modulated output signal, each signal path of the plurality of signal paths receiving the clock signal according to a respective clock signal delay, each clock signal delay different from each other clock signal delay, and each multiplier of each signal path being configured to receive a respective tap coefficient signal having a respective tap coefficient delay corresponding to the clock signal delay of the signal path, and the adder being configured to receive n modulated output signals from the plurality of signal paths and combine the n modulated output signals to provide the cancellation signal; and a controller. Currently amended
The analog cancellation module of claim 16, wherein each sample-and- hold circuit and multiplier of the FIR filter includes one or more Gallium Nitride (GaN) devices configured to provide linear operation of the FIR filter. Original
The analog cancellation module of claim [[18]] 16, wherein the FIR filter further includes a plurality of switches coupled to the controller and configured to selectively connect and disconnect at least one signal path of the plurality of signal paths. Currently amended
The analog cancellation module of claim 18, wherein the controller and the plurality of switches of the FIR filter are configured to be controllable and to be operated to adjust a value of n. Original
Layer stacks claimed or described, ordered top of device to substrate.
FIR filter
No layer stack recorded.
GaN HEMT sample-and-hold circuit with gate-bootstrapping stage
analog cancellation module with FIR filter for transceiver system
No layer stack recorded.
Materials described outside the worked examples.
Gallium Nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3A illustrates a schematic diagram of a sample-and-hold circuit 300 in accordance with aspects described herein. In one example, the sample-and-hold …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,522,525Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a functional block diagram of a FIR filter 100 in accordance with aspects described herein. In one example, the FIR filter 100 includes a …
FIG. 2B illustrates examples of tap coefficients corresponding to different tap quantities that can be stored in the coefficient rotation table. In some examples, …
FIG. 3A illustrates a schematic diagram of a sample-and-hold circuit 300 in accordance with aspects described herein. In one example, the sample-and-hold …
FIG. 4 illustrates a schematic diagram of a multiplier circuit 400 in accordance with aspects described herein. In one example, the multiplier circuit 400 …
FIG. 5 illustrates a schematic diagram of an adder circuit 500 in accordance with aspects described herein. In one example, the adder circuit 500 corresponds …
FIG. 6A in accordance with aspects described herein; DETA I LED DESCRIPTION It is to be appreciated that embodiments of the methods and apparatuses discussed …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) A finite impulse response (FIR) filter comprising: an input of the FIR filter that receives an RF input signal; a clock input configured to receive a clock signal; an output of the FIR filter that provides a filtered output signal; a plurality of signal paths including a plurality of sample-and-hold circuits and [[a]] the plurality of multipliers a rr anged in parallel, each signal path including a respective sample-and- hold circuit and a respective multiplier being configured to receive the RF input signal and the clock signal to provide a modulated output signal, each respective signal path of the plurality of signal paths receiving the clock signal according to a respective clock signal delay, each clock signal delay different from each other clock signal delay, and each multiplier of each signal path receiving a respective tap coefficient signal having a respective tap coefficient delay corresponding to the respective signal path; an adder configured to receive n modulated output signals from the plurality of signal paths and combine the n modulated output signals to produce the filtered output signal; and a controller. Currently amended
The FIR filter of claim 1, further comprising a plurality of switches, each switch of the plurality of switches being coupled to the controller and configured to selectively connect and disconnect at least one signal path of the plurality of signal paths. Original
The FIR filter of claim 1, wherein the plurality of sample-and-hold circuits and the plurality of multipliers include one or more Gallium Nitride (GaN) devices configured to provide linear operation of the FIR filter. Original
Canceled
(Cu rr ently Amended) The FIR filter of claim [[5]] 1, wherein the plurality of sample-and-hold circuits are further configured to sample the RF input signal based on the respective clock signal delays of the signal paths to provide a plurality of sampled output signals. Currently amended
(Cu rr ently Amended) The FIR filter of claim 6, wherein the plurality of multipliers are configured to multiply the sampled output signals with a respective tap coefficient value of the respective tap coefficient signal to provide a plurality of modulated output signals. Currently amended
(Cu rr ently Amended) An analog cancellation module including a finite impulse response (FIR) filter for use in a transceiver system, the analog cancellation module comprising: an input of the analog cancellation module that receives an RF input signal, the RF input signal corresponding to a transmit signal provided to a transmit path of the transceiver system; an output of the analog cancellation module that provides a cancellation signal to a receive path of the transceiver system to cancel transmit signal interference; the FIR filter including a plurality of signal paths configured to provide a synthesized frequency response corresponding to the receive path and an adder, each signal path including a respective sample-and-hold circuit and a respective multiplier configured to receive the RF input signal and provide a modulated output signal, each signal path of the plurality of signal paths receiving the clock signal according to a respective clock signal delay, each clock signal delay different from each other clock signal delay, and each multiplier of each signal path being configured to receive a respective tap coefficient signal having a respective tap coefficient delay corresponding to the clock signal delay of the signal path, and the adder being configured to receive n modulated output signals from the plurality of signal paths and combine the n modulated output signals to provide the cancellation signal; and a controller. Currently amended
The analog cancellation module of claim 16, wherein each sample-and- hold circuit and multiplier of the FIR filter includes one or more Gallium Nitride (GaN) devices configured to provide linear operation of the FIR filter. Original
The analog cancellation module of claim [[18]] 16, wherein the FIR filter further includes a plurality of switches coupled to the controller and configured to selectively connect and disconnect at least one signal path of the plurality of signal paths. Currently amended
The analog cancellation module of claim 18, wherein the controller and the plurality of switches of the FIR filter are configured to be controllable and to be operated to adjust a value of n. Original
Layer stacks claimed or described, ordered top of device to substrate.
FIR filter
No layer stack recorded.
GaN HEMT sample-and-hold circuit with gate-bootstrapping stage
analog cancellation module with FIR filter for transceiver system
No layer stack recorded.
Materials described outside the worked examples.
Gallium Nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3A illustrates a schematic diagram of a sample-and-hold circuit 300 in accordance with aspects described herein. In one example, the sample-and-hold …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,522,525Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a functional block diagram of a FIR filter 100 in accordance with aspects described herein. In one example, the FIR filter 100 includes a …
FIG. 2B illustrates examples of tap coefficients corresponding to different tap quantities that can be stored in the coefficient rotation table. In some examples, …
FIG. 3A illustrates a schematic diagram of a sample-and-hold circuit 300 in accordance with aspects described herein. In one example, the sample-and-hold …
FIG. 4 illustrates a schematic diagram of a multiplier circuit 400 in accordance with aspects described herein. In one example, the multiplier circuit 400 …
FIG. 5 illustrates a schematic diagram of an adder circuit 500 in accordance with aspects described herein. In one example, the adder circuit 500 corresponds …
FIG. 6A in accordance with aspects described herein; DETA I LED DESCRIPTION It is to be appreciated that embodiments of the methods and apparatuses discussed …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) A finite impulse response (FIR) filter comprising: an input of the FIR filter that receives an RF input signal; a clock input configured to receive a clock signal; an output of the FIR filter that provides a filtered output signal; a plurality of signal paths including a plurality of sample-and-hold circuits and [[a]] the plurality of multipliers a rr anged in parallel, each signal path including a respective sample-and- hold circuit and a respective multiplier being configured to receive the RF input signal and the clock signal to provide a modulated output signal, each respective signal path of the plurality of signal paths receiving the clock signal according to a respective clock signal delay, each clock signal delay different from each other clock signal delay, and each multiplier of each signal path receiving a respective tap coefficient signal having a respective tap coefficient delay corresponding to the respective signal path; an adder configured to receive n modulated output signals from the plurality of signal paths and combine the n modulated output signals to produce the filtered output signal; and a controller. Currently amended
The FIR filter of claim 1, further comprising a plurality of switches, each switch of the plurality of switches being coupled to the controller and configured to selectively connect and disconnect at least one signal path of the plurality of signal paths. Original
The FIR filter of claim 1, wherein the plurality of sample-and-hold circuits and the plurality of multipliers include one or more Gallium Nitride (GaN) devices configured to provide linear operation of the FIR filter. Original
Canceled
(Cu rr ently Amended) The FIR filter of claim [[5]] 1, wherein the plurality of sample-and-hold circuits are further configured to sample the RF input signal based on the respective clock signal delays of the signal paths to provide a plurality of sampled output signals. Currently amended
(Cu rr ently Amended) The FIR filter of claim 6, wherein the plurality of multipliers are configured to multiply the sampled output signals with a respective tap coefficient value of the respective tap coefficient signal to provide a plurality of modulated output signals. Currently amended
(Cu rr ently Amended) An analog cancellation module including a finite impulse response (FIR) filter for use in a transceiver system, the analog cancellation module comprising: an input of the analog cancellation module that receives an RF input signal, the RF input signal corresponding to a transmit signal provided to a transmit path of the transceiver system; an output of the analog cancellation module that provides a cancellation signal to a receive path of the transceiver system to cancel transmit signal interference; the FIR filter including a plurality of signal paths configured to provide a synthesized frequency response corresponding to the receive path and an adder, each signal path including a respective sample-and-hold circuit and a respective multiplier configured to receive the RF input signal and provide a modulated output signal, each signal path of the plurality of signal paths receiving the clock signal according to a respective clock signal delay, each clock signal delay different from each other clock signal delay, and each multiplier of each signal path being configured to receive a respective tap coefficient signal having a respective tap coefficient delay corresponding to the clock signal delay of the signal path, and the adder being configured to receive n modulated output signals from the plurality of signal paths and combine the n modulated output signals to provide the cancellation signal; and a controller. Currently amended
The analog cancellation module of claim 16, wherein each sample-and- hold circuit and multiplier of the FIR filter includes one or more Gallium Nitride (GaN) devices configured to provide linear operation of the FIR filter. Original
The analog cancellation module of claim [[18]] 16, wherein the FIR filter further includes a plurality of switches coupled to the controller and configured to selectively connect and disconnect at least one signal path of the plurality of signal paths. Currently amended
The analog cancellation module of claim 18, wherein the controller and the plurality of switches of the FIR filter are configured to be controllable and to be operated to adjust a value of n. Original
Layer stacks claimed or described, ordered top of device to substrate.
FIR filter
No layer stack recorded.
GaN HEMT sample-and-hold circuit with gate-bootstrapping stage
analog cancellation module with FIR filter for transceiver system
No layer stack recorded.
Materials described outside the worked examples.
Gallium Nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3A illustrates a schematic diagram of a sample-and-hold circuit 300 in accordance with aspects described herein. In one example, the sample-and-hold …
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,522,525Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a functional block diagram of a FIR filter 100 in accordance with aspects described herein. In one example, the FIR filter 100 includes a …
FIG. 2B illustrates examples of tap coefficients corresponding to different tap quantities that can be stored in the coefficient rotation table. In some examples, …
FIG. 3A illustrates a schematic diagram of a sample-and-hold circuit 300 in accordance with aspects described herein. In one example, the sample-and-hold …
FIG. 4 illustrates a schematic diagram of a multiplier circuit 400 in accordance with aspects described herein. In one example, the multiplier circuit 400 …
FIG. 5 illustrates a schematic diagram of an adder circuit 500 in accordance with aspects described herein. In one example, the adder circuit 500 corresponds …
FIG. 6A in accordance with aspects described herein; DETA I LED DESCRIPTION It is to be appreciated that embodiments of the methods and apparatuses discussed …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
(Cu rr ently Amended) A finite impulse response (FIR) filter comprising: an input of the FIR filter that receives an RF input signal; a clock input configured to receive a clock signal; an output of the FIR filter that provides a filtered output signal; a plurality of signal paths including a plurality of sample-and-hold circuits and [[a]] the plurality of multipliers a rr anged in parallel, each signal path including a respective sample-and- hold circuit and a respective multiplier being configured to receive the RF input signal and the clock signal to provide a modulated output signal, each respective signal path of the plurality of signal paths receiving the clock signal according to a respective clock signal delay, each clock signal delay different from each other clock signal delay, and each multiplier of each signal path receiving a respective tap coefficient signal having a respective tap coefficient delay corresponding to the respective signal path; an adder configured to receive n modulated output signals from the plurality of signal paths and combine the n modulated output signals to produce the filtered output signal; and a controller. Currently amended
The FIR filter of claim 1, further comprising a plurality of switches, each switch of the plurality of switches being coupled to the controller and configured to selectively connect and disconnect at least one signal path of the plurality of signal paths. Original
The FIR filter of claim 1, wherein the plurality of sample-and-hold circuits and the plurality of multipliers include one or more Gallium Nitride (GaN) devices configured to provide linear operation of the FIR filter. Original
Canceled
(Cu rr ently Amended) The FIR filter of claim [[5]] 1, wherein the plurality of sample-and-hold circuits are further configured to sample the RF input signal based on the respective clock signal delays of the signal paths to provide a plurality of sampled output signals. Currently amended
(Cu rr ently Amended) The FIR filter of claim 6, wherein the plurality of multipliers are configured to multiply the sampled output signals with a respective tap coefficient value of the respective tap coefficient signal to provide a plurality of modulated output signals. Currently amended
(Cu rr ently Amended) An analog cancellation module including a finite impulse response (FIR) filter for use in a transceiver system, the analog cancellation module comprising: an input of the analog cancellation module that receives an RF input signal, the RF input signal corresponding to a transmit signal provided to a transmit path of the transceiver system; an output of the analog cancellation module that provides a cancellation signal to a receive path of the transceiver system to cancel transmit signal interference; the FIR filter including a plurality of signal paths configured to provide a synthesized frequency response corresponding to the receive path and an adder, each signal path including a respective sample-and-hold circuit and a respective multiplier configured to receive the RF input signal and provide a modulated output signal, each signal path of the plurality of signal paths receiving the clock signal according to a respective clock signal delay, each clock signal delay different from each other clock signal delay, and each multiplier of each signal path being configured to receive a respective tap coefficient signal having a respective tap coefficient delay corresponding to the clock signal delay of the signal path, and the adder being configured to receive n modulated output signals from the plurality of signal paths and combine the n modulated output signals to provide the cancellation signal; and a controller. Currently amended
The analog cancellation module of claim 16, wherein each sample-and- hold circuit and multiplier of the FIR filter includes one or more Gallium Nitride (GaN) devices configured to provide linear operation of the FIR filter. Original
The analog cancellation module of claim [[18]] 16, wherein the FIR filter further includes a plurality of switches coupled to the controller and configured to selectively connect and disconnect at least one signal path of the plurality of signal paths. Currently amended
The analog cancellation module of claim 18, wherein the controller and the plurality of switches of the FIR filter are configured to be controllable and to be operated to adjust a value of n. Original
Layer stacks claimed or described, ordered top of device to substrate.
FIR filter
No layer stack recorded.
GaN HEMT sample-and-hold circuit with gate-bootstrapping stage
analog cancellation module with FIR filter for transceiver system
No layer stack recorded.
Materials described outside the worked examples.
Gallium Nitride (GaN)
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 3A illustrates a schematic diagram of a sample-and-hold circuit 300 in accordance with aspects described herein. In one example, the sample-and-hold …
Related documents with shared materials, methods, properties, or citations.