Patent
US 11,695,088 B2SELF-BYPASS DIODE FUNCTION FOR GALLIUM ARSENIDE PHOTOVOLTAIC DEVICES
Hui Nie, Brendan M. Kayes, Isik C. Kizilyalli
Utica Leaseco, LLC, Rochester Hills, MI (US)·Jul. 4, 2023·US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,695,088 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a diagrammatic illustration of a series of 25 connected solar cells in a solar cell module including a shaded solar cell;
FIG. 2 is a diagrammatic illustration of a series of connected solar cells having discrete bypass diodes con- nected in parallel; 30
FIG. 3 to form a photo- voltaic cell in accordance with some embodiments described 35 herein;
FIG. 4 depicts a cross-sectional view of a semiconductor structure formed from the unit of
FIGS. 5-6 depict cross-sectional views of the semicon- ductor structure of
FIG. 6 for illustrative purposes at a midpoint in the graded layer, due to the material gradation the heterojunction may be at any point 20 within the layer …
FIG. 7 depicts a cross-sectional view of a two-sided 40 photovoltaic cell in accordance with some embodiments described herein; and
FIG. 8 is a graph illustrating doping and breakdown characteristics of a gallium arsenide based solar cell with respect to the bypass function described …
FIG. 9 is a graph illustrating voltage and current charac- teristics of a gallium arsenide based solar cell with respect to the bypass function described …
FIG. 10 is a graph illustrating band-to-band tunneling characteristics of a gallium arsenide based solar cell with 50 respect to the bypass function described …
FIG. 11 is a graph illustrating voltage and current char- acteristics of a gallium arsenide based solar cell with respect to the bypass function described …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming a semiconductor device, the method comprising: providing a semiconductor structure, the semiconductor structure including a base layer configured to absorb photons to convert light energy into electrical energy at the device; and B₂ wherein providing the semiconductor structure includes forming an emitter layer in the semiconductor struc-ture, the emitter layer being made of a different material than the base layer and having a higher bandgap than the base layer, wherein a p-n junction of the semiconductor structure is formed between the emitter layer and the base layer such that under reverse-bias conditions in the resulting device the p-n junction provides a bypass function using a Zener breakdown effect that breaks down in a controlled manner, and wherein the semiconductor structure includes an interme-diate layer between the emitter layer and the base layer, the p-n junction being formed between the emitter layer and the intermediate layer, and a heterojunction being formed between the base layer and the intermediate layer.
The method of claim 1, wherein the bypass function is intrinsic to the p-n junction of the semiconductor device such that the semiconductor device provides the bypass function with no distinct bypass diode connected to or included in the semiconductor device.
The method of claim 1, wherein the base layer is highly doped at about 4×1017 cm⁻³ or greater.
The method of claim 1, wherein the base layer is highly doped within a range of about 4×1017 cm⁻³ to about 1×1019 cm⁻³, and a thickness of the base layer is within a range of about 300 nm to about 3,500 nm.
The method of claim 1, wherein the p-n junction is formed at a location offset from the heterojunction in the semiconductor structure by up to about 200 nm.
The method of claim 1, further comprising separating the semiconductor structure from a growth wafer during an epitaxial lift-off (ELO) process, wherein the ELO process includes etching a sacrificial layer disposed between the semiconductor structure and the growth wafer.
The method of claim 1, wherein the semiconductor device is a photovoltaic device and the base layer includes a Group III-V compound semiconductor.
The method of claim 1, wherein forming the emitter layer includes forming the p-n junction, the p-n junction being a heterojunction.
The method of claim 1, further comprising forming a window layer disposed on a surface of the base layer and away from the emitter layer.
A method for forming a semiconductor device, the method comprising: providing a semiconductor structure including a base layer that absorbs photons to convert light energy into electrical energy at the semiconductor device, with the base layer including a Group III-V compound semiconductor; forming the semiconductor structure to include an emitter layer that is made of a different material than the base layer and has a higher bandgap than the base layer; forming a p-n junction within the semiconductor structure between the emitter layer and the base layer such that under reverse-bias conditions of the semiconductor device, the p-n junction provides a bypass function using a Zener breakdown effect that breaks down in a controlled manner; forming an intermediate layer between the emitter layer and the base layer; and 19 forming a window layer disposed on a surface of the base layer and away from the emitter layer.
The method of claim 11, wherein the base layer is highly doped within a range of about 4×1017 cm⁻³ to about 1×1019 cm⁻³, and a thickness of the base layer is within a range of about 300 nm to about 3,500 nm.
The method of claim 11, further comprising providing the bypass function with no distinct bypass diode connected to or included in the semiconductor device.
The method of claim 11, further comprising providing 10 a contact layer disposed adjacent to the window layer and a metal layer disposed adjacent to the contact layer.
The method of claim 11, further comprising forming the p-n junction at a location offset from a heterojunction in the semiconductor structure by up to about 200 nm.
The method of claim 11, further comprising forming the p-n junction between the emitter layer and the interme-diate layer, and forming a heterojunction between the base layer and the intermediate layer.
The method of claim 11, further comprising forming the intermediate layer to include a gradation in material composition from the material of the base layer to the material of the emitter layer.
The method of claim 11, wherein the p-n junction is a heterojunction. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
gallium arsenide based photovoltaic cell with self-bypass diode function
Materials described outside the worked examples.
base layer (Group III-V compound semiconductor, e.g. gallium arsenide)
GaAs
emitter layer (higher bandgap material, different from base layer)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 8 is a graph illustrating doping and breakdown characteristics of a gallium arsenide based solar cell with respect to the bypass function described …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
base layer doping concentration (lower bound) | ≥ 400000000000000000 cm⁻³ | GaAs |
base layer doping concentration (range) | 400000000000000000–10000000000000000000 cm⁻³ |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 37
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,695,088 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a diagrammatic illustration of a series of 25 connected solar cells in a solar cell module including a shaded solar cell;
FIG. 2 is a diagrammatic illustration of a series of connected solar cells having discrete bypass diodes con- nected in parallel; 30
FIG. 3 to form a photo- voltaic cell in accordance with some embodiments described 35 herein;
FIG. 4 depicts a cross-sectional view of a semiconductor structure formed from the unit of
FIGS. 5-6 depict cross-sectional views of the semicon- ductor structure of
FIG. 6 for illustrative purposes at a midpoint in the graded layer, due to the material gradation the heterojunction may be at any point 20 within the layer …
FIG. 7 depicts a cross-sectional view of a two-sided 40 photovoltaic cell in accordance with some embodiments described herein; and
FIG. 8 is a graph illustrating doping and breakdown characteristics of a gallium arsenide based solar cell with respect to the bypass function described …
FIG. 9 is a graph illustrating voltage and current charac- teristics of a gallium arsenide based solar cell with respect to the bypass function described …
FIG. 10 is a graph illustrating band-to-band tunneling characteristics of a gallium arsenide based solar cell with 50 respect to the bypass function described …
FIG. 11 is a graph illustrating voltage and current char- acteristics of a gallium arsenide based solar cell with respect to the bypass function described …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming a semiconductor device, the method comprising: providing a semiconductor structure, the semiconductor structure including a base layer configured to absorb photons to convert light energy into electrical energy at the device; and B₂ wherein providing the semiconductor structure includes forming an emitter layer in the semiconductor struc-ture, the emitter layer being made of a different material than the base layer and having a higher bandgap than the base layer, wherein a p-n junction of the semiconductor structure is formed between the emitter layer and the base layer such that under reverse-bias conditions in the resulting device the p-n junction provides a bypass function using a Zener breakdown effect that breaks down in a controlled manner, and wherein the semiconductor structure includes an interme-diate layer between the emitter layer and the base layer, the p-n junction being formed between the emitter layer and the intermediate layer, and a heterojunction being formed between the base layer and the intermediate layer.
The method of claim 1, wherein the bypass function is intrinsic to the p-n junction of the semiconductor device such that the semiconductor device provides the bypass function with no distinct bypass diode connected to or included in the semiconductor device.
The method of claim 1, wherein the base layer is highly doped at about 4×1017 cm⁻³ or greater.
The method of claim 1, wherein the base layer is highly doped within a range of about 4×1017 cm⁻³ to about 1×1019 cm⁻³, and a thickness of the base layer is within a range of about 300 nm to about 3,500 nm.
The method of claim 1, wherein the p-n junction is formed at a location offset from the heterojunction in the semiconductor structure by up to about 200 nm.
The method of claim 1, further comprising separating the semiconductor structure from a growth wafer during an epitaxial lift-off (ELO) process, wherein the ELO process includes etching a sacrificial layer disposed between the semiconductor structure and the growth wafer.
The method of claim 1, wherein the semiconductor device is a photovoltaic device and the base layer includes a Group III-V compound semiconductor.
The method of claim 1, wherein forming the emitter layer includes forming the p-n junction, the p-n junction being a heterojunction.
The method of claim 1, further comprising forming a window layer disposed on a surface of the base layer and away from the emitter layer.
A method for forming a semiconductor device, the method comprising: providing a semiconductor structure including a base layer that absorbs photons to convert light energy into electrical energy at the semiconductor device, with the base layer including a Group III-V compound semiconductor; forming the semiconductor structure to include an emitter layer that is made of a different material than the base layer and has a higher bandgap than the base layer; forming a p-n junction within the semiconductor structure between the emitter layer and the base layer such that under reverse-bias conditions of the semiconductor device, the p-n junction provides a bypass function using a Zener breakdown effect that breaks down in a controlled manner; forming an intermediate layer between the emitter layer and the base layer; and 19 forming a window layer disposed on a surface of the base layer and away from the emitter layer.
The method of claim 11, wherein the base layer is highly doped within a range of about 4×1017 cm⁻³ to about 1×1019 cm⁻³, and a thickness of the base layer is within a range of about 300 nm to about 3,500 nm.
The method of claim 11, further comprising providing the bypass function with no distinct bypass diode connected to or included in the semiconductor device.
The method of claim 11, further comprising providing 10 a contact layer disposed adjacent to the window layer and a metal layer disposed adjacent to the contact layer.
The method of claim 11, further comprising forming the p-n junction at a location offset from a heterojunction in the semiconductor structure by up to about 200 nm.
The method of claim 11, further comprising forming the p-n junction between the emitter layer and the interme-diate layer, and forming a heterojunction between the base layer and the intermediate layer.
The method of claim 11, further comprising forming the intermediate layer to include a gradation in material composition from the material of the base layer to the material of the emitter layer.
The method of claim 11, wherein the p-n junction is a heterojunction. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
gallium arsenide based photovoltaic cell with self-bypass diode function
Materials described outside the worked examples.
base layer (Group III-V compound semiconductor, e.g. gallium arsenide)
GaAs
emitter layer (higher bandgap material, different from base layer)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 8 is a graph illustrating doping and breakdown characteristics of a gallium arsenide based solar cell with respect to the bypass function described …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
base layer doping concentration (lower bound) | ≥ 400000000000000000 cm⁻³ | GaAs |
base layer doping concentration (range) | 400000000000000000–10000000000000000000 cm⁻³ |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 37
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,695,088 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a diagrammatic illustration of a series of 25 connected solar cells in a solar cell module including a shaded solar cell;
FIG. 2 is a diagrammatic illustration of a series of connected solar cells having discrete bypass diodes con- nected in parallel; 30
FIG. 3 to form a photo- voltaic cell in accordance with some embodiments described 35 herein;
FIG. 4 depicts a cross-sectional view of a semiconductor structure formed from the unit of
FIGS. 5-6 depict cross-sectional views of the semicon- ductor structure of
FIG. 6 for illustrative purposes at a midpoint in the graded layer, due to the material gradation the heterojunction may be at any point 20 within the layer …
FIG. 7 depicts a cross-sectional view of a two-sided 40 photovoltaic cell in accordance with some embodiments described herein; and
FIG. 8 is a graph illustrating doping and breakdown characteristics of a gallium arsenide based solar cell with respect to the bypass function described …
FIG. 9 is a graph illustrating voltage and current charac- teristics of a gallium arsenide based solar cell with respect to the bypass function described …
FIG. 10 is a graph illustrating band-to-band tunneling characteristics of a gallium arsenide based solar cell with 50 respect to the bypass function described …
FIG. 11 is a graph illustrating voltage and current char- acteristics of a gallium arsenide based solar cell with respect to the bypass function described …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming a semiconductor device, the method comprising: providing a semiconductor structure, the semiconductor structure including a base layer configured to absorb photons to convert light energy into electrical energy at the device; and B₂ wherein providing the semiconductor structure includes forming an emitter layer in the semiconductor struc-ture, the emitter layer being made of a different material than the base layer and having a higher bandgap than the base layer, wherein a p-n junction of the semiconductor structure is formed between the emitter layer and the base layer such that under reverse-bias conditions in the resulting device the p-n junction provides a bypass function using a Zener breakdown effect that breaks down in a controlled manner, and wherein the semiconductor structure includes an interme-diate layer between the emitter layer and the base layer, the p-n junction being formed between the emitter layer and the intermediate layer, and a heterojunction being formed between the base layer and the intermediate layer.
The method of claim 1, wherein the bypass function is intrinsic to the p-n junction of the semiconductor device such that the semiconductor device provides the bypass function with no distinct bypass diode connected to or included in the semiconductor device.
The method of claim 1, wherein the base layer is highly doped at about 4×1017 cm⁻³ or greater.
The method of claim 1, wherein the base layer is highly doped within a range of about 4×1017 cm⁻³ to about 1×1019 cm⁻³, and a thickness of the base layer is within a range of about 300 nm to about 3,500 nm.
The method of claim 1, wherein the p-n junction is formed at a location offset from the heterojunction in the semiconductor structure by up to about 200 nm.
The method of claim 1, further comprising separating the semiconductor structure from a growth wafer during an epitaxial lift-off (ELO) process, wherein the ELO process includes etching a sacrificial layer disposed between the semiconductor structure and the growth wafer.
The method of claim 1, wherein the semiconductor device is a photovoltaic device and the base layer includes a Group III-V compound semiconductor.
The method of claim 1, wherein forming the emitter layer includes forming the p-n junction, the p-n junction being a heterojunction.
The method of claim 1, further comprising forming a window layer disposed on a surface of the base layer and away from the emitter layer.
A method for forming a semiconductor device, the method comprising: providing a semiconductor structure including a base layer that absorbs photons to convert light energy into electrical energy at the semiconductor device, with the base layer including a Group III-V compound semiconductor; forming the semiconductor structure to include an emitter layer that is made of a different material than the base layer and has a higher bandgap than the base layer; forming a p-n junction within the semiconductor structure between the emitter layer and the base layer such that under reverse-bias conditions of the semiconductor device, the p-n junction provides a bypass function using a Zener breakdown effect that breaks down in a controlled manner; forming an intermediate layer between the emitter layer and the base layer; and 19 forming a window layer disposed on a surface of the base layer and away from the emitter layer.
The method of claim 11, wherein the base layer is highly doped within a range of about 4×1017 cm⁻³ to about 1×1019 cm⁻³, and a thickness of the base layer is within a range of about 300 nm to about 3,500 nm.
The method of claim 11, further comprising providing the bypass function with no distinct bypass diode connected to or included in the semiconductor device.
The method of claim 11, further comprising providing 10 a contact layer disposed adjacent to the window layer and a metal layer disposed adjacent to the contact layer.
The method of claim 11, further comprising forming the p-n junction at a location offset from a heterojunction in the semiconductor structure by up to about 200 nm.
The method of claim 11, further comprising forming the p-n junction between the emitter layer and the interme-diate layer, and forming a heterojunction between the base layer and the intermediate layer.
The method of claim 11, further comprising forming the intermediate layer to include a gradation in material composition from the material of the base layer to the material of the emitter layer.
The method of claim 11, wherein the p-n junction is a heterojunction. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
gallium arsenide based photovoltaic cell with self-bypass diode function
Materials described outside the worked examples.
base layer (Group III-V compound semiconductor, e.g. gallium arsenide)
GaAs
emitter layer (higher bandgap material, different from base layer)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 8 is a graph illustrating doping and breakdown characteristics of a gallium arsenide based solar cell with respect to the bypass function described …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
base layer doping concentration (lower bound) | ≥ 400000000000000000 cm⁻³ | GaAs |
base layer doping concentration (range) | 400000000000000000–10000000000000000000 cm⁻³ |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 37
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,695,088 B2Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a diagrammatic illustration of a series of 25 connected solar cells in a solar cell module including a shaded solar cell;
FIG. 2 is a diagrammatic illustration of a series of connected solar cells having discrete bypass diodes con- nected in parallel; 30
FIG. 3 to form a photo- voltaic cell in accordance with some embodiments described 35 herein;
FIG. 4 depicts a cross-sectional view of a semiconductor structure formed from the unit of
FIGS. 5-6 depict cross-sectional views of the semicon- ductor structure of
FIG. 6 for illustrative purposes at a midpoint in the graded layer, due to the material gradation the heterojunction may be at any point 20 within the layer …
FIG. 7 depicts a cross-sectional view of a two-sided 40 photovoltaic cell in accordance with some embodiments described herein; and
FIG. 8 is a graph illustrating doping and breakdown characteristics of a gallium arsenide based solar cell with respect to the bypass function described …
FIG. 9 is a graph illustrating voltage and current charac- teristics of a gallium arsenide based solar cell with respect to the bypass function described …
FIG. 10 is a graph illustrating band-to-band tunneling characteristics of a gallium arsenide based solar cell with 50 respect to the bypass function described …
FIG. 11 is a graph illustrating voltage and current char- acteristics of a gallium arsenide based solar cell with respect to the bypass function described …
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A method for forming a semiconductor device, the method comprising: providing a semiconductor structure, the semiconductor structure including a base layer configured to absorb photons to convert light energy into electrical energy at the device; and B₂ wherein providing the semiconductor structure includes forming an emitter layer in the semiconductor struc-ture, the emitter layer being made of a different material than the base layer and having a higher bandgap than the base layer, wherein a p-n junction of the semiconductor structure is formed between the emitter layer and the base layer such that under reverse-bias conditions in the resulting device the p-n junction provides a bypass function using a Zener breakdown effect that breaks down in a controlled manner, and wherein the semiconductor structure includes an interme-diate layer between the emitter layer and the base layer, the p-n junction being formed between the emitter layer and the intermediate layer, and a heterojunction being formed between the base layer and the intermediate layer.
The method of claim 1, wherein the bypass function is intrinsic to the p-n junction of the semiconductor device such that the semiconductor device provides the bypass function with no distinct bypass diode connected to or included in the semiconductor device.
The method of claim 1, wherein the base layer is highly doped at about 4×1017 cm⁻³ or greater.
The method of claim 1, wherein the base layer is highly doped within a range of about 4×1017 cm⁻³ to about 1×1019 cm⁻³, and a thickness of the base layer is within a range of about 300 nm to about 3,500 nm.
The method of claim 1, wherein the p-n junction is formed at a location offset from the heterojunction in the semiconductor structure by up to about 200 nm.
The method of claim 1, further comprising separating the semiconductor structure from a growth wafer during an epitaxial lift-off (ELO) process, wherein the ELO process includes etching a sacrificial layer disposed between the semiconductor structure and the growth wafer.
The method of claim 1, wherein the semiconductor device is a photovoltaic device and the base layer includes a Group III-V compound semiconductor.
The method of claim 1, wherein forming the emitter layer includes forming the p-n junction, the p-n junction being a heterojunction.
The method of claim 1, further comprising forming a window layer disposed on a surface of the base layer and away from the emitter layer.
A method for forming a semiconductor device, the method comprising: providing a semiconductor structure including a base layer that absorbs photons to convert light energy into electrical energy at the semiconductor device, with the base layer including a Group III-V compound semiconductor; forming the semiconductor structure to include an emitter layer that is made of a different material than the base layer and has a higher bandgap than the base layer; forming a p-n junction within the semiconductor structure between the emitter layer and the base layer such that under reverse-bias conditions of the semiconductor device, the p-n junction provides a bypass function using a Zener breakdown effect that breaks down in a controlled manner; forming an intermediate layer between the emitter layer and the base layer; and 19 forming a window layer disposed on a surface of the base layer and away from the emitter layer.
The method of claim 11, wherein the base layer is highly doped within a range of about 4×1017 cm⁻³ to about 1×1019 cm⁻³, and a thickness of the base layer is within a range of about 300 nm to about 3,500 nm.
The method of claim 11, further comprising providing the bypass function with no distinct bypass diode connected to or included in the semiconductor device.
The method of claim 11, further comprising providing 10 a contact layer disposed adjacent to the window layer and a metal layer disposed adjacent to the contact layer.
The method of claim 11, further comprising forming the p-n junction at a location offset from a heterojunction in the semiconductor structure by up to about 200 nm.
The method of claim 11, further comprising forming the p-n junction between the emitter layer and the interme-diate layer, and forming a heterojunction between the base layer and the intermediate layer.
The method of claim 11, further comprising forming the intermediate layer to include a gradation in material composition from the material of the base layer to the material of the emitter layer.
The method of claim 11, wherein the p-n junction is a heterojunction. ∗ ∗ ∗ ∗ ∗
Layer stacks claimed or described, ordered top of device to substrate.
gallium arsenide based photovoltaic cell with self-bypass diode function
Materials described outside the worked examples.
base layer (Group III-V compound semiconductor, e.g. gallium arsenide)
GaAs
emitter layer (higher bandgap material, different from base layer)
Additional fabrication and treatment steps described in the patent.
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 8 is a graph illustrating doping and breakdown characteristics of a gallium arsenide based solar cell with respect to the bypass function described …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
base layer doping concentration (lower bound) | ≥ 400000000000000000 cm⁻³ | GaAs |
base layer doping concentration (range) | 400000000000000000–10000000000000000000 cm⁻³ |
Patents and literature cited by this patent (applicant and examiner references).
Cited patents · 37
Related documents with shared materials, methods, properties, or citations.
intermediate layer
window layer
contact layer
sacrificial layer
aluminum gallium arsenide
AlGaAs
aluminum gallium indium phosphide
AlGaInP
aluminum indium phosphide
AlInP
aluminum arsenide
AlAs
buffer layer
FIG. 9 is a graph illustrating voltage and current charac- teristics of a gallium arsenide based solar cell with respect to the bypass function described …
FIG. 10 is a graph illustrating band-to-band tunneling characteristics of a gallium arsenide based solar cell with 50 respect to the bypass function described …
FIG. 11 is a graph illustrating voltage and current char- acteristics of a gallium arsenide based solar cell with respect to the bypass function described …
base layer thickness (range) | 300–3500 nm | GaAs |
offset of p-n junction from heterojunction | 0–200 nm | — |
buffer layer thickness | 100–600 nm | buffer layer |
Thickness | 3–100 nm | — |
Thickness | 5–30 nm | — |
Thickness | 10–1000 nm | — |
Thickness | 10–100 nm | — |
Thickness | 25–75 nm | — |
Thickness | 5–75 nm | — |
Thickness | 1000–2000 nm | — |
Thickness | 1–2 µm | — |
Thickness | 55–500 nm | — |
Thickness | 100–500 nm | — |
Thickness | 5–20 Å | — |
Thickness | 25–200 nm | — |
Thickness | 50–150 nm | — |
Thickness | 0.4–0.6 µm | — |
Thickness | 0.7–2 µm | — |
Thickness | 0.7–1 µm | — |
Thickness | 10–120 µm | — |
Thickness | ≤ 1 µm | — |
Thickness | ≤ 500 nm | — |
Thickness | ≥ 5 µm | — |
Cited non-patent literature · 2
intermediate layer
window layer
contact layer
sacrificial layer
aluminum gallium arsenide
AlGaAs
aluminum gallium indium phosphide
AlGaInP
aluminum indium phosphide
AlInP
aluminum arsenide
AlAs
buffer layer
FIG. 9 is a graph illustrating voltage and current charac- teristics of a gallium arsenide based solar cell with respect to the bypass function described …
FIG. 10 is a graph illustrating band-to-band tunneling characteristics of a gallium arsenide based solar cell with 50 respect to the bypass function described …
FIG. 11 is a graph illustrating voltage and current char- acteristics of a gallium arsenide based solar cell with respect to the bypass function described …
base layer thickness (range) | 300–3500 nm | GaAs |
offset of p-n junction from heterojunction | 0–200 nm | — |
buffer layer thickness | 100–600 nm | buffer layer |
Thickness | 3–100 nm | — |
Thickness | 5–30 nm | — |
Thickness | 10–1000 nm | — |
Thickness | 10–100 nm | — |
Thickness | 25–75 nm | — |
Thickness | 5–75 nm | — |
Thickness | 1000–2000 nm | — |
Thickness | 1–2 µm | — |
Thickness | 55–500 nm | — |
Thickness | 100–500 nm | — |
Thickness | 5–20 Å | — |
Thickness | 25–200 nm | — |
Thickness | 50–150 nm | — |
Thickness | 0.4–0.6 µm | — |
Thickness | 0.7–2 µm | — |
Thickness | 0.7–1 µm | — |
Thickness | 10–120 µm | — |
Thickness | ≤ 1 µm | — |
Thickness | ≤ 500 nm | — |
Thickness | ≥ 5 µm | — |
Cited non-patent literature · 2
intermediate layer
window layer
contact layer
sacrificial layer
aluminum gallium arsenide
AlGaAs
aluminum gallium indium phosphide
AlGaInP
aluminum indium phosphide
AlInP
aluminum arsenide
AlAs
buffer layer
FIG. 9 is a graph illustrating voltage and current charac- teristics of a gallium arsenide based solar cell with respect to the bypass function described …
FIG. 10 is a graph illustrating band-to-band tunneling characteristics of a gallium arsenide based solar cell with 50 respect to the bypass function described …
FIG. 11 is a graph illustrating voltage and current char- acteristics of a gallium arsenide based solar cell with respect to the bypass function described …
base layer thickness (range) | 300–3500 nm | GaAs |
offset of p-n junction from heterojunction | 0–200 nm | — |
buffer layer thickness | 100–600 nm | buffer layer |
Thickness | 3–100 nm | — |
Thickness | 5–30 nm | — |
Thickness | 10–1000 nm | — |
Thickness | 10–100 nm | — |
Thickness | 25–75 nm | — |
Thickness | 5–75 nm | — |
Thickness | 1000–2000 nm | — |
Thickness | 1–2 µm | — |
Thickness | 55–500 nm | — |
Thickness | 100–500 nm | — |
Thickness | 5–20 Å | — |
Thickness | 25–200 nm | — |
Thickness | 50–150 nm | — |
Thickness | 0.4–0.6 µm | — |
Thickness | 0.7–2 µm | — |
Thickness | 0.7–1 µm | — |
Thickness | 10–120 µm | — |
Thickness | ≤ 1 µm | — |
Thickness | ≤ 500 nm | — |
Thickness | ≥ 5 µm | — |
Cited non-patent literature · 2
intermediate layer
window layer
contact layer
sacrificial layer
aluminum gallium arsenide
AlGaAs
aluminum gallium indium phosphide
AlGaInP
aluminum indium phosphide
AlInP
aluminum arsenide
AlAs
buffer layer
FIG. 9 is a graph illustrating voltage and current charac- teristics of a gallium arsenide based solar cell with respect to the bypass function described …
FIG. 10 is a graph illustrating band-to-band tunneling characteristics of a gallium arsenide based solar cell with 50 respect to the bypass function described …
FIG. 11 is a graph illustrating voltage and current char- acteristics of a gallium arsenide based solar cell with respect to the bypass function described …
base layer thickness (range) | 300–3500 nm | GaAs |
offset of p-n junction from heterojunction | 0–200 nm | — |
buffer layer thickness | 100–600 nm | buffer layer |
Thickness | 3–100 nm | — |
Thickness | 5–30 nm | — |
Thickness | 10–1000 nm | — |
Thickness | 10–100 nm | — |
Thickness | 25–75 nm | — |
Thickness | 5–75 nm | — |
Thickness | 1000–2000 nm | — |
Thickness | 1–2 µm | — |
Thickness | 55–500 nm | — |
Thickness | 100–500 nm | — |
Thickness | 5–20 Å | — |
Thickness | 25–200 nm | — |
Thickness | 50–150 nm | — |
Thickness | 0.4–0.6 µm | — |
Thickness | 0.7–2 µm | — |
Thickness | 0.7–1 µm | — |
Thickness | 10–120 µm | — |
Thickness | ≤ 1 µm | — |
Thickness | ≤ 500 nm | — |
Thickness | ≥ 5 µm | — |
Cited non-patent literature · 2