Patent
US 10,109,736SUPPERLATTICE BUFFER STRUCTURE FOR GALLIUM NITRIDE TRANSISTORS
Chi-Ming Chen
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 10,109,736Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor comprising: a first strained layer superlattice (SLS) layer arranged over a substrate, wherein the first SLS layer has a first compressive stress, wherein the first SLS layer alternates multiple times between tensile layers and compressive layers, wherein the tensile layers produce a first tensile stress, wherein the compressive layers produce a second compressive stress, and wherein the tensile and compressive layers collectively produce the first compressive stress; a first buffer layer arranged over and contacting the first SLS layer, wherein the first buffer layer includes dopants configured to increase a first resistance of the first buffer layer, and wherein the first buffer layer has a second tensile stress that counteracts the first compressive stress; a second SLS layer arranged over the first buffer layer; a second buffer layer arranged over the second SLS layer and including dopants configured to increase a second resistance of the second buffer layer, wherein the second buffer layer is a single material, and wherein the single material is limited to gallium nitride (GaN); a channel layer arranged over and directly contacting the second buffer layer; and an active layer arranged over and directly abutting the channel layer, wherein the channel and active layers collectively define a heterojunction. Currently amended
The transistor according to claim 1, wherein the first SLS layer includes about 20 to about 100 pairs of lattice mismatched layers, and wherein a pair of lattice mismatched layers includes layers with mismatched lattice constants. Original
The transistor according to claim 1, wherein the second SLS layer includes about 20 to about 100 pairs of lattice mismatched layers, and wherein a pair of lattice mismatched layers includes layers with mismatched lattice constants. Original
The transistor according to claim 1, further including: a dielectric layer arranged over the active layer; a source electrode and a drain electrode arranged over the dielectric layer and extending to the active layer through the dielectric layer; and a gate electrode arranged over the dielectric layer and between the source electrode and the drain electrode. Original
The transistor according to claim 1, wherein the first or second SLS layer includes a plurality of pairs of lattice mismatched layers configured to collectively produce a compressive force, wherein a pair of lattice mismatched layers includes layers with mismatched lattice constants, wherein lattice mismatched layers of a pair of lattice mismatched layers are respectively an aluminum nitride (AIN) layer and a gallium nitride (GaN) layer, wherein the GaN layer produces a second compressive force, and wherein the AIN layer produces a second tensile force that is less than the second compressive force. Previously presented
The transistor according to claim 1, wherein the first and second buffer layers are a single material, wherein the first and second SLS layers are each defined by a plurality of pairs of lattice mismatched semiconductor layers, wherein each of the pairs is limited to a single material different than that of the first and second buffer layers, wherein the first and second SLS layers are configured to trap electrons, and wherein the first and second SLS layers are configured to block silicon diffusing from the substrate towards the first and second buffer layers. Previously presented
The transistor according to claim 1, further comprising: a graded buffer layer arranged under the first SLS layer, wherein the graded buffer layer comprises at least three layers of aluminum gallium nitride (AIGaN). Previously presented
The transistor according to claim 1, wherein the first and second buffer layers both have resistances greater than a resistance of the channel SVG 14620399.08-31-2018.JLI₈NUJDRXEAPX0.CLM.8.5.631.614.658.663.svg 0.163 0.09 Chemistry Black and white Serial No. 14/620,399 Page 9 layer, and wherein doping concentrations of the first and second buffer layers exceed about 1e19cm-Previously presented
Canceled
Canceled
Canceled
Canceled
11-19. Canceled
Canceled
A transistor comprising: a silicon substrate; first and second strained layer superlattice (SLS)/buffer pairs stacked in that order over the silicon substrate, wherein the first and second SLS/buffer pairs include corresponding SLS layers and corresponding buffer layers arranged over the corresponding SLS layers, wherein the SLS layers include alternating layers of aluminum nitride (AIN) and gallium nitride (GaN), wherein the buffer layers include GaN layers doped with carbon or iron, wherein the SLS layers comprise quantum dots configured to trap electrons from the silicon substrate, and wherein the SLS layers are configured to negate tensile stress by the buffer layers; a channel layer of undoped GaN arranged over the second SLS/buffer pair; an active layer arranged over and directly abutting the channel layer, wherein the active layer includes aluminum gallium nitride (AIGaN), and wherein the channel and active layers collectively define a heterojunction; a gate electrode arranged over the active layer and between a source electrode and a drain electrode, wherein a first portion of the source electrode and a first portion of the drain electrode directly contact the active layer; and a dielectric layer arranged over and directly contacting the active layer, wherein the dielectric layer separates the gate electrode, a second portion of the source electrode, and a second portion of the drain electrode from the active layer, and wherein the dielectric layer is continuously planar from a sidewall of the first portion of the source electrode to a sidewall of the first portion of the drain electrode. Previously presented
The transistor according to claim 20, wherein the SLS layers each comprise a plurality of pairs of lattice mismatched layers stacked upon one another, and wherein the plurality of pairs of lattice mismatched layers each comprise one of the layers of GaN and one of the layers of AIN arranged over and contacting the one of the layers of GaN. Previously presented
The transistor according to claim 20, wherein the buffer layers both have resistances greater than a resistance of the channel layer, and SVG 14620399.08-31-2018.JLI₈NUJDRXEAPX0.CLM.4.14.491.1566.518.1615.svg 0.163 0.09 Chemistry Black and white wherein doping concentrations of the corresponding buffer layers exceed about 1e1 9cm-Previously presented
The transistor according to claim 20, wherein the layers of AIN in the SLS layers have a first lattice constant and the layers of GaN in the SLS layers have a second lattice constant different than the first lattice constant. Previously presented
The transistor according to claim 20, wherein the buffer layers are limited to GaN and have a different concentration of carbon or iron than the SLS layers, wherein the SLS layers are limited to AIN and GaN, wherein the buffers layers and the layers of AIN in the SLS layers have tensile stress, and wherein the layers of GaN in the SLS layers have compressive stress counteracting the tensile stress. Previously presented
The transistor according to claim 20, wherein the sidewall of the first portion of the source electrode faces the gate electrode, wherein the second portion of the source electrode overhangs the sidewall of the first portion of the source electrode, and wherein the dielectric layer is in continuous direct contact with both the source electrode and the active layer from the sidewall of the first portion of the source electrode to a sidewall of the second portion of the source electrode. Previously presented
23-28. Canceled
Canceled
Canceled
A transistor comprising: a silicon substrate; a seed layer arranged over and directly contacting the silicon substrate, wherein the seed layer comprises aluminum nitride (AIN); a graded buffer layer arranged over and directly contacting the seed layer, wherein the graded buffer layer comprises at least three layers of aluminum gallium nitride (AIGaN), wherein each of the at least three layers has a different amount of an element common to the at least three layers, and wherein the graded buffer layer is doped with carbon or iron; a first strained layer superlattice (SLS) layer arranged over and directly contacting the graded buffer layer, wherein the first SLS layer has a first compressive stress, wherein the first SLS layer comprises a first plurality of alternating layers of aluminum nitride (AIN) and gallium nitride (GaN), and wherein the first plurality of alternating layers of AIN and GaN collectively produce the first compressive stress; a first buffer layer arranged over and directly contacting the first SLS layer, wherein the first buffer layer consists essentially of a single GaN layer doped with carbon or iron, and wherein the first buffer layer has a tensile stress that counteracts the first compressive stress; a second SLS layer arranged over and directly contacting the first buffer layer, wherein the second SLS layer has a second compressive stress, wherein the second SLS layer comprises a second plurality of alternating layers of AIN and GaN, and wherein the second plurality of alternating layers of AIN and GaN collectively produce the second compressive stress; a second buffer layer arranged over and directly contacting the second SLS layer, wherein the second buffer layer consists essentially of a single GaN layer doped with carbon or iron, and wherein the second buffer layer has a tensile stress that counteracts the second compressive stress; a channel layer arranged over and directly contacting the second buffer layer, wherein the channel layer comprises a single undoped GaN layer; and an active layer arranged over and directly contacting the channel layer, wherein the active layer comprises AIGaN, and wherein the channel layer and th e active layer collectively define a heterojunction. Currently amended
The transistor according to claim 34, further comprising: a gate electrode arranged over the active layer and between a source electrode and a drain electrode, wherein a first portion of the source electrode and a first portion of the drain electrode directly contact the active layer; and a dielectric layer arranged over and directly contacting the active layer, wherein the dielectric layer separates the gate electrode, a second portion of the source electrode, and a second portion of the drain electrode from the active layer, and wherein the dielectric layer is continuously planar from a sidewall of the first portion of the source electrode to a sidewall of the first portion of the drain electrode. Previously presented
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor with multi-SLS structure (generic)
Materials described outside the worked examples.
strained layer superlattice (SLS) layer
aluminum nitride
AlN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
high resistivity GaN buffer layer doping concentration (carbon) | ≥ 10000000000000000000 cm⁻³ | GaN |
GaN channel layer carbon concentration upper limit |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,109,736Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor comprising: a first strained layer superlattice (SLS) layer arranged over a substrate, wherein the first SLS layer has a first compressive stress, wherein the first SLS layer alternates multiple times between tensile layers and compressive layers, wherein the tensile layers produce a first tensile stress, wherein the compressive layers produce a second compressive stress, and wherein the tensile and compressive layers collectively produce the first compressive stress; a first buffer layer arranged over and contacting the first SLS layer, wherein the first buffer layer includes dopants configured to increase a first resistance of the first buffer layer, and wherein the first buffer layer has a second tensile stress that counteracts the first compressive stress; a second SLS layer arranged over the first buffer layer; a second buffer layer arranged over the second SLS layer and including dopants configured to increase a second resistance of the second buffer layer, wherein the second buffer layer is a single material, and wherein the single material is limited to gallium nitride (GaN); a channel layer arranged over and directly contacting the second buffer layer; and an active layer arranged over and directly abutting the channel layer, wherein the channel and active layers collectively define a heterojunction. Currently amended
The transistor according to claim 1, wherein the first SLS layer includes about 20 to about 100 pairs of lattice mismatched layers, and wherein a pair of lattice mismatched layers includes layers with mismatched lattice constants. Original
The transistor according to claim 1, wherein the second SLS layer includes about 20 to about 100 pairs of lattice mismatched layers, and wherein a pair of lattice mismatched layers includes layers with mismatched lattice constants. Original
The transistor according to claim 1, further including: a dielectric layer arranged over the active layer; a source electrode and a drain electrode arranged over the dielectric layer and extending to the active layer through the dielectric layer; and a gate electrode arranged over the dielectric layer and between the source electrode and the drain electrode. Original
The transistor according to claim 1, wherein the first or second SLS layer includes a plurality of pairs of lattice mismatched layers configured to collectively produce a compressive force, wherein a pair of lattice mismatched layers includes layers with mismatched lattice constants, wherein lattice mismatched layers of a pair of lattice mismatched layers are respectively an aluminum nitride (AIN) layer and a gallium nitride (GaN) layer, wherein the GaN layer produces a second compressive force, and wherein the AIN layer produces a second tensile force that is less than the second compressive force. Previously presented
The transistor according to claim 1, wherein the first and second buffer layers are a single material, wherein the first and second SLS layers are each defined by a plurality of pairs of lattice mismatched semiconductor layers, wherein each of the pairs is limited to a single material different than that of the first and second buffer layers, wherein the first and second SLS layers are configured to trap electrons, and wherein the first and second SLS layers are configured to block silicon diffusing from the substrate towards the first and second buffer layers. Previously presented
The transistor according to claim 1, further comprising: a graded buffer layer arranged under the first SLS layer, wherein the graded buffer layer comprises at least three layers of aluminum gallium nitride (AIGaN). Previously presented
The transistor according to claim 1, wherein the first and second buffer layers both have resistances greater than a resistance of the channel SVG 14620399.08-31-2018.JLI₈NUJDRXEAPX0.CLM.8.5.631.614.658.663.svg 0.163 0.09 Chemistry Black and white Serial No. 14/620,399 Page 9 layer, and wherein doping concentrations of the first and second buffer layers exceed about 1e19cm-Previously presented
Canceled
Canceled
Canceled
Canceled
11-19. Canceled
Canceled
A transistor comprising: a silicon substrate; first and second strained layer superlattice (SLS)/buffer pairs stacked in that order over the silicon substrate, wherein the first and second SLS/buffer pairs include corresponding SLS layers and corresponding buffer layers arranged over the corresponding SLS layers, wherein the SLS layers include alternating layers of aluminum nitride (AIN) and gallium nitride (GaN), wherein the buffer layers include GaN layers doped with carbon or iron, wherein the SLS layers comprise quantum dots configured to trap electrons from the silicon substrate, and wherein the SLS layers are configured to negate tensile stress by the buffer layers; a channel layer of undoped GaN arranged over the second SLS/buffer pair; an active layer arranged over and directly abutting the channel layer, wherein the active layer includes aluminum gallium nitride (AIGaN), and wherein the channel and active layers collectively define a heterojunction; a gate electrode arranged over the active layer and between a source electrode and a drain electrode, wherein a first portion of the source electrode and a first portion of the drain electrode directly contact the active layer; and a dielectric layer arranged over and directly contacting the active layer, wherein the dielectric layer separates the gate electrode, a second portion of the source electrode, and a second portion of the drain electrode from the active layer, and wherein the dielectric layer is continuously planar from a sidewall of the first portion of the source electrode to a sidewall of the first portion of the drain electrode. Previously presented
The transistor according to claim 20, wherein the SLS layers each comprise a plurality of pairs of lattice mismatched layers stacked upon one another, and wherein the plurality of pairs of lattice mismatched layers each comprise one of the layers of GaN and one of the layers of AIN arranged over and contacting the one of the layers of GaN. Previously presented
The transistor according to claim 20, wherein the buffer layers both have resistances greater than a resistance of the channel layer, and SVG 14620399.08-31-2018.JLI₈NUJDRXEAPX0.CLM.4.14.491.1566.518.1615.svg 0.163 0.09 Chemistry Black and white wherein doping concentrations of the corresponding buffer layers exceed about 1e1 9cm-Previously presented
The transistor according to claim 20, wherein the layers of AIN in the SLS layers have a first lattice constant and the layers of GaN in the SLS layers have a second lattice constant different than the first lattice constant. Previously presented
The transistor according to claim 20, wherein the buffer layers are limited to GaN and have a different concentration of carbon or iron than the SLS layers, wherein the SLS layers are limited to AIN and GaN, wherein the buffers layers and the layers of AIN in the SLS layers have tensile stress, and wherein the layers of GaN in the SLS layers have compressive stress counteracting the tensile stress. Previously presented
The transistor according to claim 20, wherein the sidewall of the first portion of the source electrode faces the gate electrode, wherein the second portion of the source electrode overhangs the sidewall of the first portion of the source electrode, and wherein the dielectric layer is in continuous direct contact with both the source electrode and the active layer from the sidewall of the first portion of the source electrode to a sidewall of the second portion of the source electrode. Previously presented
23-28. Canceled
Canceled
Canceled
A transistor comprising: a silicon substrate; a seed layer arranged over and directly contacting the silicon substrate, wherein the seed layer comprises aluminum nitride (AIN); a graded buffer layer arranged over and directly contacting the seed layer, wherein the graded buffer layer comprises at least three layers of aluminum gallium nitride (AIGaN), wherein each of the at least three layers has a different amount of an element common to the at least three layers, and wherein the graded buffer layer is doped with carbon or iron; a first strained layer superlattice (SLS) layer arranged over and directly contacting the graded buffer layer, wherein the first SLS layer has a first compressive stress, wherein the first SLS layer comprises a first plurality of alternating layers of aluminum nitride (AIN) and gallium nitride (GaN), and wherein the first plurality of alternating layers of AIN and GaN collectively produce the first compressive stress; a first buffer layer arranged over and directly contacting the first SLS layer, wherein the first buffer layer consists essentially of a single GaN layer doped with carbon or iron, and wherein the first buffer layer has a tensile stress that counteracts the first compressive stress; a second SLS layer arranged over and directly contacting the first buffer layer, wherein the second SLS layer has a second compressive stress, wherein the second SLS layer comprises a second plurality of alternating layers of AIN and GaN, and wherein the second plurality of alternating layers of AIN and GaN collectively produce the second compressive stress; a second buffer layer arranged over and directly contacting the second SLS layer, wherein the second buffer layer consists essentially of a single GaN layer doped with carbon or iron, and wherein the second buffer layer has a tensile stress that counteracts the second compressive stress; a channel layer arranged over and directly contacting the second buffer layer, wherein the channel layer comprises a single undoped GaN layer; and an active layer arranged over and directly contacting the channel layer, wherein the active layer comprises AIGaN, and wherein the channel layer and th e active layer collectively define a heterojunction. Currently amended
The transistor according to claim 34, further comprising: a gate electrode arranged over the active layer and between a source electrode and a drain electrode, wherein a first portion of the source electrode and a first portion of the drain electrode directly contact the active layer; and a dielectric layer arranged over and directly contacting the active layer, wherein the dielectric layer separates the gate electrode, a second portion of the source electrode, and a second portion of the drain electrode from the active layer, and wherein the dielectric layer is continuously planar from a sidewall of the first portion of the source electrode to a sidewall of the first portion of the drain electrode. Previously presented
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor with multi-SLS structure (generic)
Materials described outside the worked examples.
strained layer superlattice (SLS) layer
aluminum nitride
AlN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
high resistivity GaN buffer layer doping concentration (carbon) | ≥ 10000000000000000000 cm⁻³ | GaN |
GaN channel layer carbon concentration upper limit |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,109,736Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor comprising: a first strained layer superlattice (SLS) layer arranged over a substrate, wherein the first SLS layer has a first compressive stress, wherein the first SLS layer alternates multiple times between tensile layers and compressive layers, wherein the tensile layers produce a first tensile stress, wherein the compressive layers produce a second compressive stress, and wherein the tensile and compressive layers collectively produce the first compressive stress; a first buffer layer arranged over and contacting the first SLS layer, wherein the first buffer layer includes dopants configured to increase a first resistance of the first buffer layer, and wherein the first buffer layer has a second tensile stress that counteracts the first compressive stress; a second SLS layer arranged over the first buffer layer; a second buffer layer arranged over the second SLS layer and including dopants configured to increase a second resistance of the second buffer layer, wherein the second buffer layer is a single material, and wherein the single material is limited to gallium nitride (GaN); a channel layer arranged over and directly contacting the second buffer layer; and an active layer arranged over and directly abutting the channel layer, wherein the channel and active layers collectively define a heterojunction. Currently amended
The transistor according to claim 1, wherein the first SLS layer includes about 20 to about 100 pairs of lattice mismatched layers, and wherein a pair of lattice mismatched layers includes layers with mismatched lattice constants. Original
The transistor according to claim 1, wherein the second SLS layer includes about 20 to about 100 pairs of lattice mismatched layers, and wherein a pair of lattice mismatched layers includes layers with mismatched lattice constants. Original
The transistor according to claim 1, further including: a dielectric layer arranged over the active layer; a source electrode and a drain electrode arranged over the dielectric layer and extending to the active layer through the dielectric layer; and a gate electrode arranged over the dielectric layer and between the source electrode and the drain electrode. Original
The transistor according to claim 1, wherein the first or second SLS layer includes a plurality of pairs of lattice mismatched layers configured to collectively produce a compressive force, wherein a pair of lattice mismatched layers includes layers with mismatched lattice constants, wherein lattice mismatched layers of a pair of lattice mismatched layers are respectively an aluminum nitride (AIN) layer and a gallium nitride (GaN) layer, wherein the GaN layer produces a second compressive force, and wherein the AIN layer produces a second tensile force that is less than the second compressive force. Previously presented
The transistor according to claim 1, wherein the first and second buffer layers are a single material, wherein the first and second SLS layers are each defined by a plurality of pairs of lattice mismatched semiconductor layers, wherein each of the pairs is limited to a single material different than that of the first and second buffer layers, wherein the first and second SLS layers are configured to trap electrons, and wherein the first and second SLS layers are configured to block silicon diffusing from the substrate towards the first and second buffer layers. Previously presented
The transistor according to claim 1, further comprising: a graded buffer layer arranged under the first SLS layer, wherein the graded buffer layer comprises at least three layers of aluminum gallium nitride (AIGaN). Previously presented
The transistor according to claim 1, wherein the first and second buffer layers both have resistances greater than a resistance of the channel SVG 14620399.08-31-2018.JLI₈NUJDRXEAPX0.CLM.8.5.631.614.658.663.svg 0.163 0.09 Chemistry Black and white Serial No. 14/620,399 Page 9 layer, and wherein doping concentrations of the first and second buffer layers exceed about 1e19cm-Previously presented
Canceled
Canceled
Canceled
Canceled
11-19. Canceled
Canceled
A transistor comprising: a silicon substrate; first and second strained layer superlattice (SLS)/buffer pairs stacked in that order over the silicon substrate, wherein the first and second SLS/buffer pairs include corresponding SLS layers and corresponding buffer layers arranged over the corresponding SLS layers, wherein the SLS layers include alternating layers of aluminum nitride (AIN) and gallium nitride (GaN), wherein the buffer layers include GaN layers doped with carbon or iron, wherein the SLS layers comprise quantum dots configured to trap electrons from the silicon substrate, and wherein the SLS layers are configured to negate tensile stress by the buffer layers; a channel layer of undoped GaN arranged over the second SLS/buffer pair; an active layer arranged over and directly abutting the channel layer, wherein the active layer includes aluminum gallium nitride (AIGaN), and wherein the channel and active layers collectively define a heterojunction; a gate electrode arranged over the active layer and between a source electrode and a drain electrode, wherein a first portion of the source electrode and a first portion of the drain electrode directly contact the active layer; and a dielectric layer arranged over and directly contacting the active layer, wherein the dielectric layer separates the gate electrode, a second portion of the source electrode, and a second portion of the drain electrode from the active layer, and wherein the dielectric layer is continuously planar from a sidewall of the first portion of the source electrode to a sidewall of the first portion of the drain electrode. Previously presented
The transistor according to claim 20, wherein the SLS layers each comprise a plurality of pairs of lattice mismatched layers stacked upon one another, and wherein the plurality of pairs of lattice mismatched layers each comprise one of the layers of GaN and one of the layers of AIN arranged over and contacting the one of the layers of GaN. Previously presented
The transistor according to claim 20, wherein the buffer layers both have resistances greater than a resistance of the channel layer, and SVG 14620399.08-31-2018.JLI₈NUJDRXEAPX0.CLM.4.14.491.1566.518.1615.svg 0.163 0.09 Chemistry Black and white wherein doping concentrations of the corresponding buffer layers exceed about 1e1 9cm-Previously presented
The transistor according to claim 20, wherein the layers of AIN in the SLS layers have a first lattice constant and the layers of GaN in the SLS layers have a second lattice constant different than the first lattice constant. Previously presented
The transistor according to claim 20, wherein the buffer layers are limited to GaN and have a different concentration of carbon or iron than the SLS layers, wherein the SLS layers are limited to AIN and GaN, wherein the buffers layers and the layers of AIN in the SLS layers have tensile stress, and wherein the layers of GaN in the SLS layers have compressive stress counteracting the tensile stress. Previously presented
The transistor according to claim 20, wherein the sidewall of the first portion of the source electrode faces the gate electrode, wherein the second portion of the source electrode overhangs the sidewall of the first portion of the source electrode, and wherein the dielectric layer is in continuous direct contact with both the source electrode and the active layer from the sidewall of the first portion of the source electrode to a sidewall of the second portion of the source electrode. Previously presented
23-28. Canceled
Canceled
Canceled
A transistor comprising: a silicon substrate; a seed layer arranged over and directly contacting the silicon substrate, wherein the seed layer comprises aluminum nitride (AIN); a graded buffer layer arranged over and directly contacting the seed layer, wherein the graded buffer layer comprises at least three layers of aluminum gallium nitride (AIGaN), wherein each of the at least three layers has a different amount of an element common to the at least three layers, and wherein the graded buffer layer is doped with carbon or iron; a first strained layer superlattice (SLS) layer arranged over and directly contacting the graded buffer layer, wherein the first SLS layer has a first compressive stress, wherein the first SLS layer comprises a first plurality of alternating layers of aluminum nitride (AIN) and gallium nitride (GaN), and wherein the first plurality of alternating layers of AIN and GaN collectively produce the first compressive stress; a first buffer layer arranged over and directly contacting the first SLS layer, wherein the first buffer layer consists essentially of a single GaN layer doped with carbon or iron, and wherein the first buffer layer has a tensile stress that counteracts the first compressive stress; a second SLS layer arranged over and directly contacting the first buffer layer, wherein the second SLS layer has a second compressive stress, wherein the second SLS layer comprises a second plurality of alternating layers of AIN and GaN, and wherein the second plurality of alternating layers of AIN and GaN collectively produce the second compressive stress; a second buffer layer arranged over and directly contacting the second SLS layer, wherein the second buffer layer consists essentially of a single GaN layer doped with carbon or iron, and wherein the second buffer layer has a tensile stress that counteracts the second compressive stress; a channel layer arranged over and directly contacting the second buffer layer, wherein the channel layer comprises a single undoped GaN layer; and an active layer arranged over and directly contacting the channel layer, wherein the active layer comprises AIGaN, and wherein the channel layer and th e active layer collectively define a heterojunction. Currently amended
The transistor according to claim 34, further comprising: a gate electrode arranged over the active layer and between a source electrode and a drain electrode, wherein a first portion of the source electrode and a first portion of the drain electrode directly contact the active layer; and a dielectric layer arranged over and directly contacting the active layer, wherein the dielectric layer separates the gate electrode, a second portion of the source electrode, and a second portion of the drain electrode from the active layer, and wherein the dielectric layer is continuously planar from a sidewall of the first portion of the source electrode to a sidewall of the first portion of the drain electrode. Previously presented
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor with multi-SLS structure (generic)
Materials described outside the worked examples.
strained layer superlattice (SLS) layer
aluminum nitride
AlN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
high resistivity GaN buffer layer doping concentration (carbon) | ≥ 10000000000000000000 cm⁻³ | GaN |
GaN channel layer carbon concentration upper limit |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,109,736Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A transistor comprising: a first strained layer superlattice (SLS) layer arranged over a substrate, wherein the first SLS layer has a first compressive stress, wherein the first SLS layer alternates multiple times between tensile layers and compressive layers, wherein the tensile layers produce a first tensile stress, wherein the compressive layers produce a second compressive stress, and wherein the tensile and compressive layers collectively produce the first compressive stress; a first buffer layer arranged over and contacting the first SLS layer, wherein the first buffer layer includes dopants configured to increase a first resistance of the first buffer layer, and wherein the first buffer layer has a second tensile stress that counteracts the first compressive stress; a second SLS layer arranged over the first buffer layer; a second buffer layer arranged over the second SLS layer and including dopants configured to increase a second resistance of the second buffer layer, wherein the second buffer layer is a single material, and wherein the single material is limited to gallium nitride (GaN); a channel layer arranged over and directly contacting the second buffer layer; and an active layer arranged over and directly abutting the channel layer, wherein the channel and active layers collectively define a heterojunction. Currently amended
The transistor according to claim 1, wherein the first SLS layer includes about 20 to about 100 pairs of lattice mismatched layers, and wherein a pair of lattice mismatched layers includes layers with mismatched lattice constants. Original
The transistor according to claim 1, wherein the second SLS layer includes about 20 to about 100 pairs of lattice mismatched layers, and wherein a pair of lattice mismatched layers includes layers with mismatched lattice constants. Original
The transistor according to claim 1, further including: a dielectric layer arranged over the active layer; a source electrode and a drain electrode arranged over the dielectric layer and extending to the active layer through the dielectric layer; and a gate electrode arranged over the dielectric layer and between the source electrode and the drain electrode. Original
The transistor according to claim 1, wherein the first or second SLS layer includes a plurality of pairs of lattice mismatched layers configured to collectively produce a compressive force, wherein a pair of lattice mismatched layers includes layers with mismatched lattice constants, wherein lattice mismatched layers of a pair of lattice mismatched layers are respectively an aluminum nitride (AIN) layer and a gallium nitride (GaN) layer, wherein the GaN layer produces a second compressive force, and wherein the AIN layer produces a second tensile force that is less than the second compressive force. Previously presented
The transistor according to claim 1, wherein the first and second buffer layers are a single material, wherein the first and second SLS layers are each defined by a plurality of pairs of lattice mismatched semiconductor layers, wherein each of the pairs is limited to a single material different than that of the first and second buffer layers, wherein the first and second SLS layers are configured to trap electrons, and wherein the first and second SLS layers are configured to block silicon diffusing from the substrate towards the first and second buffer layers. Previously presented
The transistor according to claim 1, further comprising: a graded buffer layer arranged under the first SLS layer, wherein the graded buffer layer comprises at least three layers of aluminum gallium nitride (AIGaN). Previously presented
The transistor according to claim 1, wherein the first and second buffer layers both have resistances greater than a resistance of the channel SVG 14620399.08-31-2018.JLI₈NUJDRXEAPX0.CLM.8.5.631.614.658.663.svg 0.163 0.09 Chemistry Black and white Serial No. 14/620,399 Page 9 layer, and wherein doping concentrations of the first and second buffer layers exceed about 1e19cm-Previously presented
Canceled
Canceled
Canceled
Canceled
11-19. Canceled
Canceled
A transistor comprising: a silicon substrate; first and second strained layer superlattice (SLS)/buffer pairs stacked in that order over the silicon substrate, wherein the first and second SLS/buffer pairs include corresponding SLS layers and corresponding buffer layers arranged over the corresponding SLS layers, wherein the SLS layers include alternating layers of aluminum nitride (AIN) and gallium nitride (GaN), wherein the buffer layers include GaN layers doped with carbon or iron, wherein the SLS layers comprise quantum dots configured to trap electrons from the silicon substrate, and wherein the SLS layers are configured to negate tensile stress by the buffer layers; a channel layer of undoped GaN arranged over the second SLS/buffer pair; an active layer arranged over and directly abutting the channel layer, wherein the active layer includes aluminum gallium nitride (AIGaN), and wherein the channel and active layers collectively define a heterojunction; a gate electrode arranged over the active layer and between a source electrode and a drain electrode, wherein a first portion of the source electrode and a first portion of the drain electrode directly contact the active layer; and a dielectric layer arranged over and directly contacting the active layer, wherein the dielectric layer separates the gate electrode, a second portion of the source electrode, and a second portion of the drain electrode from the active layer, and wherein the dielectric layer is continuously planar from a sidewall of the first portion of the source electrode to a sidewall of the first portion of the drain electrode. Previously presented
The transistor according to claim 20, wherein the SLS layers each comprise a plurality of pairs of lattice mismatched layers stacked upon one another, and wherein the plurality of pairs of lattice mismatched layers each comprise one of the layers of GaN and one of the layers of AIN arranged over and contacting the one of the layers of GaN. Previously presented
The transistor according to claim 20, wherein the buffer layers both have resistances greater than a resistance of the channel layer, and SVG 14620399.08-31-2018.JLI₈NUJDRXEAPX0.CLM.4.14.491.1566.518.1615.svg 0.163 0.09 Chemistry Black and white wherein doping concentrations of the corresponding buffer layers exceed about 1e1 9cm-Previously presented
The transistor according to claim 20, wherein the layers of AIN in the SLS layers have a first lattice constant and the layers of GaN in the SLS layers have a second lattice constant different than the first lattice constant. Previously presented
The transistor according to claim 20, wherein the buffer layers are limited to GaN and have a different concentration of carbon or iron than the SLS layers, wherein the SLS layers are limited to AIN and GaN, wherein the buffers layers and the layers of AIN in the SLS layers have tensile stress, and wherein the layers of GaN in the SLS layers have compressive stress counteracting the tensile stress. Previously presented
The transistor according to claim 20, wherein the sidewall of the first portion of the source electrode faces the gate electrode, wherein the second portion of the source electrode overhangs the sidewall of the first portion of the source electrode, and wherein the dielectric layer is in continuous direct contact with both the source electrode and the active layer from the sidewall of the first portion of the source electrode to a sidewall of the second portion of the source electrode. Previously presented
23-28. Canceled
Canceled
Canceled
A transistor comprising: a silicon substrate; a seed layer arranged over and directly contacting the silicon substrate, wherein the seed layer comprises aluminum nitride (AIN); a graded buffer layer arranged over and directly contacting the seed layer, wherein the graded buffer layer comprises at least three layers of aluminum gallium nitride (AIGaN), wherein each of the at least three layers has a different amount of an element common to the at least three layers, and wherein the graded buffer layer is doped with carbon or iron; a first strained layer superlattice (SLS) layer arranged over and directly contacting the graded buffer layer, wherein the first SLS layer has a first compressive stress, wherein the first SLS layer comprises a first plurality of alternating layers of aluminum nitride (AIN) and gallium nitride (GaN), and wherein the first plurality of alternating layers of AIN and GaN collectively produce the first compressive stress; a first buffer layer arranged over and directly contacting the first SLS layer, wherein the first buffer layer consists essentially of a single GaN layer doped with carbon or iron, and wherein the first buffer layer has a tensile stress that counteracts the first compressive stress; a second SLS layer arranged over and directly contacting the first buffer layer, wherein the second SLS layer has a second compressive stress, wherein the second SLS layer comprises a second plurality of alternating layers of AIN and GaN, and wherein the second plurality of alternating layers of AIN and GaN collectively produce the second compressive stress; a second buffer layer arranged over and directly contacting the second SLS layer, wherein the second buffer layer consists essentially of a single GaN layer doped with carbon or iron, and wherein the second buffer layer has a tensile stress that counteracts the second compressive stress; a channel layer arranged over and directly contacting the second buffer layer, wherein the channel layer comprises a single undoped GaN layer; and an active layer arranged over and directly contacting the channel layer, wherein the active layer comprises AIGaN, and wherein the channel layer and th e active layer collectively define a heterojunction. Currently amended
The transistor according to claim 34, further comprising: a gate electrode arranged over the active layer and between a source electrode and a drain electrode, wherein a first portion of the source electrode and a first portion of the drain electrode directly contact the active layer; and a dielectric layer arranged over and directly contacting the active layer, wherein the dielectric layer separates the gate electrode, a second portion of the source electrode, and a second portion of the drain electrode from the active layer, and wherein the dielectric layer is continuously planar from a sidewall of the first portion of the source electrode to a sidewall of the first portion of the drain electrode. Previously presented
Canceled
Layer stacks claimed or described, ordered top of device to substrate.
GaN transistor with multi-SLS structure (generic)
Materials described outside the worked examples.
strained layer superlattice (SLS) layer
aluminum nitride
AlN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
high resistivity GaN buffer layer doping concentration (carbon) | ≥ 10000000000000000000 cm⁻³ | GaN |
GaN channel layer carbon concentration upper limit |
Related documents with shared materials, methods, properties, or citations.
GaN transistor with multi-SLS structure on silicon substrate (claim 20)
GaN transistor with seed layer, graded buffer, and dual SLS/buffer pairs (claim 34)
gallium nitride (doped)
GaN
aluminum gallium nitride
AlGaN
silicon substrate
Si
GaN |
first SLS layer carbon or iron concentration | ≥ 50000000000000000000 cm⁻³ | strained layer superlattice (SLS) layer |
Thickness | 0.2–0.5 µm | — |
Thickness | 0.5–2 µm | — |
Thickness | 800–2000 nm | — |
Thickness | 20–100 nm | — |
Thickness | 50–200 nm | — |
Thickness | 0.2–1.5 µm | — |
Thickness | 10–30 nm | — |
Pressure | 20–100 pa | — |
Thickness | 0.1–1.5 µm | — |
Thickness | 0.2–1 µm | — |
Thickness | 0.2–1.5 nm | — |
Thickness | 2–20 nm | — |
Thickness | 10–200 nm | — |
Thickness | 2–8 nm | — |
Thickness | ≤ 4 µm | — |
Thickness | ≥ 50000000000000000000 cm | — |
Thickness | ≥ 10 mm | — |
Thickness | ≥ 500000000000000000 cm | — |
GaN transistor with multi-SLS structure on silicon substrate (claim 20)
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gallium nitride (doped)
GaN
aluminum gallium nitride
AlGaN
silicon substrate
Si
GaN |
first SLS layer carbon or iron concentration | ≥ 50000000000000000000 cm⁻³ | strained layer superlattice (SLS) layer |
Thickness | 0.2–0.5 µm | — |
Thickness | 0.5–2 µm | — |
Thickness | 800–2000 nm | — |
Thickness | 20–100 nm | — |
Thickness | 50–200 nm | — |
Thickness | 0.2–1.5 µm | — |
Thickness | 10–30 nm | — |
Pressure | 20–100 pa | — |
Thickness | 0.1–1.5 µm | — |
Thickness | 0.2–1 µm | — |
Thickness | 0.2–1.5 nm | — |
Thickness | 2–20 nm | — |
Thickness | 10–200 nm | — |
Thickness | 2–8 nm | — |
Thickness | ≤ 4 µm | — |
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Thickness | ≥ 10 mm | — |
Thickness | ≥ 500000000000000000 cm | — |
GaN transistor with multi-SLS structure on silicon substrate (claim 20)
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gallium nitride (doped)
GaN
aluminum gallium nitride
AlGaN
silicon substrate
Si
GaN |
first SLS layer carbon or iron concentration | ≥ 50000000000000000000 cm⁻³ | strained layer superlattice (SLS) layer |
Thickness | 0.2–0.5 µm | — |
Thickness | 0.5–2 µm | — |
Thickness | 800–2000 nm | — |
Thickness | 20–100 nm | — |
Thickness | 50–200 nm | — |
Thickness | 0.2–1.5 µm | — |
Thickness | 10–30 nm | — |
Pressure | 20–100 pa | — |
Thickness | 0.1–1.5 µm | — |
Thickness | 0.2–1 µm | — |
Thickness | 0.2–1.5 nm | — |
Thickness | 2–20 nm | — |
Thickness | 10–200 nm | — |
Thickness | 2–8 nm | — |
Thickness | ≤ 4 µm | — |
Thickness | ≥ 50000000000000000000 cm | — |
Thickness | ≥ 10 mm | — |
Thickness | ≥ 500000000000000000 cm | — |
GaN transistor with multi-SLS structure on silicon substrate (claim 20)
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gallium nitride (doped)
GaN
aluminum gallium nitride
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silicon substrate
Si
GaN |
first SLS layer carbon or iron concentration | ≥ 50000000000000000000 cm⁻³ | strained layer superlattice (SLS) layer |
Thickness | 0.2–0.5 µm | — |
Thickness | 0.5–2 µm | — |
Thickness | 800–2000 nm | — |
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Thickness | 50–200 nm | — |
Thickness | 0.2–1.5 µm | — |
Thickness | 10–30 nm | — |
Pressure | 20–100 pa | — |
Thickness | 0.1–1.5 µm | — |
Thickness | 0.2–1 µm | — |
Thickness | 0.2–1.5 nm | — |
Thickness | 2–20 nm | — |
Thickness | 10–200 nm | — |
Thickness | 2–8 nm | — |
Thickness | ≤ 4 µm | — |
Thickness | ≥ 50000000000000000000 cm | — |
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