Patent
US 9,929,079LEADLESS ELECTRONIC PACKAGES FOR GAN DEVICES
Daniel Marvin Kinzer
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 9,929,079Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the invention; [0015]
FIG. 2C is an isometric view of the bottom of the half-bridge component illustrated in
FIG. 3 is a plan view of the inside of a half-bridge component with the encapsulant removed according to an embodiment of the invention; [0019]
FIG. 4 is a plan view of the inside of a half-bridge component with the encapsulant removed according to an embodiment of the invention; [0020]
FIG. 5 B is a cross-sectional view of the inside of a the half-bridge component illustrated in
FIG. 6 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the invention; [0023]
FIG. 7 B is a plan view of the bottom of the electronic component illustrated in
FIG. 8 is a plan view of the inside of an electronic component with the encapsulant removed according to an embodiment of the invention; and [0026]
FIG. 9 is method of manufacturing an electronic component according to an embodiment of the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic component comprising: a first lead, a second lead, and a third lead; at least a first semiconductor device having a device top surface opposite a device bottom surface, wherein the device bottom surface is attached to a top surface of the first lead and the device top surface includes at least one source terminal that is electrically coupled to the first lead, at least one drain terminal that is electrically coupled to the second lead and at least one input terminal that is electrically coupled to the third lead; and an electrically insulative encapsulant formed around the at least a first semiconductor device and around at least a portion of the first lead, the second lead and the third lead.
The electronic component of claim 1 further comprising a second semiconductor device attached to the second lead.
The electronic component of claim 1 wherein the first lead is separated from the second lead by a distance of 0.8 to 3.0 millimeters.
The electronic component of claim 1 wherein the third lead is a PW M input.
The electronic component of claim 1 wherein the at least a first semiconductor device includes a low side transistor monolithically integrated with a low side drive circuit.
The electronic component of claim 1 wherein the at least a first semiconductor device includes a transistor having a source coupled to the at least one source terminal, a drain coupled to at least one drain terminal and a gate coupled to the at least one input terminal.
The electronic component of claim 1 wherein the device top surface of the at least a first semiconductor device includes a level shift output terminal that is configured to be electrically coupled to a level shift input on a second semiconductor device.
The electronic component of claim 1 wherein the at least a first semiconductor device includes a bidirectional transistor.
The electronic component of claim 1 wherein the first GaN-based die includes a low side transistor monolithically integrated with a low side drive circuit.
The electronic component of claim 1 wherein the first GaN-based die includes a transistor having a source coupled to the one or more source terminals, a drain coupled to at least one drain terminal and a gate coupled to one of the one or more input terminals.
An electronic component comprising: an electrically conductive package base including a first lead, a second lead, and a third lead; a first GaN-based die having a top surface opposite a bottom surface, wherein the bottom surface is attached to the first lead and the top surface includes one or more source terminals that are electrically coupled to the first lead, one or more drain terminals that are electrically coupled to the second lead and one or more input terminals that are electrically coupled to the third lead; and an encapsulant formed over the first GaN-based die and at least a top surface of the electrically conductive package base.
The electronic component of claim 23 further comprising a second GaN- based die attached to the second lead.
A packaged electronic device comprising: a package including a leadframe having a first lead, a second lead, and a third lead; at least a first integrated circuit (IC) die having a top surface opposite a bottom surface, wherein the bottom surface is positioned on the first lead and the top surface includes one or more source terminals that are electrically coupled to the first lead, one or more drain terminals that are electrically coupled to the second lead and one or more input terminals that are electrically coupled to the third lead; and an electrically insulative encapsulant formed around the at least a first IC and around at least a portion of the leadframe.
The packaged electronic device of claim 29 further comprising a second integrated circuit attached to the second lead.
The packaged electronic device of claim 29 wherein the at least a first integrated circuit includes a low side transistor monolithically integrated with a low side drive circuit.
The packaged electronic device of claim 29 wherein the at least a first integrated circuit includes a transistor having a source coupled to the one or more source terminals, a drain coupled
Layer stacks claimed or described, ordered top of device to substrate.
electronic component with semiconductor device on leadframe
high side transistor with integrated high side drive circuit
low side transistor with integrated low side drive circuit
Materials described outside the worked examples.
semiconductor device
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
specific_on_resistance_range_GaN_device | 1–10 | GaN |
Thickness | 0.8–3 mm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,929,079Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the invention; [0015]
FIG. 2C is an isometric view of the bottom of the half-bridge component illustrated in
FIG. 3 is a plan view of the inside of a half-bridge component with the encapsulant removed according to an embodiment of the invention; [0019]
FIG. 4 is a plan view of the inside of a half-bridge component with the encapsulant removed according to an embodiment of the invention; [0020]
FIG. 5 B is a cross-sectional view of the inside of a the half-bridge component illustrated in
FIG. 6 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the invention; [0023]
FIG. 7 B is a plan view of the bottom of the electronic component illustrated in
FIG. 8 is a plan view of the inside of an electronic component with the encapsulant removed according to an embodiment of the invention; and [0026]
FIG. 9 is method of manufacturing an electronic component according to an embodiment of the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic component comprising: a first lead, a second lead, and a third lead; at least a first semiconductor device having a device top surface opposite a device bottom surface, wherein the device bottom surface is attached to a top surface of the first lead and the device top surface includes at least one source terminal that is electrically coupled to the first lead, at least one drain terminal that is electrically coupled to the second lead and at least one input terminal that is electrically coupled to the third lead; and an electrically insulative encapsulant formed around the at least a first semiconductor device and around at least a portion of the first lead, the second lead and the third lead.
The electronic component of claim 1 further comprising a second semiconductor device attached to the second lead.
The electronic component of claim 1 wherein the first lead is separated from the second lead by a distance of 0.8 to 3.0 millimeters.
The electronic component of claim 1 wherein the third lead is a PW M input.
The electronic component of claim 1 wherein the at least a first semiconductor device includes a low side transistor monolithically integrated with a low side drive circuit.
The electronic component of claim 1 wherein the at least a first semiconductor device includes a transistor having a source coupled to the at least one source terminal, a drain coupled to at least one drain terminal and a gate coupled to the at least one input terminal.
The electronic component of claim 1 wherein the device top surface of the at least a first semiconductor device includes a level shift output terminal that is configured to be electrically coupled to a level shift input on a second semiconductor device.
The electronic component of claim 1 wherein the at least a first semiconductor device includes a bidirectional transistor.
The electronic component of claim 1 wherein the first GaN-based die includes a low side transistor monolithically integrated with a low side drive circuit.
The electronic component of claim 1 wherein the first GaN-based die includes a transistor having a source coupled to the one or more source terminals, a drain coupled to at least one drain terminal and a gate coupled to one of the one or more input terminals.
An electronic component comprising: an electrically conductive package base including a first lead, a second lead, and a third lead; a first GaN-based die having a top surface opposite a bottom surface, wherein the bottom surface is attached to the first lead and the top surface includes one or more source terminals that are electrically coupled to the first lead, one or more drain terminals that are electrically coupled to the second lead and one or more input terminals that are electrically coupled to the third lead; and an encapsulant formed over the first GaN-based die and at least a top surface of the electrically conductive package base.
The electronic component of claim 23 further comprising a second GaN- based die attached to the second lead.
A packaged electronic device comprising: a package including a leadframe having a first lead, a second lead, and a third lead; at least a first integrated circuit (IC) die having a top surface opposite a bottom surface, wherein the bottom surface is positioned on the first lead and the top surface includes one or more source terminals that are electrically coupled to the first lead, one or more drain terminals that are electrically coupled to the second lead and one or more input terminals that are electrically coupled to the third lead; and an electrically insulative encapsulant formed around the at least a first IC and around at least a portion of the leadframe.
The packaged electronic device of claim 29 further comprising a second integrated circuit attached to the second lead.
The packaged electronic device of claim 29 wherein the at least a first integrated circuit includes a low side transistor monolithically integrated with a low side drive circuit.
The packaged electronic device of claim 29 wherein the at least a first integrated circuit includes a transistor having a source coupled to the one or more source terminals, a drain coupled
Layer stacks claimed or described, ordered top of device to substrate.
electronic component with semiconductor device on leadframe
high side transistor with integrated high side drive circuit
low side transistor with integrated low side drive circuit
Materials described outside the worked examples.
semiconductor device
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
specific_on_resistance_range_GaN_device | 1–10 | GaN |
Thickness | 0.8–3 mm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,929,079Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the invention; [0015]
FIG. 2C is an isometric view of the bottom of the half-bridge component illustrated in
FIG. 3 is a plan view of the inside of a half-bridge component with the encapsulant removed according to an embodiment of the invention; [0019]
FIG. 4 is a plan view of the inside of a half-bridge component with the encapsulant removed according to an embodiment of the invention; [0020]
FIG. 5 B is a cross-sectional view of the inside of a the half-bridge component illustrated in
FIG. 6 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the invention; [0023]
FIG. 7 B is a plan view of the bottom of the electronic component illustrated in
FIG. 8 is a plan view of the inside of an electronic component with the encapsulant removed according to an embodiment of the invention; and [0026]
FIG. 9 is method of manufacturing an electronic component according to an embodiment of the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic component comprising: a first lead, a second lead, and a third lead; at least a first semiconductor device having a device top surface opposite a device bottom surface, wherein the device bottom surface is attached to a top surface of the first lead and the device top surface includes at least one source terminal that is electrically coupled to the first lead, at least one drain terminal that is electrically coupled to the second lead and at least one input terminal that is electrically coupled to the third lead; and an electrically insulative encapsulant formed around the at least a first semiconductor device and around at least a portion of the first lead, the second lead and the third lead.
The electronic component of claim 1 further comprising a second semiconductor device attached to the second lead.
The electronic component of claim 1 wherein the first lead is separated from the second lead by a distance of 0.8 to 3.0 millimeters.
The electronic component of claim 1 wherein the third lead is a PW M input.
The electronic component of claim 1 wherein the at least a first semiconductor device includes a low side transistor monolithically integrated with a low side drive circuit.
The electronic component of claim 1 wherein the at least a first semiconductor device includes a transistor having a source coupled to the at least one source terminal, a drain coupled to at least one drain terminal and a gate coupled to the at least one input terminal.
The electronic component of claim 1 wherein the device top surface of the at least a first semiconductor device includes a level shift output terminal that is configured to be electrically coupled to a level shift input on a second semiconductor device.
The electronic component of claim 1 wherein the at least a first semiconductor device includes a bidirectional transistor.
The electronic component of claim 1 wherein the first GaN-based die includes a low side transistor monolithically integrated with a low side drive circuit.
The electronic component of claim 1 wherein the first GaN-based die includes a transistor having a source coupled to the one or more source terminals, a drain coupled to at least one drain terminal and a gate coupled to one of the one or more input terminals.
An electronic component comprising: an electrically conductive package base including a first lead, a second lead, and a third lead; a first GaN-based die having a top surface opposite a bottom surface, wherein the bottom surface is attached to the first lead and the top surface includes one or more source terminals that are electrically coupled to the first lead, one or more drain terminals that are electrically coupled to the second lead and one or more input terminals that are electrically coupled to the third lead; and an encapsulant formed over the first GaN-based die and at least a top surface of the electrically conductive package base.
The electronic component of claim 23 further comprising a second GaN- based die attached to the second lead.
A packaged electronic device comprising: a package including a leadframe having a first lead, a second lead, and a third lead; at least a first integrated circuit (IC) die having a top surface opposite a bottom surface, wherein the bottom surface is positioned on the first lead and the top surface includes one or more source terminals that are electrically coupled to the first lead, one or more drain terminals that are electrically coupled to the second lead and one or more input terminals that are electrically coupled to the third lead; and an electrically insulative encapsulant formed around the at least a first IC and around at least a portion of the leadframe.
The packaged electronic device of claim 29 further comprising a second integrated circuit attached to the second lead.
The packaged electronic device of claim 29 wherein the at least a first integrated circuit includes a low side transistor monolithically integrated with a low side drive circuit.
The packaged electronic device of claim 29 wherein the at least a first integrated circuit includes a transistor having a source coupled to the one or more source terminals, a drain coupled
Layer stacks claimed or described, ordered top of device to substrate.
electronic component with semiconductor device on leadframe
high side transistor with integrated high side drive circuit
low side transistor with integrated low side drive circuit
Materials described outside the worked examples.
semiconductor device
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
specific_on_resistance_range_GaN_device | 1–10 | GaN |
Thickness | 0.8–3 mm |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,929,079Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the invention; [0015]
FIG. 2C is an isometric view of the bottom of the half-bridge component illustrated in
FIG. 3 is a plan view of the inside of a half-bridge component with the encapsulant removed according to an embodiment of the invention; [0019]
FIG. 4 is a plan view of the inside of a half-bridge component with the encapsulant removed according to an embodiment of the invention; [0020]
FIG. 5 B is a cross-sectional view of the inside of a the half-bridge component illustrated in
FIG. 6 is a simplified schematic of a half bridge power conversion circuit according to an embodiment of the invention; [0023]
FIG. 7 B is a plan view of the bottom of the electronic component illustrated in
FIG. 8 is a plan view of the inside of an electronic component with the encapsulant removed according to an embodiment of the invention; and [0026]
FIG. 9 is method of manufacturing an electronic component according to an embodiment of the invention.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
An electronic component comprising: a first lead, a second lead, and a third lead; at least a first semiconductor device having a device top surface opposite a device bottom surface, wherein the device bottom surface is attached to a top surface of the first lead and the device top surface includes at least one source terminal that is electrically coupled to the first lead, at least one drain terminal that is electrically coupled to the second lead and at least one input terminal that is electrically coupled to the third lead; and an electrically insulative encapsulant formed around the at least a first semiconductor device and around at least a portion of the first lead, the second lead and the third lead.
The electronic component of claim 1 further comprising a second semiconductor device attached to the second lead.
The electronic component of claim 1 wherein the first lead is separated from the second lead by a distance of 0.8 to 3.0 millimeters.
The electronic component of claim 1 wherein the third lead is a PW M input.
The electronic component of claim 1 wherein the at least a first semiconductor device includes a low side transistor monolithically integrated with a low side drive circuit.
The electronic component of claim 1 wherein the at least a first semiconductor device includes a transistor having a source coupled to the at least one source terminal, a drain coupled to at least one drain terminal and a gate coupled to the at least one input terminal.
The electronic component of claim 1 wherein the device top surface of the at least a first semiconductor device includes a level shift output terminal that is configured to be electrically coupled to a level shift input on a second semiconductor device.
The electronic component of claim 1 wherein the at least a first semiconductor device includes a bidirectional transistor.
The electronic component of claim 1 wherein the first GaN-based die includes a low side transistor monolithically integrated with a low side drive circuit.
The electronic component of claim 1 wherein the first GaN-based die includes a transistor having a source coupled to the one or more source terminals, a drain coupled to at least one drain terminal and a gate coupled to one of the one or more input terminals.
An electronic component comprising: an electrically conductive package base including a first lead, a second lead, and a third lead; a first GaN-based die having a top surface opposite a bottom surface, wherein the bottom surface is attached to the first lead and the top surface includes one or more source terminals that are electrically coupled to the first lead, one or more drain terminals that are electrically coupled to the second lead and one or more input terminals that are electrically coupled to the third lead; and an encapsulant formed over the first GaN-based die and at least a top surface of the electrically conductive package base.
The electronic component of claim 23 further comprising a second GaN- based die attached to the second lead.
A packaged electronic device comprising: a package including a leadframe having a first lead, a second lead, and a third lead; at least a first integrated circuit (IC) die having a top surface opposite a bottom surface, wherein the bottom surface is positioned on the first lead and the top surface includes one or more source terminals that are electrically coupled to the first lead, one or more drain terminals that are electrically coupled to the second lead and one or more input terminals that are electrically coupled to the third lead; and an electrically insulative encapsulant formed around the at least a first IC and around at least a portion of the leadframe.
The packaged electronic device of claim 29 further comprising a second integrated circuit attached to the second lead.
The packaged electronic device of claim 29 wherein the at least a first integrated circuit includes a low side transistor monolithically integrated with a low side drive circuit.
The packaged electronic device of claim 29 wherein the at least a first integrated circuit includes a transistor having a source coupled to the one or more source terminals, a drain coupled
Layer stacks claimed or described, ordered top of device to substrate.
electronic component with semiconductor device on leadframe
high side transistor with integrated high side drive circuit
low side transistor with integrated low side drive circuit
Materials described outside the worked examples.
semiconductor device
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
specific_on_resistance_range_GaN_device | 1–10 | GaN |
Thickness | 0.8–3 mm |
Related documents with shared materials, methods, properties, or citations.
electronic component with GaN-based die on conductive package base
packaged electronic device with IC die on leadframe
silicon
Si
electrically insulative encapsulant
| — |
Thickness | 1.8–2.8 mm | — |
Thickness | 0.7–1.2 mm | — |
Thickness | 50–250 µm | — |
Thickness | 100–200 µm | — |
Thickness | 0.6–2 mm | — |
Thickness | 0.8–1.2 mm | — |
Thickness | 1–4 mm | — |
Thickness | 1.1–3.1 mm | — |
Thickness | 1.6–2.6 mm | — |
Thickness | 2–2.2 mm | — |
Thickness | 50000–1000000 nm | — |
Thickness | 150–500 µm | — |
Thickness | 0.5–4 mm | — |
Thickness | 1–3 mm | — |
Thickness | 2–3 mm | — |
Thickness | 0.5–1.5 mm | — |
Thickness | ≥ 1.5 mm | — |
Thickness | ≥ 0.8 mm | — |
Thickness | ≥ 1 mm | — |
Thickness | ≥ 2 mm | — |
Thickness | ≥ 2.8 mm | — |
Thickness | 1.1–3 mm | — |
electronic component with GaN-based die on conductive package base
packaged electronic device with IC die on leadframe
silicon
Si
electrically insulative encapsulant
| — |
Thickness | 1.8–2.8 mm | — |
Thickness | 0.7–1.2 mm | — |
Thickness | 50–250 µm | — |
Thickness | 100–200 µm | — |
Thickness | 0.6–2 mm | — |
Thickness | 0.8–1.2 mm | — |
Thickness | 1–4 mm | — |
Thickness | 1.1–3.1 mm | — |
Thickness | 1.6–2.6 mm | — |
Thickness | 2–2.2 mm | — |
Thickness | 50000–1000000 nm | — |
Thickness | 150–500 µm | — |
Thickness | 0.5–4 mm | — |
Thickness | 1–3 mm | — |
Thickness | 2–3 mm | — |
Thickness | 0.5–1.5 mm | — |
Thickness | ≥ 1.5 mm | — |
Thickness | ≥ 0.8 mm | — |
Thickness | ≥ 1 mm | — |
Thickness | ≥ 2 mm | — |
Thickness | ≥ 2.8 mm | — |
Thickness | 1.1–3 mm | — |
electronic component with GaN-based die on conductive package base
packaged electronic device with IC die on leadframe
silicon
Si
electrically insulative encapsulant
| — |
Thickness | 1.8–2.8 mm | — |
Thickness | 0.7–1.2 mm | — |
Thickness | 50–250 µm | — |
Thickness | 100–200 µm | — |
Thickness | 0.6–2 mm | — |
Thickness | 0.8–1.2 mm | — |
Thickness | 1–4 mm | — |
Thickness | 1.1–3.1 mm | — |
Thickness | 1.6–2.6 mm | — |
Thickness | 2–2.2 mm | — |
Thickness | 50000–1000000 nm | — |
Thickness | 150–500 µm | — |
Thickness | 0.5–4 mm | — |
Thickness | 1–3 mm | — |
Thickness | 2–3 mm | — |
Thickness | 0.5–1.5 mm | — |
Thickness | ≥ 1.5 mm | — |
Thickness | ≥ 0.8 mm | — |
Thickness | ≥ 1 mm | — |
Thickness | ≥ 2 mm | — |
Thickness | ≥ 2.8 mm | — |
Thickness | 1.1–3 mm | — |
electronic component with GaN-based die on conductive package base
packaged electronic device with IC die on leadframe
silicon
Si
electrically insulative encapsulant
| — |
Thickness | 1.8–2.8 mm | — |
Thickness | 0.7–1.2 mm | — |
Thickness | 50–250 µm | — |
Thickness | 100–200 µm | — |
Thickness | 0.6–2 mm | — |
Thickness | 0.8–1.2 mm | — |
Thickness | 1–4 mm | — |
Thickness | 1.1–3.1 mm | — |
Thickness | 1.6–2.6 mm | — |
Thickness | 2–2.2 mm | — |
Thickness | 50000–1000000 nm | — |
Thickness | 150–500 µm | — |
Thickness | 0.5–4 mm | — |
Thickness | 1–3 mm | — |
Thickness | 2–3 mm | — |
Thickness | 0.5–1.5 mm | — |
Thickness | ≥ 1.5 mm | — |
Thickness | ≥ 0.8 mm | — |
Thickness | ≥ 1 mm | — |
Thickness | ≥ 2 mm | — |
Thickness | ≥ 2.8 mm | — |
Thickness | 1.1–3 mm | — |