The m eth od o f cla im 1 fu rther co mpris ng' 036 92. B₁₅₅C -13- Application forming, w ithi n the re action ch am ber, a silicon nitride l ayer ato p the oxy-ni tride lay er; a nd removing the wafer from the react ion chamber 13. The m eth od o f c laim 1 w here in the oxy-nitrde la yer is formed wi th a graded nitrogen composition that va n es from a hi ghes t at omi c per centage at or nea r the nitrde la yer to a low est at ormc percentage at or near a top surfac e of the oxy-n itri de layer 14 The m eth od of claim 1 where i n the n itride-b ased sem iconductor la yer compris es AI GaN 15 A method of fab ricating a multvl ayer stru ctu re f or a heter oJunction field- effect trans istor (HFET) device comprising. (a) exposing, wi thin the reacti on chamber, a top surface of a nitride- base d sem iconducto r layer to a first alu min um s ource. (b) exposi ng, withi n the react ion chamber, the w afer to a nitro gen (N) p las m a res ulting in the fo rmat ion o f an alum inum nitrid e (AIN) la yer at op the n i tride-base d se miconductor la yer, (c) exposing, within the react io n cha m ber, a top surface o f the AIN la yer t o a sec ond alu minu m s ou rce and (d) e xposing, within the react io n cha m ber, the wafer t o a nitrogen-ox ygen plas ma, res ulti ng i n the f ormation of an alum inum oxy- nit ri de (AION) layer atop the AIN la yer. wherein the nit ride la yer c ompr ses a p ass i vat ion lay er and the oxy- nit ride layer c omprn ses a gate d i elect ri c of the pow er transistor dev ice 036 92. B₁₅₅C -14-Application 16. The m eth o d of claim 15 wherein the first alu minum sou rce and the second alum inum sourc e b o th compnr se a tn-m eth y l al uminum (TMA) source 17 The m eth o d of cla im 15 furt her c ompnrsing re p eatin g steps (a) and (b) until the A IN l ayer is f o rmed t o a first th i ckness 18 The m eth o d of claim 17 wherein the first th ic kness is i n a ra nge o f a bou t 2-10 nm th ick. 19 The m eth od of claim 15 fu rther com pris ing repe ating steps (c) and (d) until the AI ON layer is f o rmed to a se co nd thi ck ness 20 The method of claim 19 w herein the second th ick ness is in a range of a bout 10 -25 nm th ick. 21 The m eth od of cla im 15 fu rther c om pris ing forming, wi thin the reacti on chamber, a sil ico n n itri de layer atop the AI O N layer 22 The method o f claim 15 w herein the AIO N layer is f o rmed w ith a graded nitro gen c ompositio n that va ri es from a highest at omi c percentage at o r near the nit ri de layer t o a low est at orm c percentage at o r near a t op surface o f the ox y-nitride layer 23 The m eth od o f cla im 15 wherein the nit ride- based se miconductor l ayer comprises AIGaN 036 92. B₁₅₅C -15- Application 24 A nitri de-ba se d heter o-junctio n f i eld-effect tran sis tor (HFVET) device comprising' a f irs t active semiconducto r layer, a sec on d act ive semiconducto r layer d ispos ed at op the f i rst active sem iconducto r layer, a t wo-dimension al electr on g as be ing forme d th e rebet ween, a multi -layer structu re that includes a firs t n itri de-ba s ed passi vat ion layer dispo sed d i rectly on the secon d a ctiv e sem icondu ctor layer, an d a n o xy- nitri de layer dispo sed d i rect ly on the f irst nitr de-ba s ed pa ssi vati on layer, the f irst nitrdeb ased p ass ivation layer hav in g a f i rst th ickn ess a n d the o xy- ni tride l ayer hav ing a sec ond thickness, the oxy-nitrde layer comprsing a g ate d i elect ric o f the nitride- based HFET dev i ce, a nd spaced-apart s ource an d dra in ohmic contacts directly on, or in re ce sses t hat exten d thr oug h t h e sec on d act iv e se miconducto r layer. 25 The nitr de-based HF ET dev ic e of cla im 24 w here in the first nitri de-ba sed pass ivation l ayer compri se AIN 26 The nitri de-ba sed FE T dev ic e of cla im 24 w her ein the first nitride-based pass ivation layer c ompri se SiN 27 The nit ri de- bas ed FE T de vice of claim 24 wherei n t he firs t t hicknesis is in a ran g e of ab out 2 -10 nm thick. 28 The ni tride-based FE T de vice o f cla im 24 w here i n the oxy- nit n de layer comprise s AI ON. 036 92. B₁₅₅C -16- Application 29. The nitrde-based HFET device of a m 24 wherei n the second thicknes s i s in a range of about 10 -25 nm th ick ABSTRA CT O F THE DISCLOSURE A m eth od of fabricating a m ult -layer structu re f or a pow er tr ansistor device incl ude s per forming, withi n a rea ction chamber, a nitrogen pl asma st rk e, result ing in the f ormation of a nitride layer directly on a nitride-based active semiconductor layer A top surf ace o f the n itri de lay er i s the n exp os ed t o a second source A su bsequ ent nitrogen-oxygen plasm a st rik e res ul ts in the f ormation o f a n oxy-nitrde lay er directly o n the nitri de la yer The nitride layer compris es a p assivation lay er and the oxy- nitri de layer compri ses a g ate die lectric o f the p ow er tra nsistor device. 036 92. B₁₅₅C -18- Application SVG 14154355.01-14-2014.HQFF₄ZYVPXXIFW3.SPEC₁1165086.3.332.3048.2178.3091.svg 0.143 6.153 Drawing Black and white Claims What is claimed is:

Th e method of claim 34 wherein the fi rst thickness is in a range of about 2-10 nm thick.

The m eth od o f cla im 1 fu rther co mpris ng' 036 92. B₁₅₅C -13- Application forming, w ithi n the re action ch am ber, a silicon nitride l ayer ato p the oxy-ni tride lay er; a nd removing the wafer from the react ion chamber 13. The m eth od o f c laim 1 w here in the oxy-nitrde la yer is formed wi th a graded nitrogen composition that va n es from a hi ghes t at omi c per centage at or nea r the nitrde la yer to a low est at ormc percentage at or near a top surfac e of the oxy-n itri de layer 14 The m eth od of claim 1 where i n the n itride-b ased sem iconductor la yer compris es AI GaN 15 A method of fab ricating a multvl ayer stru ctu re f or a heter oJunction field- effect trans istor (HFET) device comprising. (a) exposing, wi thin the reacti on chamber, a top surface of a nitride- base d sem iconducto r layer to a first alu min um s ource. (b) exposi ng, withi n the react ion chamber, the w afer to a nitro gen (N) p las m a res ulting in the fo rmat ion o f an alum inum nitrid e (AIN) la yer at op the n i tride-base d se miconductor la yer, (c) exposing, within the react io n cha m ber, a top surface o f the AIN la yer t o a sec ond alu minu m s ou rce and (d) e xposing, within the react io n cha m ber, the wafer t o a nitrogen-ox ygen plas ma, res ulti ng i n the f ormation of an alum inum oxy- nit ri de (AION) layer atop the AIN la yer. wherein the nit ride la yer c ompr ses a p ass i vat ion lay er and the oxy- nit ride layer c omprn ses a gate d i elect ri c of the pow er transistor dev ice 036 92. B₁₅₅C -14-Application 16. The m eth o d of claim 15 wherein the first alu minum sou rce and the second alum inum sourc e b o th compnr se a tn-m eth y l al uminum (TMA) source 17 The m eth o d of cla im 15 furt her c ompnrsing re p eatin g steps (a) and (b) until the A IN l ayer is f o rmed t o a first th i ckness 18 The m eth o d of claim 17 wherein the first th ic kness is i n a ra nge o f a bou t 2-10 nm th ick. 19 The m eth od of claim 15 fu rther com pris ing repe ating steps (c) and (d) until the AI ON layer is f o rmed to a se co nd thi ck ness 20 The method of claim 19 w herein the second th ick ness is in a range of a bout 10 -25 nm th ick. 21 The m eth od of cla im 15 fu rther c om pris ing forming, wi thin the reacti on chamber, a sil ico n n itri de layer atop the AI O N layer 22 The method o f claim 15 w herein the AIO N layer is f o rmed w ith a graded nitro gen c ompositio n that va ri es from a highest at omi c percentage at o r near the nit ri de layer t o a low est at orm c percentage at o r near a t op surface o f the ox y-nitride layer 23 The m eth od o f cla im 15 wherein the nit ride- based se miconductor l ayer comprises AIGaN 036 92. B₁₅₅C -15- Application 24 A nitri de-ba se d heter o-junctio n f i eld-effect tran sis tor (HFVET) device comprising' a f irs t active semiconducto r layer, a sec on d act ive semiconducto r layer d ispos ed at op the f i rst active sem iconducto r layer, a t wo-dimension al electr on g as be ing forme d th e rebet ween, a multi -layer structu re that includes a firs t n itri de-ba s ed passi vat ion layer dispo sed d i rectly on the secon d a ctiv e sem icondu ctor layer, an d a n o xy- nitri de layer dispo sed d i rect ly on the f irst nitr de-ba s ed pa ssi vati on layer, the f irst nitrdeb ased p ass ivation layer hav in g a f i rst th ickn ess a n d the o xy- ni tride l ayer hav ing a sec ond thickness, the oxy-nitrde layer comprsing a g ate d i elect ric o f the nitride- based HFET dev i ce, a nd spaced-apart s ource an d dra in ohmic contacts directly on, or in re ce sses t hat exten d thr oug h t h e sec on d act iv e se miconducto r layer. 25 The nitr de-based HF ET dev ic e of cla im 24 w here in the first nitri de-ba sed pass ivation l ayer compri se AIN 26 The nitri de-ba sed FE T dev ic e of cla im 24 w her ein the first nitride-based pass ivation layer c ompri se SiN 27 The nit ri de- bas ed FE T de vice of claim 24 wherei n t he firs t t hicknesis is in a ran g e of ab out 2 -10 nm thick. 28 The ni tride-based FE T de vice o f cla im 24 w here i n the oxy- nit n de layer comprise s AI ON. 036 92. B₁₅₅C -16- Application 29. The nitrde-based HFET device of a m 24 wherei n the second thicknes s i s in a range of about 10 -25 nm th ick ABSTRA CT O F THE DISCLOSURE A m eth od of fabricating a m ult -layer structu re f or a pow er tr ansistor device incl ude s per forming, withi n a rea ction chamber, a nitrogen pl asma st rk e, result ing in the f ormation of a nitride layer directly on a nitride-based active semiconductor layer A top surf ace o f the n itri de lay er i s the n exp os ed t o a second source A su bsequ ent nitrogen-oxygen plasm a st rik e res ul ts in the f ormation o f a n oxy-nitrde lay er directly o n the nitri de la yer The nitride layer compris es a p assivation lay er and the oxy- nitri de layer compri ses a g ate die lectric o f the p ow er tra nsistor device. 036 92. B₁₅₅C -18- Application SVG 14154355.01-14-2014.HQFF₄ZYVPXXIFW3.SPEC₁1165086.3.332.3048.2178.3091.svg 0.143 6.153 Drawing Black and white Claims What is claimed is:

Th e method of claim 34 wherein the fi rst thickness is in a range of about 2-10 nm thick.

The m eth od o f cla im 1 fu rther co mpris ng' 036 92. B₁₅₅C -13- Application forming, w ithi n the re action ch am ber, a silicon nitride l ayer ato p the oxy-ni tride lay er; a nd removing the wafer from the react ion chamber 13. The m eth od o f c laim 1 w here in the oxy-nitrde la yer is formed wi th a graded nitrogen composition that va n es from a hi ghes t at omi c per centage at or nea r the nitrde la yer to a low est at ormc percentage at or near a top surfac e of the oxy-n itri de layer 14 The m eth od of claim 1 where i n the n itride-b ased sem iconductor la yer compris es AI GaN 15 A method of fab ricating a multvl ayer stru ctu re f or a heter oJunction field- effect trans istor (HFET) device comprising. (a) exposing, wi thin the reacti on chamber, a top surface of a nitride- base d sem iconducto r layer to a first alu min um s ource. (b) exposi ng, withi n the react ion chamber, the w afer to a nitro gen (N) p las m a res ulting in the fo rmat ion o f an alum inum nitrid e (AIN) la yer at op the n i tride-base d se miconductor la yer, (c) exposing, within the react io n cha m ber, a top surface o f the AIN la yer t o a sec ond alu minu m s ou rce and (d) e xposing, within the react io n cha m ber, the wafer t o a nitrogen-ox ygen plas ma, res ulti ng i n the f ormation of an alum inum oxy- nit ri de (AION) layer atop the AIN la yer. wherein the nit ride la yer c ompr ses a p ass i vat ion lay er and the oxy- nit ride layer c omprn ses a gate d i elect ri c of the pow er transistor dev ice 036 92. B₁₅₅C -14-Application 16. The m eth o d of claim 15 wherein the first alu minum sou rce and the second alum inum sourc e b o th compnr se a tn-m eth y l al uminum (TMA) source 17 The m eth o d of cla im 15 furt her c ompnrsing re p eatin g steps (a) and (b) until the A IN l ayer is f o rmed t o a first th i ckness 18 The m eth o d of claim 17 wherein the first th ic kness is i n a ra nge o f a bou t 2-10 nm th ick. 19 The m eth od of claim 15 fu rther com pris ing repe ating steps (c) and (d) until the AI ON layer is f o rmed to a se co nd thi ck ness 20 The method of claim 19 w herein the second th ick ness is in a range of a bout 10 -25 nm th ick. 21 The m eth od of cla im 15 fu rther c om pris ing forming, wi thin the reacti on chamber, a sil ico n n itri de layer atop the AI O N layer 22 The method o f claim 15 w herein the AIO N layer is f o rmed w ith a graded nitro gen c ompositio n that va ri es from a highest at omi c percentage at o r near the nit ri de layer t o a low est at orm c percentage at o r near a t op surface o f the ox y-nitride layer 23 The m eth od o f cla im 15 wherein the nit ride- based se miconductor l ayer comprises AIGaN 036 92. B₁₅₅C -15- Application 24 A nitri de-ba se d heter o-junctio n f i eld-effect tran sis tor (HFVET) device comprising' a f irs t active semiconducto r layer, a sec on d act ive semiconducto r layer d ispos ed at op the f i rst active sem iconducto r layer, a t wo-dimension al electr on g as be ing forme d th e rebet ween, a multi -layer structu re that includes a firs t n itri de-ba s ed passi vat ion layer dispo sed d i rectly on the secon d a ctiv e sem icondu ctor layer, an d a n o xy- nitri de layer dispo sed d i rect ly on the f irst nitr de-ba s ed pa ssi vati on layer, the f irst nitrdeb ased p ass ivation layer hav in g a f i rst th ickn ess a n d the o xy- ni tride l ayer hav ing a sec ond thickness, the oxy-nitrde layer comprsing a g ate d i elect ric o f the nitride- based HFET dev i ce, a nd spaced-apart s ource an d dra in ohmic contacts directly on, or in re ce sses t hat exten d thr oug h t h e sec on d act iv e se miconducto r layer. 25 The nitr de-based HF ET dev ic e of cla im 24 w here in the first nitri de-ba sed pass ivation l ayer compri se AIN 26 The nitri de-ba sed FE T dev ic e of cla im 24 w her ein the first nitride-based pass ivation layer c ompri se SiN 27 The nit ri de- bas ed FE T de vice of claim 24 wherei n t he firs t t hicknesis is in a ran g e of ab out 2 -10 nm thick. 28 The ni tride-based FE T de vice o f cla im 24 w here i n the oxy- nit n de layer comprise s AI ON. 036 92. B₁₅₅C -16- Application 29. The nitrde-based HFET device of a m 24 wherei n the second thicknes s i s in a range of about 10 -25 nm th ick ABSTRA CT O F THE DISCLOSURE A m eth od of fabricating a m ult -layer structu re f or a pow er tr ansistor device incl ude s per forming, withi n a rea ction chamber, a nitrogen pl asma st rk e, result ing in the f ormation of a nitride layer directly on a nitride-based active semiconductor layer A top surf ace o f the n itri de lay er i s the n exp os ed t o a second source A su bsequ ent nitrogen-oxygen plasm a st rik e res ul ts in the f ormation o f a n oxy-nitrde lay er directly o n the nitri de la yer The nitride layer compris es a p assivation lay er and the oxy- nitri de layer compri ses a g ate die lectric o f the p ow er tra nsistor device. 036 92. B₁₅₅C -18- Application SVG 14154355.01-14-2014.HQFF₄ZYVPXXIFW3.SPEC₁1165086.3.332.3048.2178.3091.svg 0.143 6.153 Drawing Black and white Claims What is claimed is:

Th e method of claim 34 wherein the fi rst thickness is in a range of about 2-10 nm thick.

The m eth od o f cla im 1 fu rther co mpris ng' 036 92. B₁₅₅C -13- Application forming, w ithi n the re action ch am ber, a silicon nitride l ayer ato p the oxy-ni tride lay er; a nd removing the wafer from the react ion chamber 13. The m eth od o f c laim 1 w here in the oxy-nitrde la yer is formed wi th a graded nitrogen composition that va n es from a hi ghes t at omi c per centage at or nea r the nitrde la yer to a low est at ormc percentage at or near a top surfac e of the oxy-n itri de layer 14 The m eth od of claim 1 where i n the n itride-b ased sem iconductor la yer compris es AI GaN 15 A method of fab ricating a multvl ayer stru ctu re f or a heter oJunction field- effect trans istor (HFET) device comprising. (a) exposing, wi thin the reacti on chamber, a top surface of a nitride- base d sem iconducto r layer to a first alu min um s ource. (b) exposi ng, withi n the react ion chamber, the w afer to a nitro gen (N) p las m a res ulting in the fo rmat ion o f an alum inum nitrid e (AIN) la yer at op the n i tride-base d se miconductor la yer, (c) exposing, within the react io n cha m ber, a top surface o f the AIN la yer t o a sec ond alu minu m s ou rce and (d) e xposing, within the react io n cha m ber, the wafer t o a nitrogen-ox ygen plas ma, res ulti ng i n the f ormation of an alum inum oxy- nit ri de (AION) layer atop the AIN la yer. wherein the nit ride la yer c ompr ses a p ass i vat ion lay er and the oxy- nit ride layer c omprn ses a gate d i elect ri c of the pow er transistor dev ice 036 92. B₁₅₅C -14-Application 16. The m eth o d of claim 15 wherein the first alu minum sou rce and the second alum inum sourc e b o th compnr se a tn-m eth y l al uminum (TMA) source 17 The m eth o d of cla im 15 furt her c ompnrsing re p eatin g steps (a) and (b) until the A IN l ayer is f o rmed t o a first th i ckness 18 The m eth o d of claim 17 wherein the first th ic kness is i n a ra nge o f a bou t 2-10 nm th ick. 19 The m eth od of claim 15 fu rther com pris ing repe ating steps (c) and (d) until the AI ON layer is f o rmed to a se co nd thi ck ness 20 The method of claim 19 w herein the second th ick ness is in a range of a bout 10 -25 nm th ick. 21 The m eth od of cla im 15 fu rther c om pris ing forming, wi thin the reacti on chamber, a sil ico n n itri de layer atop the AI O N layer 22 The method o f claim 15 w herein the AIO N layer is f o rmed w ith a graded nitro gen c ompositio n that va ri es from a highest at omi c percentage at o r near the nit ri de layer t o a low est at orm c percentage at o r near a t op surface o f the ox y-nitride layer 23 The m eth od o f cla im 15 wherein the nit ride- based se miconductor l ayer comprises AIGaN 036 92. B₁₅₅C -15- Application 24 A nitri de-ba se d heter o-junctio n f i eld-effect tran sis tor (HFVET) device comprising' a f irs t active semiconducto r layer, a sec on d act ive semiconducto r layer d ispos ed at op the f i rst active sem iconducto r layer, a t wo-dimension al electr on g as be ing forme d th e rebet ween, a multi -layer structu re that includes a firs t n itri de-ba s ed passi vat ion layer dispo sed d i rectly on the secon d a ctiv e sem icondu ctor layer, an d a n o xy- nitri de layer dispo sed d i rect ly on the f irst nitr de-ba s ed pa ssi vati on layer, the f irst nitrdeb ased p ass ivation layer hav in g a f i rst th ickn ess a n d the o xy- ni tride l ayer hav ing a sec ond thickness, the oxy-nitrde layer comprsing a g ate d i elect ric o f the nitride- based HFET dev i ce, a nd spaced-apart s ource an d dra in ohmic contacts directly on, or in re ce sses t hat exten d thr oug h t h e sec on d act iv e se miconducto r layer. 25 The nitr de-based HF ET dev ic e of cla im 24 w here in the first nitri de-ba sed pass ivation l ayer compri se AIN 26 The nitri de-ba sed FE T dev ic e of cla im 24 w her ein the first nitride-based pass ivation layer c ompri se SiN 27 The nit ri de- bas ed FE T de vice of claim 24 wherei n t he firs t t hicknesis is in a ran g e of ab out 2 -10 nm thick. 28 The ni tride-based FE T de vice o f cla im 24 w here i n the oxy- nit n de layer comprise s AI ON. 036 92. B₁₅₅C -16- Application 29. The nitrde-based HFET device of a m 24 wherei n the second thicknes s i s in a range of about 10 -25 nm th ick ABSTRA CT O F THE DISCLOSURE A m eth od of fabricating a m ult -layer structu re f or a pow er tr ansistor device incl ude s per forming, withi n a rea ction chamber, a nitrogen pl asma st rk e, result ing in the f ormation of a nitride layer directly on a nitride-based active semiconductor layer A top surf ace o f the n itri de lay er i s the n exp os ed t o a second source A su bsequ ent nitrogen-oxygen plasm a st rik e res ul ts in the f ormation o f a n oxy-nitrde lay er directly o n the nitri de la yer The nitride layer compris es a p assivation lay er and the oxy- nitri de layer compri ses a g ate die lectric o f the p ow er tra nsistor device. 036 92. B₁₅₅C -18- Application SVG 14154355.01-14-2014.HQFF₄ZYVPXXIFW3.SPEC₁1165086.3.332.3048.2178.3091.svg 0.143 6.153 Drawing Black and white Claims What is claimed is:

Th e method of claim 34 wherein the fi rst thickness is in a range of about 2-10 nm thick.