Patent
US 10,978,581GUARD RINGS FOR CASCODE GALLIUM NITRIDE DEVICES
Woochul JEON
US
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Patent
Atlas literature
Patent
US 10,978,581Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a guard ring structure; [0027]
FIG. 2 is top view of another guard ring structure; [0028]
FIG. 3 is a top view of an implementation of a guard ring structure; [0029]
FIG. 4A is a top view of another implementation of a guard ring structure; [0030]
FIG. 5 A is a top view of another implementation of a guard ring structure; [0032]
FIG. 6 is a view an implementation of a guard ring protecting a device; [0034]
FIG. 7 is a top view of a cascode device using an implementation of a guard ring structure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a depletion mode (D-mode) transistor comprising one or more source fingers, one or more drain fingers and one or more gate[[s]] pads; an enhanced mode (E-mode) transistor comprising one or more source pads, one or more drain pads and one or more gate pads; and a guard ring; wherein the one or more gate pads of the D-mode transistor couple with the one or more source pads of the E-mode transistor, an electrical ground, and the guard ring. Currently amended
The semiconductor device of claim 1, wherein the D-mode transistor is a gallium nitride (GaN) high electron mobility transistor (HEMT). Original
The semiconductor device of claim 1, wherein the E-mode transistor is a silicon (Si) field effect transistor (F ET). Original
The semiconductor device of claim 1, further comprising a gate bus formed as [[a]] the guard ring. Currently amended
The semiconductor device of claim 1, wherein the D-mode transistor is coupled to a first conductive lead frame and the E-mode transistor is coupled to a second conductive lead frame. Original
The semiconductor device of claim 1, further comprising a pin out from each of the drain of the D-mode transistor and [[the]] _ a gate and [[the]] _ a source of the E-mode transistor. Currently amended
The semiconductor device of claim 1, wherein [[the]] _ a source of the D-mode transistor is coupled to [[the] a drain of the E-mode transistor. Currently amended
The semiconductor device of claim 1, wherein [[the]] _ a source of the D-mode transistor and [[the]] a drain of the E-mode transistor are coupled together through a wire bond. Currently amended
A semiconductor device comprising: a depletion mode (D-mode) transistor comprising one or more source fingers, one or more drain fingers and one or more gate[[s]] pads; an enhanced mode (E-mode) transistor comprising one or more source pads, one or more drain pads and one or more gate pads; and a guard ring; wherein the one or more gate pads of the D-mode transistor couple with the one or more source pads of the E-mode transistor, an electrical ground, and the guard ring St; and wherein the source is not grounded. Currently amended
The semiconductor device of claim 9, wherein the D-mode transistor is a gallium nitride (GaN) high electron mobility transistor (HEMT). Original
The semiconductor device of claim 9, wherein the E-mode transistor is a silicon (Si) field effect transistor (F ET). Original
The semiconductor device of claim 9, further comprising a gate bus formed as [[a]] the guard ring. Currently amended
The semiconductor device of claim 9, wherein the D-mode transistor is coupled to a first conductive lead frame and the E-mode transistor is coupled to a second conductive lead frame. Original
The semiconductor device of claim 9, further comprising a pin out from each of the drain of the D-mode transistor and [[the]] _ a gate and [[the]] a source of the E-mode transistor. Currently amended
The semiconductor device of claim 9, wherein [[the]] of a source of the D-mode transistor is coupled to [[the]] a drain of the E-mode transistor. Currently amended
1 6. The semiconductor device of claim 9, wherein [[the]] a source of the D-mode transistor and [[the]]a drain of the E-mode transistor are coupled together through a wire bond. Currently amended
A semiconductor device comprising: a depletion mode (D-mode) transistor comprising one or more source fingers, one or more drain fingers and one or more gate[[s]] pads; an enhanced mode (E-mode) transistor comprising one or more source pads, one or more drain pads and one or more gate pads; and a second guard ring surrounding an outer perimeter of [[the]] a first guard ring, the first guard ring coupled with the one or more gate pads of at least the D-mode transistor; wherein the one or more gate pads of the D-mode transistor couple with the one or more source pads of the E-mode transistor and an electrical ground. Currently amended
The semiconductor device of claim 17, further comprising a gate bus formed as [[a]] the first guard ring of the D-mode transistor. Currently amended
The semiconductor device of claim 17, wherein the D-mode transistor is coupled to a first conductive lead frame and the E-mode transistor is coupled to a second conductive lead frame. Original
. Canceled
Layer stacks claimed or described, ordered top of device to substrate.
cascode semiconductor device with D-mode and E-mode transistors and guard ring
GaN high electron mobility transistor (HEMT) as D-mode transistor
silicon field effect transistor (Si FET) as E-mode transistor
cascode semiconductor device with D-mode and E-mode transistors and dual guard rings
Materials described outside the worked examples.
gallium nitride
GaN
silicon
Si
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,978,581Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a guard ring structure; [0027]
FIG. 2 is top view of another guard ring structure; [0028]
FIG. 3 is a top view of an implementation of a guard ring structure; [0029]
FIG. 4A is a top view of another implementation of a guard ring structure; [0030]
FIG. 5 A is a top view of another implementation of a guard ring structure; [0032]
FIG. 6 is a view an implementation of a guard ring protecting a device; [0034]
FIG. 7 is a top view of a cascode device using an implementation of a guard ring structure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a depletion mode (D-mode) transistor comprising one or more source fingers, one or more drain fingers and one or more gate[[s]] pads; an enhanced mode (E-mode) transistor comprising one or more source pads, one or more drain pads and one or more gate pads; and a guard ring; wherein the one or more gate pads of the D-mode transistor couple with the one or more source pads of the E-mode transistor, an electrical ground, and the guard ring. Currently amended
The semiconductor device of claim 1, wherein the D-mode transistor is a gallium nitride (GaN) high electron mobility transistor (HEMT). Original
The semiconductor device of claim 1, wherein the E-mode transistor is a silicon (Si) field effect transistor (F ET). Original
The semiconductor device of claim 1, further comprising a gate bus formed as [[a]] the guard ring. Currently amended
The semiconductor device of claim 1, wherein the D-mode transistor is coupled to a first conductive lead frame and the E-mode transistor is coupled to a second conductive lead frame. Original
The semiconductor device of claim 1, further comprising a pin out from each of the drain of the D-mode transistor and [[the]] _ a gate and [[the]] _ a source of the E-mode transistor. Currently amended
The semiconductor device of claim 1, wherein [[the]] _ a source of the D-mode transistor is coupled to [[the] a drain of the E-mode transistor. Currently amended
The semiconductor device of claim 1, wherein [[the]] _ a source of the D-mode transistor and [[the]] a drain of the E-mode transistor are coupled together through a wire bond. Currently amended
A semiconductor device comprising: a depletion mode (D-mode) transistor comprising one or more source fingers, one or more drain fingers and one or more gate[[s]] pads; an enhanced mode (E-mode) transistor comprising one or more source pads, one or more drain pads and one or more gate pads; and a guard ring; wherein the one or more gate pads of the D-mode transistor couple with the one or more source pads of the E-mode transistor, an electrical ground, and the guard ring St; and wherein the source is not grounded. Currently amended
The semiconductor device of claim 9, wherein the D-mode transistor is a gallium nitride (GaN) high electron mobility transistor (HEMT). Original
The semiconductor device of claim 9, wherein the E-mode transistor is a silicon (Si) field effect transistor (F ET). Original
The semiconductor device of claim 9, further comprising a gate bus formed as [[a]] the guard ring. Currently amended
The semiconductor device of claim 9, wherein the D-mode transistor is coupled to a first conductive lead frame and the E-mode transistor is coupled to a second conductive lead frame. Original
The semiconductor device of claim 9, further comprising a pin out from each of the drain of the D-mode transistor and [[the]] _ a gate and [[the]] a source of the E-mode transistor. Currently amended
The semiconductor device of claim 9, wherein [[the]] of a source of the D-mode transistor is coupled to [[the]] a drain of the E-mode transistor. Currently amended
1 6. The semiconductor device of claim 9, wherein [[the]] a source of the D-mode transistor and [[the]]a drain of the E-mode transistor are coupled together through a wire bond. Currently amended
A semiconductor device comprising: a depletion mode (D-mode) transistor comprising one or more source fingers, one or more drain fingers and one or more gate[[s]] pads; an enhanced mode (E-mode) transistor comprising one or more source pads, one or more drain pads and one or more gate pads; and a second guard ring surrounding an outer perimeter of [[the]] a first guard ring, the first guard ring coupled with the one or more gate pads of at least the D-mode transistor; wherein the one or more gate pads of the D-mode transistor couple with the one or more source pads of the E-mode transistor and an electrical ground. Currently amended
The semiconductor device of claim 17, further comprising a gate bus formed as [[a]] the first guard ring of the D-mode transistor. Currently amended
The semiconductor device of claim 17, wherein the D-mode transistor is coupled to a first conductive lead frame and the E-mode transistor is coupled to a second conductive lead frame. Original
. Canceled
Layer stacks claimed or described, ordered top of device to substrate.
cascode semiconductor device with D-mode and E-mode transistors and guard ring
GaN high electron mobility transistor (HEMT) as D-mode transistor
silicon field effect transistor (Si FET) as E-mode transistor
cascode semiconductor device with D-mode and E-mode transistors and dual guard rings
Materials described outside the worked examples.
gallium nitride
GaN
silicon
Si
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,978,581Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a guard ring structure; [0027]
FIG. 2 is top view of another guard ring structure; [0028]
FIG. 3 is a top view of an implementation of a guard ring structure; [0029]
FIG. 4A is a top view of another implementation of a guard ring structure; [0030]
FIG. 5 A is a top view of another implementation of a guard ring structure; [0032]
FIG. 6 is a view an implementation of a guard ring protecting a device; [0034]
FIG. 7 is a top view of a cascode device using an implementation of a guard ring structure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a depletion mode (D-mode) transistor comprising one or more source fingers, one or more drain fingers and one or more gate[[s]] pads; an enhanced mode (E-mode) transistor comprising one or more source pads, one or more drain pads and one or more gate pads; and a guard ring; wherein the one or more gate pads of the D-mode transistor couple with the one or more source pads of the E-mode transistor, an electrical ground, and the guard ring. Currently amended
The semiconductor device of claim 1, wherein the D-mode transistor is a gallium nitride (GaN) high electron mobility transistor (HEMT). Original
The semiconductor device of claim 1, wherein the E-mode transistor is a silicon (Si) field effect transistor (F ET). Original
The semiconductor device of claim 1, further comprising a gate bus formed as [[a]] the guard ring. Currently amended
The semiconductor device of claim 1, wherein the D-mode transistor is coupled to a first conductive lead frame and the E-mode transistor is coupled to a second conductive lead frame. Original
The semiconductor device of claim 1, further comprising a pin out from each of the drain of the D-mode transistor and [[the]] _ a gate and [[the]] _ a source of the E-mode transistor. Currently amended
The semiconductor device of claim 1, wherein [[the]] _ a source of the D-mode transistor is coupled to [[the] a drain of the E-mode transistor. Currently amended
The semiconductor device of claim 1, wherein [[the]] _ a source of the D-mode transistor and [[the]] a drain of the E-mode transistor are coupled together through a wire bond. Currently amended
A semiconductor device comprising: a depletion mode (D-mode) transistor comprising one or more source fingers, one or more drain fingers and one or more gate[[s]] pads; an enhanced mode (E-mode) transistor comprising one or more source pads, one or more drain pads and one or more gate pads; and a guard ring; wherein the one or more gate pads of the D-mode transistor couple with the one or more source pads of the E-mode transistor, an electrical ground, and the guard ring St; and wherein the source is not grounded. Currently amended
The semiconductor device of claim 9, wherein the D-mode transistor is a gallium nitride (GaN) high electron mobility transistor (HEMT). Original
The semiconductor device of claim 9, wherein the E-mode transistor is a silicon (Si) field effect transistor (F ET). Original
The semiconductor device of claim 9, further comprising a gate bus formed as [[a]] the guard ring. Currently amended
The semiconductor device of claim 9, wherein the D-mode transistor is coupled to a first conductive lead frame and the E-mode transistor is coupled to a second conductive lead frame. Original
The semiconductor device of claim 9, further comprising a pin out from each of the drain of the D-mode transistor and [[the]] _ a gate and [[the]] a source of the E-mode transistor. Currently amended
The semiconductor device of claim 9, wherein [[the]] of a source of the D-mode transistor is coupled to [[the]] a drain of the E-mode transistor. Currently amended
1 6. The semiconductor device of claim 9, wherein [[the]] a source of the D-mode transistor and [[the]]a drain of the E-mode transistor are coupled together through a wire bond. Currently amended
A semiconductor device comprising: a depletion mode (D-mode) transistor comprising one or more source fingers, one or more drain fingers and one or more gate[[s]] pads; an enhanced mode (E-mode) transistor comprising one or more source pads, one or more drain pads and one or more gate pads; and a second guard ring surrounding an outer perimeter of [[the]] a first guard ring, the first guard ring coupled with the one or more gate pads of at least the D-mode transistor; wherein the one or more gate pads of the D-mode transistor couple with the one or more source pads of the E-mode transistor and an electrical ground. Currently amended
The semiconductor device of claim 17, further comprising a gate bus formed as [[a]] the first guard ring of the D-mode transistor. Currently amended
The semiconductor device of claim 17, wherein the D-mode transistor is coupled to a first conductive lead frame and the E-mode transistor is coupled to a second conductive lead frame. Original
. Canceled
Layer stacks claimed or described, ordered top of device to substrate.
cascode semiconductor device with D-mode and E-mode transistors and guard ring
GaN high electron mobility transistor (HEMT) as D-mode transistor
silicon field effect transistor (Si FET) as E-mode transistor
cascode semiconductor device with D-mode and E-mode transistors and dual guard rings
Materials described outside the worked examples.
gallium nitride
GaN
silicon
Si
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,978,581Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 is a cross-sectional view of a guard ring structure; [0027]
FIG. 2 is top view of another guard ring structure; [0028]
FIG. 3 is a top view of an implementation of a guard ring structure; [0029]
FIG. 4A is a top view of another implementation of a guard ring structure; [0030]
FIG. 5 A is a top view of another implementation of a guard ring structure; [0032]
FIG. 6 is a view an implementation of a guard ring protecting a device; [0034]
FIG. 7 is a top view of a cascode device using an implementation of a guard ring structure.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device comprising: a depletion mode (D-mode) transistor comprising one or more source fingers, one or more drain fingers and one or more gate[[s]] pads; an enhanced mode (E-mode) transistor comprising one or more source pads, one or more drain pads and one or more gate pads; and a guard ring; wherein the one or more gate pads of the D-mode transistor couple with the one or more source pads of the E-mode transistor, an electrical ground, and the guard ring. Currently amended
The semiconductor device of claim 1, wherein the D-mode transistor is a gallium nitride (GaN) high electron mobility transistor (HEMT). Original
The semiconductor device of claim 1, wherein the E-mode transistor is a silicon (Si) field effect transistor (F ET). Original
The semiconductor device of claim 1, further comprising a gate bus formed as [[a]] the guard ring. Currently amended
The semiconductor device of claim 1, wherein the D-mode transistor is coupled to a first conductive lead frame and the E-mode transistor is coupled to a second conductive lead frame. Original
The semiconductor device of claim 1, further comprising a pin out from each of the drain of the D-mode transistor and [[the]] _ a gate and [[the]] _ a source of the E-mode transistor. Currently amended
The semiconductor device of claim 1, wherein [[the]] _ a source of the D-mode transistor is coupled to [[the] a drain of the E-mode transistor. Currently amended
The semiconductor device of claim 1, wherein [[the]] _ a source of the D-mode transistor and [[the]] a drain of the E-mode transistor are coupled together through a wire bond. Currently amended
A semiconductor device comprising: a depletion mode (D-mode) transistor comprising one or more source fingers, one or more drain fingers and one or more gate[[s]] pads; an enhanced mode (E-mode) transistor comprising one or more source pads, one or more drain pads and one or more gate pads; and a guard ring; wherein the one or more gate pads of the D-mode transistor couple with the one or more source pads of the E-mode transistor, an electrical ground, and the guard ring St; and wherein the source is not grounded. Currently amended
The semiconductor device of claim 9, wherein the D-mode transistor is a gallium nitride (GaN) high electron mobility transistor (HEMT). Original
The semiconductor device of claim 9, wherein the E-mode transistor is a silicon (Si) field effect transistor (F ET). Original
The semiconductor device of claim 9, further comprising a gate bus formed as [[a]] the guard ring. Currently amended
The semiconductor device of claim 9, wherein the D-mode transistor is coupled to a first conductive lead frame and the E-mode transistor is coupled to a second conductive lead frame. Original
The semiconductor device of claim 9, further comprising a pin out from each of the drain of the D-mode transistor and [[the]] _ a gate and [[the]] a source of the E-mode transistor. Currently amended
The semiconductor device of claim 9, wherein [[the]] of a source of the D-mode transistor is coupled to [[the]] a drain of the E-mode transistor. Currently amended
1 6. The semiconductor device of claim 9, wherein [[the]] a source of the D-mode transistor and [[the]]a drain of the E-mode transistor are coupled together through a wire bond. Currently amended
A semiconductor device comprising: a depletion mode (D-mode) transistor comprising one or more source fingers, one or more drain fingers and one or more gate[[s]] pads; an enhanced mode (E-mode) transistor comprising one or more source pads, one or more drain pads and one or more gate pads; and a second guard ring surrounding an outer perimeter of [[the]] a first guard ring, the first guard ring coupled with the one or more gate pads of at least the D-mode transistor; wherein the one or more gate pads of the D-mode transistor couple with the one or more source pads of the E-mode transistor and an electrical ground. Currently amended
The semiconductor device of claim 17, further comprising a gate bus formed as [[a]] the first guard ring of the D-mode transistor. Currently amended
The semiconductor device of claim 17, wherein the D-mode transistor is coupled to a first conductive lead frame and the E-mode transistor is coupled to a second conductive lead frame. Original
. Canceled
Layer stacks claimed or described, ordered top of device to substrate.
cascode semiconductor device with D-mode and E-mode transistors and guard ring
GaN high electron mobility transistor (HEMT) as D-mode transistor
silicon field effect transistor (Si FET) as E-mode transistor
cascode semiconductor device with D-mode and E-mode transistors and dual guard rings
Materials described outside the worked examples.
gallium nitride
GaN
silicon
Si
Related documents with shared materials, methods, properties, or citations.
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