Patent
US 11,107,755Packaging for Lateral High Voltage GaN Power Devices
Zhanming Li
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,107,755Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A packaged semiconductor device, comprising: a lateral semiconductor power device chip comprising an upper surface having at least two electrodes disposed thereon, and a lower surface, wherein the upper and lower surfaces are coplanar; at least one metal lead electrically connected to a first electrode of the at least two electrodes; a back-plate; an electrically insulating and thermally conducting adhesive disposed between the lower surface of the lateral semiconductor power device chip and the back-plate; wherein the back-plate comprises at least a metal portion that is electrically connected to a second electrode of the at least two electrodes.
The packaged semiconductor device of claim 1, wherein: the back-plate comprises only the metal portion and underlies the lateral semiconductor power device chip; and the electrically insulating and thermally conducting adhesive is disposed between the lateral semiconductor power device chip and the back-plate.
The packaged semiconductor device of claim 1, wherein: the back-plate comprises the metal portion and an electrically insulating and thermally conducting portion disposed adjacent the metal portion; wherein the lateral semiconductor power device chip is disposed over the electrically insulating and thermally conducting portion of the back-plate; wherein the electrically insulating and thermally conducting adhesive is disposed between the lateral semiconductor power device chip and the electrically insulating and thermally conducting portion of the back-plate.
The packaged semiconductor device of claim 1, wherein: respective electrical connections between the at least first and second electrodes and at least one metal lead and the metal portion of the back-plate are established by bond wires.
The packaged semiconductor device of claim 1, wherein: the lateral semiconductor power device chip is a field-effect transistor (FET); wherein the first electrode is a gate electrode and is electrically connected to a first metal lead; wherein the second electrode is a source electrode and is electrically connected to the metal portion of the back-plate; wherein a third electrode is a drain electrode and is electrically connected to a second metal lead.
The packaged semiconductor device of claim 1, wherein: the lateral semiconductor power device chip is a FET; wherein the first electrode is a gate electrode and is electrically connected to a first metal lead; wherein the second electrode is a drain electrode and is electrically connected to the metal portion of the back-plate; wherein a third electrode is a source electrode and is electrically connected to a second metal lead.
The packaged semiconductor device of claim 1, wherein: the lateral semiconductor power device chip comprises a GaN, GaN/GaN, GaN/Si, or GaN/ceramic technology.
The packaged semiconductor device of claim 1, wherein: the package conforms with a JEDEC standard format.
A method for packaging a lateral semiconductor power device chip comprising an upper surface having at least two electrodes disposed thereon, and a lower surface, wherein the upper and lower surfaces are coplanar, the method comprising: electrically connecting a first electrode of the at least two electrodes to a first metal lead of a device package; disposing an electrically insulating and thermally conducting adhesive between the lower surface of the lateral semiconductor power device chip and a back-plate of the device package; wherein the back-plate comprises at least a metal portion that is electrically connected to a second electrode of the at least two electrodes.
The method of claim 12, wherein: the back-plate comprises only the metal portion and underlies the lateral semiconductor power device chip; and the electrically insulating and thermally conducting adhesive is disposed between the lateral semiconductor power device chip and the back-plate.
The method of claim 12, wherein: the back-plate comprises the metal portion and an electrically insulating and thermally conducting portion disposed on the metal portion; wherein the lateral semiconductor power device chip is disposed over the electrically insulating and thermally conducting portion of the back-plate; wherein the electrically insulating and thermally conducting adhesive is disposed between the lateral semiconductor power device chip and the electrically insulating and thermally conducting portion of the back-plate.
The method of claim 12, wherein: the back-plate comprises the metal portion and an electrically insulating and thermally conducting portion disposed adjacent the metal portion; wherein the lateral semiconductor power device chip is disposed over the electrically insulating and thermally conducting portion of the back-plate; wherein the electrically insulating and thermally conducting adhesive is disposed between the lateral semiconductor power device chip and the electrically insulating and thermally conducting portion of the back-plate.
The method of claim 12, wherein: respective electrical connections between the at least first and second electrodes and at least one metal lead and the metal portion of the back-plate are established by bond wires.
The method of claim 12, wherein: the lateral semiconductor power device chip is a field-effect transistor (FET); wherein the first electrode is a gate electrode and is electrically connected to the first metal lead; wherein the second electrode is a source electrode and is electrically connected to the metal portion of the back-plate; wherein a third electrode is a drain electrode and is electrically connected to a second metal lead of the package.
The method of claim 12, wherein: the lateral semiconductor power device chip is a FET; wherein the first electrode is a gate electrode and is electrically connected to the first metal lead; wherein the second electrode is a drain electrode and is electrically connected to the metal portion of the back-plate; wherein a third electrode is a source electrode and is electrically connected to a second metal lead of the package.
The method of claim 12, wherein: the lateral semiconductor power device chip comprises a GaN, GaN/GaN, GaN/Si, or GaN/ceramic technology.
The method of claim 12, wherein: the package conforms with a JEDEC standard format.
Layer stacks claimed or described, ordered top of device to substrate.
packaged lateral semiconductor power device (metal back-plate only)
packaged lateral semiconductor power device (insulating layer on metal back-plate)
Materials described outside the worked examples.
electrically insulating and thermally conducting adhesive
metal back-plate
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,107,755Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A packaged semiconductor device, comprising: a lateral semiconductor power device chip comprising an upper surface having at least two electrodes disposed thereon, and a lower surface, wherein the upper and lower surfaces are coplanar; at least one metal lead electrically connected to a first electrode of the at least two electrodes; a back-plate; an electrically insulating and thermally conducting adhesive disposed between the lower surface of the lateral semiconductor power device chip and the back-plate; wherein the back-plate comprises at least a metal portion that is electrically connected to a second electrode of the at least two electrodes.
The packaged semiconductor device of claim 1, wherein: the back-plate comprises only the metal portion and underlies the lateral semiconductor power device chip; and the electrically insulating and thermally conducting adhesive is disposed between the lateral semiconductor power device chip and the back-plate.
The packaged semiconductor device of claim 1, wherein: the back-plate comprises the metal portion and an electrically insulating and thermally conducting portion disposed adjacent the metal portion; wherein the lateral semiconductor power device chip is disposed over the electrically insulating and thermally conducting portion of the back-plate; wherein the electrically insulating and thermally conducting adhesive is disposed between the lateral semiconductor power device chip and the electrically insulating and thermally conducting portion of the back-plate.
The packaged semiconductor device of claim 1, wherein: respective electrical connections between the at least first and second electrodes and at least one metal lead and the metal portion of the back-plate are established by bond wires.
The packaged semiconductor device of claim 1, wherein: the lateral semiconductor power device chip is a field-effect transistor (FET); wherein the first electrode is a gate electrode and is electrically connected to a first metal lead; wherein the second electrode is a source electrode and is electrically connected to the metal portion of the back-plate; wherein a third electrode is a drain electrode and is electrically connected to a second metal lead.
The packaged semiconductor device of claim 1, wherein: the lateral semiconductor power device chip is a FET; wherein the first electrode is a gate electrode and is electrically connected to a first metal lead; wherein the second electrode is a drain electrode and is electrically connected to the metal portion of the back-plate; wherein a third electrode is a source electrode and is electrically connected to a second metal lead.
The packaged semiconductor device of claim 1, wherein: the lateral semiconductor power device chip comprises a GaN, GaN/GaN, GaN/Si, or GaN/ceramic technology.
The packaged semiconductor device of claim 1, wherein: the package conforms with a JEDEC standard format.
A method for packaging a lateral semiconductor power device chip comprising an upper surface having at least two electrodes disposed thereon, and a lower surface, wherein the upper and lower surfaces are coplanar, the method comprising: electrically connecting a first electrode of the at least two electrodes to a first metal lead of a device package; disposing an electrically insulating and thermally conducting adhesive between the lower surface of the lateral semiconductor power device chip and a back-plate of the device package; wherein the back-plate comprises at least a metal portion that is electrically connected to a second electrode of the at least two electrodes.
The method of claim 12, wherein: the back-plate comprises only the metal portion and underlies the lateral semiconductor power device chip; and the electrically insulating and thermally conducting adhesive is disposed between the lateral semiconductor power device chip and the back-plate.
The method of claim 12, wherein: the back-plate comprises the metal portion and an electrically insulating and thermally conducting portion disposed on the metal portion; wherein the lateral semiconductor power device chip is disposed over the electrically insulating and thermally conducting portion of the back-plate; wherein the electrically insulating and thermally conducting adhesive is disposed between the lateral semiconductor power device chip and the electrically insulating and thermally conducting portion of the back-plate.
The method of claim 12, wherein: the back-plate comprises the metal portion and an electrically insulating and thermally conducting portion disposed adjacent the metal portion; wherein the lateral semiconductor power device chip is disposed over the electrically insulating and thermally conducting portion of the back-plate; wherein the electrically insulating and thermally conducting adhesive is disposed between the lateral semiconductor power device chip and the electrically insulating and thermally conducting portion of the back-plate.
The method of claim 12, wherein: respective electrical connections between the at least first and second electrodes and at least one metal lead and the metal portion of the back-plate are established by bond wires.
The method of claim 12, wherein: the lateral semiconductor power device chip is a field-effect transistor (FET); wherein the first electrode is a gate electrode and is electrically connected to the first metal lead; wherein the second electrode is a source electrode and is electrically connected to the metal portion of the back-plate; wherein a third electrode is a drain electrode and is electrically connected to a second metal lead of the package.
The method of claim 12, wherein: the lateral semiconductor power device chip is a FET; wherein the first electrode is a gate electrode and is electrically connected to the first metal lead; wherein the second electrode is a drain electrode and is electrically connected to the metal portion of the back-plate; wherein a third electrode is a source electrode and is electrically connected to a second metal lead of the package.
The method of claim 12, wherein: the lateral semiconductor power device chip comprises a GaN, GaN/GaN, GaN/Si, or GaN/ceramic technology.
The method of claim 12, wherein: the package conforms with a JEDEC standard format.
Layer stacks claimed or described, ordered top of device to substrate.
packaged lateral semiconductor power device (metal back-plate only)
packaged lateral semiconductor power device (insulating layer on metal back-plate)
Materials described outside the worked examples.
electrically insulating and thermally conducting adhesive
metal back-plate
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,107,755Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A packaged semiconductor device, comprising: a lateral semiconductor power device chip comprising an upper surface having at least two electrodes disposed thereon, and a lower surface, wherein the upper and lower surfaces are coplanar; at least one metal lead electrically connected to a first electrode of the at least two electrodes; a back-plate; an electrically insulating and thermally conducting adhesive disposed between the lower surface of the lateral semiconductor power device chip and the back-plate; wherein the back-plate comprises at least a metal portion that is electrically connected to a second electrode of the at least two electrodes.
The packaged semiconductor device of claim 1, wherein: the back-plate comprises only the metal portion and underlies the lateral semiconductor power device chip; and the electrically insulating and thermally conducting adhesive is disposed between the lateral semiconductor power device chip and the back-plate.
The packaged semiconductor device of claim 1, wherein: the back-plate comprises the metal portion and an electrically insulating and thermally conducting portion disposed adjacent the metal portion; wherein the lateral semiconductor power device chip is disposed over the electrically insulating and thermally conducting portion of the back-plate; wherein the electrically insulating and thermally conducting adhesive is disposed between the lateral semiconductor power device chip and the electrically insulating and thermally conducting portion of the back-plate.
The packaged semiconductor device of claim 1, wherein: respective electrical connections between the at least first and second electrodes and at least one metal lead and the metal portion of the back-plate are established by bond wires.
The packaged semiconductor device of claim 1, wherein: the lateral semiconductor power device chip is a field-effect transistor (FET); wherein the first electrode is a gate electrode and is electrically connected to a first metal lead; wherein the second electrode is a source electrode and is electrically connected to the metal portion of the back-plate; wherein a third electrode is a drain electrode and is electrically connected to a second metal lead.
The packaged semiconductor device of claim 1, wherein: the lateral semiconductor power device chip is a FET; wherein the first electrode is a gate electrode and is electrically connected to a first metal lead; wherein the second electrode is a drain electrode and is electrically connected to the metal portion of the back-plate; wherein a third electrode is a source electrode and is electrically connected to a second metal lead.
The packaged semiconductor device of claim 1, wherein: the lateral semiconductor power device chip comprises a GaN, GaN/GaN, GaN/Si, or GaN/ceramic technology.
The packaged semiconductor device of claim 1, wherein: the package conforms with a JEDEC standard format.
A method for packaging a lateral semiconductor power device chip comprising an upper surface having at least two electrodes disposed thereon, and a lower surface, wherein the upper and lower surfaces are coplanar, the method comprising: electrically connecting a first electrode of the at least two electrodes to a first metal lead of a device package; disposing an electrically insulating and thermally conducting adhesive between the lower surface of the lateral semiconductor power device chip and a back-plate of the device package; wherein the back-plate comprises at least a metal portion that is electrically connected to a second electrode of the at least two electrodes.
The method of claim 12, wherein: the back-plate comprises only the metal portion and underlies the lateral semiconductor power device chip; and the electrically insulating and thermally conducting adhesive is disposed between the lateral semiconductor power device chip and the back-plate.
The method of claim 12, wherein: the back-plate comprises the metal portion and an electrically insulating and thermally conducting portion disposed on the metal portion; wherein the lateral semiconductor power device chip is disposed over the electrically insulating and thermally conducting portion of the back-plate; wherein the electrically insulating and thermally conducting adhesive is disposed between the lateral semiconductor power device chip and the electrically insulating and thermally conducting portion of the back-plate.
The method of claim 12, wherein: the back-plate comprises the metal portion and an electrically insulating and thermally conducting portion disposed adjacent the metal portion; wherein the lateral semiconductor power device chip is disposed over the electrically insulating and thermally conducting portion of the back-plate; wherein the electrically insulating and thermally conducting adhesive is disposed between the lateral semiconductor power device chip and the electrically insulating and thermally conducting portion of the back-plate.
The method of claim 12, wherein: respective electrical connections between the at least first and second electrodes and at least one metal lead and the metal portion of the back-plate are established by bond wires.
The method of claim 12, wherein: the lateral semiconductor power device chip is a field-effect transistor (FET); wherein the first electrode is a gate electrode and is electrically connected to the first metal lead; wherein the second electrode is a source electrode and is electrically connected to the metal portion of the back-plate; wherein a third electrode is a drain electrode and is electrically connected to a second metal lead of the package.
The method of claim 12, wherein: the lateral semiconductor power device chip is a FET; wherein the first electrode is a gate electrode and is electrically connected to the first metal lead; wherein the second electrode is a drain electrode and is electrically connected to the metal portion of the back-plate; wherein a third electrode is a source electrode and is electrically connected to a second metal lead of the package.
The method of claim 12, wherein: the lateral semiconductor power device chip comprises a GaN, GaN/GaN, GaN/Si, or GaN/ceramic technology.
The method of claim 12, wherein: the package conforms with a JEDEC standard format.
Layer stacks claimed or described, ordered top of device to substrate.
packaged lateral semiconductor power device (metal back-plate only)
packaged lateral semiconductor power device (insulating layer on metal back-plate)
Materials described outside the worked examples.
electrically insulating and thermally conducting adhesive
metal back-plate
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,107,755Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A packaged semiconductor device, comprising: a lateral semiconductor power device chip comprising an upper surface having at least two electrodes disposed thereon, and a lower surface, wherein the upper and lower surfaces are coplanar; at least one metal lead electrically connected to a first electrode of the at least two electrodes; a back-plate; an electrically insulating and thermally conducting adhesive disposed between the lower surface of the lateral semiconductor power device chip and the back-plate; wherein the back-plate comprises at least a metal portion that is electrically connected to a second electrode of the at least two electrodes.
The packaged semiconductor device of claim 1, wherein: the back-plate comprises only the metal portion and underlies the lateral semiconductor power device chip; and the electrically insulating and thermally conducting adhesive is disposed between the lateral semiconductor power device chip and the back-plate.
The packaged semiconductor device of claim 1, wherein: the back-plate comprises the metal portion and an electrically insulating and thermally conducting portion disposed adjacent the metal portion; wherein the lateral semiconductor power device chip is disposed over the electrically insulating and thermally conducting portion of the back-plate; wherein the electrically insulating and thermally conducting adhesive is disposed between the lateral semiconductor power device chip and the electrically insulating and thermally conducting portion of the back-plate.
The packaged semiconductor device of claim 1, wherein: respective electrical connections between the at least first and second electrodes and at least one metal lead and the metal portion of the back-plate are established by bond wires.
The packaged semiconductor device of claim 1, wherein: the lateral semiconductor power device chip is a field-effect transistor (FET); wherein the first electrode is a gate electrode and is electrically connected to a first metal lead; wherein the second electrode is a source electrode and is electrically connected to the metal portion of the back-plate; wherein a third electrode is a drain electrode and is electrically connected to a second metal lead.
The packaged semiconductor device of claim 1, wherein: the lateral semiconductor power device chip is a FET; wherein the first electrode is a gate electrode and is electrically connected to a first metal lead; wherein the second electrode is a drain electrode and is electrically connected to the metal portion of the back-plate; wherein a third electrode is a source electrode and is electrically connected to a second metal lead.
The packaged semiconductor device of claim 1, wherein: the lateral semiconductor power device chip comprises a GaN, GaN/GaN, GaN/Si, or GaN/ceramic technology.
The packaged semiconductor device of claim 1, wherein: the package conforms with a JEDEC standard format.
A method for packaging a lateral semiconductor power device chip comprising an upper surface having at least two electrodes disposed thereon, and a lower surface, wherein the upper and lower surfaces are coplanar, the method comprising: electrically connecting a first electrode of the at least two electrodes to a first metal lead of a device package; disposing an electrically insulating and thermally conducting adhesive between the lower surface of the lateral semiconductor power device chip and a back-plate of the device package; wherein the back-plate comprises at least a metal portion that is electrically connected to a second electrode of the at least two electrodes.
The method of claim 12, wherein: the back-plate comprises only the metal portion and underlies the lateral semiconductor power device chip; and the electrically insulating and thermally conducting adhesive is disposed between the lateral semiconductor power device chip and the back-plate.
The method of claim 12, wherein: the back-plate comprises the metal portion and an electrically insulating and thermally conducting portion disposed on the metal portion; wherein the lateral semiconductor power device chip is disposed over the electrically insulating and thermally conducting portion of the back-plate; wherein the electrically insulating and thermally conducting adhesive is disposed between the lateral semiconductor power device chip and the electrically insulating and thermally conducting portion of the back-plate.
The method of claim 12, wherein: the back-plate comprises the metal portion and an electrically insulating and thermally conducting portion disposed adjacent the metal portion; wherein the lateral semiconductor power device chip is disposed over the electrically insulating and thermally conducting portion of the back-plate; wherein the electrically insulating and thermally conducting adhesive is disposed between the lateral semiconductor power device chip and the electrically insulating and thermally conducting portion of the back-plate.
The method of claim 12, wherein: respective electrical connections between the at least first and second electrodes and at least one metal lead and the metal portion of the back-plate are established by bond wires.
The method of claim 12, wherein: the lateral semiconductor power device chip is a field-effect transistor (FET); wherein the first electrode is a gate electrode and is electrically connected to the first metal lead; wherein the second electrode is a source electrode and is electrically connected to the metal portion of the back-plate; wherein a third electrode is a drain electrode and is electrically connected to a second metal lead of the package.
The method of claim 12, wherein: the lateral semiconductor power device chip is a FET; wherein the first electrode is a gate electrode and is electrically connected to the first metal lead; wherein the second electrode is a drain electrode and is electrically connected to the metal portion of the back-plate; wherein a third electrode is a source electrode and is electrically connected to a second metal lead of the package.
The method of claim 12, wherein: the lateral semiconductor power device chip comprises a GaN, GaN/GaN, GaN/Si, or GaN/ceramic technology.
The method of claim 12, wherein: the package conforms with a JEDEC standard format.
Layer stacks claimed or described, ordered top of device to substrate.
packaged lateral semiconductor power device (metal back-plate only)
packaged lateral semiconductor power device (insulating layer on metal back-plate)
Materials described outside the worked examples.
electrically insulating and thermally conducting adhesive
metal back-plate
Related documents with shared materials, methods, properties, or citations.
packaged lateral semiconductor power device (insulating portion adjacent metal portion in back-plate)
lateral FET packaged device (source connected to back-plate)
lateral FET packaged device (drain connected to back-plate)
electrically insulating and thermally conducting portion of back-plate
GaN
GaN/GaN
GaN/Si
GaN/ceramic
GALLIUM NITRIDE TRANSISTORS WITH SOURCE AND DRAIN FIELD PLATES AND THEIR METHODS OF FABRICATION
REDUCED PUNCHTHROUGH BREAKDOWN IN GALLIUM-NITRIDE TRANSISTORS
packaged lateral semiconductor power device (insulating portion adjacent metal portion in back-plate)
lateral FET packaged device (source connected to back-plate)
lateral FET packaged device (drain connected to back-plate)
electrically insulating and thermally conducting portion of back-plate
GaN
GaN/GaN
GaN/Si
GaN/ceramic
GALLIUM NITRIDE TRANSISTORS WITH SOURCE AND DRAIN FIELD PLATES AND THEIR METHODS OF FABRICATION
REDUCED PUNCHTHROUGH BREAKDOWN IN GALLIUM-NITRIDE TRANSISTORS
packaged lateral semiconductor power device (insulating portion adjacent metal portion in back-plate)
lateral FET packaged device (source connected to back-plate)
lateral FET packaged device (drain connected to back-plate)
electrically insulating and thermally conducting portion of back-plate
GaN
GaN/GaN
GaN/Si
GaN/ceramic
GALLIUM NITRIDE TRANSISTORS WITH SOURCE AND DRAIN FIELD PLATES AND THEIR METHODS OF FABRICATION
REDUCED PUNCHTHROUGH BREAKDOWN IN GALLIUM-NITRIDE TRANSISTORS
packaged lateral semiconductor power device (insulating portion adjacent metal portion in back-plate)
lateral FET packaged device (source connected to back-plate)
lateral FET packaged device (drain connected to back-plate)
electrically insulating and thermally conducting portion of back-plate
GaN
GaN/GaN
GaN/Si
GaN/ceramic
GALLIUM NITRIDE TRANSISTORS WITH SOURCE AND DRAIN FIELD PLATES AND THEIR METHODS OF FABRICATION