A power converter, comprising: a first power terminal and a second power terminal; a first upper series-stacked high electron mobility transistor (HEMT) module connected to the first power te rm inal and a first intermediate terminal; a first lower se ries-stacked H EMT module connected to the second power terminal and the first intermediate terminal; a first inductor connected to the first intermediate terminal and a third power terminal; and a fourth power terminal connected to the second power terminal-a fifth power terminal and a sixth power terminal: a sec ond uppe r series-stacked H EM T module connected to the fi ft h power terminal and a second intermediate terminal: a second lower series-stacked HEMT module connected to the sixth power terminal and the second intermediate termi nal; a second inductor connec ted to the second inte rm ediate terminal and a seventh power terminal: and an ei g hth power te r minal connected to the sixth power terminal, each of the first upper series-stacked HEM "T module and the first lower series-stacked HEMT module comprising a fir st plurality of HEMTs and a first series-switch-driver connected to each gate of the f irst plurality of HEMTs, and each of the second upper series-stacked II EMT module and the second lower series-stacked HEMT module comprising a se cond plurality of HEMTs and a second series-switch-driver connected to each gate o f the second plurality of H EMTs. Currently amended

Canceled

, A power con verter, comprising: a first pow er terminal and a second power terminal; a first upper series-stacked high electron mobility transistor (I- EMT) module connected to the first power terminal and a first intermediate terminal; a first lowe r series-stacked HEM T module connected to the second power terminal and the first intermediate terminal; a first inductor connected to the first inte rm ediate terminal and a third power terminal; and a fourth p ower terminal connected to the second power terminal, each of the first uppe r series-stacked HEM T module and the first lower series-sta cked H EMT module com prising a first plurality of HEMTs and a f irs t series-switch-driver connected to each gate of th e first plurality of HEMTs, each of the fi rst upper series-stacked HEMT module and the first lower series-stacked H EMT module co m prising: a first HEM T; a second H E MT, a first drain of the first HE MT being connected to a second source of the second HEMT; a first gate input terminal coupled to a first gate of the fi rst HEMT; a second gate input te rm inal coupled to a second gate o f the second H EMT; a first driver connected between the first gate input terminal and a first gate intermediate terminal; a first FB connected between the first gate intermediate terminal and the first gate of the f irst HE MT; a second driver connected between the second gate input terminal and a second gate intermediate terminal; a first gate capacitor connected between the first gate input terminal and the second gate input terminal; and a second gate capacitor connected between the second gate intermediate terminal and a second drain of the second HEMT, and the second driver comprising a second FB connected between the second gate input terminal and a second gate inte rm ediate terminal. Currently amended

A power converter, comprising: a first power te r m inal and a second power terminal; SVG 15979892.11-08-2018.JO₈YY₃K₈RXEAPX0.CLM.1.svg 0.16 6.01 Black and white fi rst power terminal and a first intermediate terminal; a first lower series-stacked HEMT module connected to the second power terminal and the fi rst inte nn ediate terminal: a first inductor co nnected to the first inter mediate te rminal and a third power terminal; and a fourth power terminal connected to the second power terminal, each o f the first upper series-stacked HEMT module and the first lower series-stacked HE M T module comprising a first plurality of HEMTs and a first series-switch-driver connected to each g ate of the first plurality of H E MT s. and each of the first upper series-stacked HEMT module and the first lower series-stacked HEMT module comprising: first to nth HEMTs being connected in series to each other; first to nth gate input terminals coupled to first to nth gates of first to nth gate HEM I s through first to nth gate intermediate terminal, respectively; first to nth drivers connected between the first to nth gate input te nm inals and the first to nth gate intermediate terminal; a first gate capacitor connected between the first gate input terminal and the second gate input terminal; a kth gate capacitor connected between a (k +1)th gate input terminal and a kth source, k being from 2 to (n- 1); a nth gate capacitor connected between a n t h gate intermediate terminal and a nth drain. Currently amended

Canceled

A power converter, comprising: a first power terminal and a second power terminal; a first upper series-stacked high electron mobility transistor (HEMT) module connected to the first power terminal and a first intermediate terminal; a first lower series-stacked HEMT module connected to the second power ter m inal and the first intermediate terminal; a first inductor connected to the first intermediate terminal and a third power terminal; a fourth power terminal connected to the second power terminal; a fifth power terminal and a sixth power ter m inal; a second upper series-stacked IlEM T module connected to the fifth power te rm inal and a second intermediate terminal; a second lower series-stacked HEMT module connected to the sixth power terminal and the second intermediate terminal; a second inductor connected to the second intermediate terminal and a seventh power terminal; and an eighth power terminal connected to the sixth power terminal, each of the first upper series-stacked HEMT module and the first lower series-stacked H EMT module comprising a first plurality of HEMTs and a fi rst series-switch-driver connected to each gate of the first plurality of HEM Ts, each of the second upper series-stacked HEMT module and the second lower series-stacked SVG 15979892.11-08-2018.JO₈YY₃K₈RXEAPX0.CLM.2.svg 0.16 6.51 Black and white connected to each gate of the second plurality of HEMTs. each of the first upper series-stacked HEM T module, the first lower series-stacked I IEMT module, the second upper series-stacked HEMT module, and the second lower series-stacked H EMT module comprising: a first HEMT; a second H EMT, a first drain of the first HEMT being connected to a second source of the second HEMT; a first gate input terminal coupled to a first gate of the first H E MT; a second gate input terminal coupled to a second gate of the second H EMT; a first driver connected between the first gate input terminal and a first gate intermediate terminal; a first FB connected between the first gate intermediate terminal and the first gate of the first HEMT; a second driver connected between the second gate input terminal and a second gate intermediate terminal; a first gate capacitor connected between the first gate input terminal and the second gate input terminal; and a second gate capacitor connected between the second gate intermediate terminal and a second drain of the second HEMT, and the second driver comprising a second FB connected between the second gate input terminal and a second gate intermediate terminal. Original

A power converter, comprising: a first power terminal and a second power terminal; a first upper series-stacked high electron mobility transistor (HEMT) module connected to the first power te rm inal and a first intermediate terminal; a first lower se ries-stacked H EMT module connected to the second power terminal and the first intermediate terminal; a first inductor connected to the first intermediate terminal and a third power terminal; and a fourth power terminal connected to the second power terminal-a fifth power terminal and a sixth power terminal: a sec ond uppe r series-stacked H EM T module connected to the fi ft h power terminal and a second intermediate terminal: a second lower series-stacked HEMT module connected to the sixth power terminal and the second intermediate termi nal; a second inductor connec ted to the second inte rm ediate terminal and a seventh power terminal: and an ei g hth power te r minal connected to the sixth power terminal, each of the first upper series-stacked HEM "T module and the first lower series-stacked HEMT module comprising a fir st plurality of HEMTs and a first series-switch-driver connected to each gate of the f irst plurality of HEMTs, and each of the second upper series-stacked II EMT module and the second lower series-stacked HEMT module comprising a se cond plurality of HEMTs and a second series-switch-driver connected to each gate o f the second plurality of H EMTs. Currently amended

Canceled

, A power con verter, comprising: a first pow er terminal and a second power terminal; a first upper series-stacked high electron mobility transistor (I- EMT) module connected to the first power terminal and a first intermediate terminal; a first lowe r series-stacked HEM T module connected to the second power terminal and the first intermediate terminal; a first inductor connected to the first inte rm ediate terminal and a third power terminal; and a fourth p ower terminal connected to the second power terminal, each of the first uppe r series-stacked HEM T module and the first lower series-sta cked H EMT module com prising a first plurality of HEMTs and a f irs t series-switch-driver connected to each gate of th e first plurality of HEMTs, each of the fi rst upper series-stacked HEMT module and the first lower series-stacked H EMT module co m prising: a first HEM T; a second H E MT, a first drain of the first HE MT being connected to a second source of the second HEMT; a first gate input terminal coupled to a first gate of the fi rst HEMT; a second gate input te rm inal coupled to a second gate o f the second H EMT; a first driver connected between the first gate input terminal and a first gate intermediate terminal; a first FB connected between the first gate intermediate terminal and the first gate of the f irst HE MT; a second driver connected between the second gate input terminal and a second gate intermediate terminal; a first gate capacitor connected between the first gate input terminal and the second gate input terminal; and a second gate capacitor connected between the second gate intermediate terminal and a second drain of the second HEMT, and the second driver comprising a second FB connected between the second gate input terminal and a second gate inte rm ediate terminal. Currently amended

A power converter, comprising: a first power te r m inal and a second power terminal; SVG 15979892.11-08-2018.JO₈YY₃K₈RXEAPX0.CLM.1.svg 0.16 6.01 Black and white fi rst power terminal and a first intermediate terminal; a first lower series-stacked HEMT module connected to the second power terminal and the fi rst inte nn ediate terminal: a first inductor co nnected to the first inter mediate te rminal and a third power terminal; and a fourth power terminal connected to the second power terminal, each o f the first upper series-stacked HEMT module and the first lower series-stacked HE M T module comprising a first plurality of HEMTs and a first series-switch-driver connected to each g ate of the first plurality of H E MT s. and each of the first upper series-stacked HEMT module and the first lower series-stacked HEMT module comprising: first to nth HEMTs being connected in series to each other; first to nth gate input terminals coupled to first to nth gates of first to nth gate HEM I s through first to nth gate intermediate terminal, respectively; first to nth drivers connected between the first to nth gate input te nm inals and the first to nth gate intermediate terminal; a first gate capacitor connected between the first gate input terminal and the second gate input terminal; a kth gate capacitor connected between a (k +1)th gate input terminal and a kth source, k being from 2 to (n- 1); a nth gate capacitor connected between a n t h gate intermediate terminal and a nth drain. Currently amended

Canceled

A power converter, comprising: a first power terminal and a second power terminal; a first upper series-stacked high electron mobility transistor (HEMT) module connected to the first power terminal and a first intermediate terminal; a first lower series-stacked HEMT module connected to the second power ter m inal and the first intermediate terminal; a first inductor connected to the first intermediate terminal and a third power terminal; a fourth power terminal connected to the second power terminal; a fifth power terminal and a sixth power ter m inal; a second upper series-stacked IlEM T module connected to the fifth power te rm inal and a second intermediate terminal; a second lower series-stacked HEMT module connected to the sixth power terminal and the second intermediate terminal; a second inductor connected to the second intermediate terminal and a seventh power terminal; and an eighth power terminal connected to the sixth power terminal, each of the first upper series-stacked HEMT module and the first lower series-stacked H EMT module comprising a first plurality of HEMTs and a fi rst series-switch-driver connected to each gate of the first plurality of HEM Ts, each of the second upper series-stacked HEMT module and the second lower series-stacked SVG 15979892.11-08-2018.JO₈YY₃K₈RXEAPX0.CLM.2.svg 0.16 6.51 Black and white connected to each gate of the second plurality of HEMTs. each of the first upper series-stacked HEM T module, the first lower series-stacked I IEMT module, the second upper series-stacked HEMT module, and the second lower series-stacked H EMT module comprising: a first HEMT; a second H EMT, a first drain of the first HEMT being connected to a second source of the second HEMT; a first gate input terminal coupled to a first gate of the first H E MT; a second gate input terminal coupled to a second gate of the second H EMT; a first driver connected between the first gate input terminal and a first gate intermediate terminal; a first FB connected between the first gate intermediate terminal and the first gate of the first HEMT; a second driver connected between the second gate input terminal and a second gate intermediate terminal; a first gate capacitor connected between the first gate input terminal and the second gate input terminal; and a second gate capacitor connected between the second gate intermediate terminal and a second drain of the second HEMT, and the second driver comprising a second FB connected between the second gate input terminal and a second gate intermediate terminal. Original

A power converter, comprising: a first power terminal and a second power terminal; a first upper series-stacked high electron mobility transistor (HEMT) module connected to the first power te rm inal and a first intermediate terminal; a first lower se ries-stacked H EMT module connected to the second power terminal and the first intermediate terminal; a first inductor connected to the first intermediate terminal and a third power terminal; and a fourth power terminal connected to the second power terminal-a fifth power terminal and a sixth power terminal: a sec ond uppe r series-stacked H EM T module connected to the fi ft h power terminal and a second intermediate terminal: a second lower series-stacked HEMT module connected to the sixth power terminal and the second intermediate termi nal; a second inductor connec ted to the second inte rm ediate terminal and a seventh power terminal: and an ei g hth power te r minal connected to the sixth power terminal, each of the first upper series-stacked HEM "T module and the first lower series-stacked HEMT module comprising a fir st plurality of HEMTs and a first series-switch-driver connected to each gate of the f irst plurality of HEMTs, and each of the second upper series-stacked II EMT module and the second lower series-stacked HEMT module comprising a se cond plurality of HEMTs and a second series-switch-driver connected to each gate o f the second plurality of H EMTs. Currently amended

Canceled

, A power con verter, comprising: a first pow er terminal and a second power terminal; a first upper series-stacked high electron mobility transistor (I- EMT) module connected to the first power terminal and a first intermediate terminal; a first lowe r series-stacked HEM T module connected to the second power terminal and the first intermediate terminal; a first inductor connected to the first inte rm ediate terminal and a third power terminal; and a fourth p ower terminal connected to the second power terminal, each of the first uppe r series-stacked HEM T module and the first lower series-sta cked H EMT module com prising a first plurality of HEMTs and a f irs t series-switch-driver connected to each gate of th e first plurality of HEMTs, each of the fi rst upper series-stacked HEMT module and the first lower series-stacked H EMT module co m prising: a first HEM T; a second H E MT, a first drain of the first HE MT being connected to a second source of the second HEMT; a first gate input terminal coupled to a first gate of the fi rst HEMT; a second gate input te rm inal coupled to a second gate o f the second H EMT; a first driver connected between the first gate input terminal and a first gate intermediate terminal; a first FB connected between the first gate intermediate terminal and the first gate of the f irst HE MT; a second driver connected between the second gate input terminal and a second gate intermediate terminal; a first gate capacitor connected between the first gate input terminal and the second gate input terminal; and a second gate capacitor connected between the second gate intermediate terminal and a second drain of the second HEMT, and the second driver comprising a second FB connected between the second gate input terminal and a second gate inte rm ediate terminal. Currently amended

A power converter, comprising: a first power te r m inal and a second power terminal; SVG 15979892.11-08-2018.JO₈YY₃K₈RXEAPX0.CLM.1.svg 0.16 6.01 Black and white fi rst power terminal and a first intermediate terminal; a first lower series-stacked HEMT module connected to the second power terminal and the fi rst inte nn ediate terminal: a first inductor co nnected to the first inter mediate te rminal and a third power terminal; and a fourth power terminal connected to the second power terminal, each o f the first upper series-stacked HEMT module and the first lower series-stacked HE M T module comprising a first plurality of HEMTs and a first series-switch-driver connected to each g ate of the first plurality of H E MT s. and each of the first upper series-stacked HEMT module and the first lower series-stacked HEMT module comprising: first to nth HEMTs being connected in series to each other; first to nth gate input terminals coupled to first to nth gates of first to nth gate HEM I s through first to nth gate intermediate terminal, respectively; first to nth drivers connected between the first to nth gate input te nm inals and the first to nth gate intermediate terminal; a first gate capacitor connected between the first gate input terminal and the second gate input terminal; a kth gate capacitor connected between a (k +1)th gate input terminal and a kth source, k being from 2 to (n- 1); a nth gate capacitor connected between a n t h gate intermediate terminal and a nth drain. Currently amended

Canceled

A power converter, comprising: a first power terminal and a second power terminal; a first upper series-stacked high electron mobility transistor (HEMT) module connected to the first power terminal and a first intermediate terminal; a first lower series-stacked HEMT module connected to the second power ter m inal and the first intermediate terminal; a first inductor connected to the first intermediate terminal and a third power terminal; a fourth power terminal connected to the second power terminal; a fifth power terminal and a sixth power ter m inal; a second upper series-stacked IlEM T module connected to the fifth power te rm inal and a second intermediate terminal; a second lower series-stacked HEMT module connected to the sixth power terminal and the second intermediate terminal; a second inductor connected to the second intermediate terminal and a seventh power terminal; and an eighth power terminal connected to the sixth power terminal, each of the first upper series-stacked HEMT module and the first lower series-stacked H EMT module comprising a first plurality of HEMTs and a fi rst series-switch-driver connected to each gate of the first plurality of HEM Ts, each of the second upper series-stacked HEMT module and the second lower series-stacked SVG 15979892.11-08-2018.JO₈YY₃K₈RXEAPX0.CLM.2.svg 0.16 6.51 Black and white connected to each gate of the second plurality of HEMTs. each of the first upper series-stacked HEM T module, the first lower series-stacked I IEMT module, the second upper series-stacked HEMT module, and the second lower series-stacked H EMT module comprising: a first HEMT; a second H EMT, a first drain of the first HEMT being connected to a second source of the second HEMT; a first gate input terminal coupled to a first gate of the first H E MT; a second gate input terminal coupled to a second gate of the second H EMT; a first driver connected between the first gate input terminal and a first gate intermediate terminal; a first FB connected between the first gate intermediate terminal and the first gate of the first HEMT; a second driver connected between the second gate input terminal and a second gate intermediate terminal; a first gate capacitor connected between the first gate input terminal and the second gate input terminal; and a second gate capacitor connected between the second gate intermediate terminal and a second drain of the second HEMT, and the second driver comprising a second FB connected between the second gate input terminal and a second gate intermediate terminal. Original

A power converter, comprising: a first power terminal and a second power terminal; a first upper series-stacked high electron mobility transistor (HEMT) module connected to the first power te rm inal and a first intermediate terminal; a first lower se ries-stacked H EMT module connected to the second power terminal and the first intermediate terminal; a first inductor connected to the first intermediate terminal and a third power terminal; and a fourth power terminal connected to the second power terminal-a fifth power terminal and a sixth power terminal: a sec ond uppe r series-stacked H EM T module connected to the fi ft h power terminal and a second intermediate terminal: a second lower series-stacked HEMT module connected to the sixth power terminal and the second intermediate termi nal; a second inductor connec ted to the second inte rm ediate terminal and a seventh power terminal: and an ei g hth power te r minal connected to the sixth power terminal, each of the first upper series-stacked HEM "T module and the first lower series-stacked HEMT module comprising a fir st plurality of HEMTs and a first series-switch-driver connected to each gate of the f irst plurality of HEMTs, and each of the second upper series-stacked II EMT module and the second lower series-stacked HEMT module comprising a se cond plurality of HEMTs and a second series-switch-driver connected to each gate o f the second plurality of H EMTs. Currently amended

Canceled

, A power con verter, comprising: a first pow er terminal and a second power terminal; a first upper series-stacked high electron mobility transistor (I- EMT) module connected to the first power terminal and a first intermediate terminal; a first lowe r series-stacked HEM T module connected to the second power terminal and the first intermediate terminal; a first inductor connected to the first inte rm ediate terminal and a third power terminal; and a fourth p ower terminal connected to the second power terminal, each of the first uppe r series-stacked HEM T module and the first lower series-sta cked H EMT module com prising a first plurality of HEMTs and a f irs t series-switch-driver connected to each gate of th e first plurality of HEMTs, each of the fi rst upper series-stacked HEMT module and the first lower series-stacked H EMT module co m prising: a first HEM T; a second H E MT, a first drain of the first HE MT being connected to a second source of the second HEMT; a first gate input terminal coupled to a first gate of the fi rst HEMT; a second gate input te rm inal coupled to a second gate o f the second H EMT; a first driver connected between the first gate input terminal and a first gate intermediate terminal; a first FB connected between the first gate intermediate terminal and the first gate of the f irst HE MT; a second driver connected between the second gate input terminal and a second gate intermediate terminal; a first gate capacitor connected between the first gate input terminal and the second gate input terminal; and a second gate capacitor connected between the second gate intermediate terminal and a second drain of the second HEMT, and the second driver comprising a second FB connected between the second gate input terminal and a second gate inte rm ediate terminal. Currently amended

A power converter, comprising: a first power te r m inal and a second power terminal; SVG 15979892.11-08-2018.JO₈YY₃K₈RXEAPX0.CLM.1.svg 0.16 6.01 Black and white fi rst power terminal and a first intermediate terminal; a first lower series-stacked HEMT module connected to the second power terminal and the fi rst inte nn ediate terminal: a first inductor co nnected to the first inter mediate te rminal and a third power terminal; and a fourth power terminal connected to the second power terminal, each o f the first upper series-stacked HEMT module and the first lower series-stacked HE M T module comprising a first plurality of HEMTs and a first series-switch-driver connected to each g ate of the first plurality of H E MT s. and each of the first upper series-stacked HEMT module and the first lower series-stacked HEMT module comprising: first to nth HEMTs being connected in series to each other; first to nth gate input terminals coupled to first to nth gates of first to nth gate HEM I s through first to nth gate intermediate terminal, respectively; first to nth drivers connected between the first to nth gate input te nm inals and the first to nth gate intermediate terminal; a first gate capacitor connected between the first gate input terminal and the second gate input terminal; a kth gate capacitor connected between a (k +1)th gate input terminal and a kth source, k being from 2 to (n- 1); a nth gate capacitor connected between a n t h gate intermediate terminal and a nth drain. Currently amended

Canceled

A power converter, comprising: a first power terminal and a second power terminal; a first upper series-stacked high electron mobility transistor (HEMT) module connected to the first power terminal and a first intermediate terminal; a first lower series-stacked HEMT module connected to the second power ter m inal and the first intermediate terminal; a first inductor connected to the first intermediate terminal and a third power terminal; a fourth power terminal connected to the second power terminal; a fifth power terminal and a sixth power ter m inal; a second upper series-stacked IlEM T module connected to the fifth power te rm inal and a second intermediate terminal; a second lower series-stacked HEMT module connected to the sixth power terminal and the second intermediate terminal; a second inductor connected to the second intermediate terminal and a seventh power terminal; and an eighth power terminal connected to the sixth power terminal, each of the first upper series-stacked HEMT module and the first lower series-stacked H EMT module comprising a first plurality of HEMTs and a fi rst series-switch-driver connected to each gate of the first plurality of HEM Ts, each of the second upper series-stacked HEMT module and the second lower series-stacked SVG 15979892.11-08-2018.JO₈YY₃K₈RXEAPX0.CLM.2.svg 0.16 6.51 Black and white connected to each gate of the second plurality of HEMTs. each of the first upper series-stacked HEM T module, the first lower series-stacked I IEMT module, the second upper series-stacked HEMT module, and the second lower series-stacked H EMT module comprising: a first HEMT; a second H EMT, a first drain of the first HEMT being connected to a second source of the second HEMT; a first gate input terminal coupled to a first gate of the first H E MT; a second gate input terminal coupled to a second gate of the second H EMT; a first driver connected between the first gate input terminal and a first gate intermediate terminal; a first FB connected between the first gate intermediate terminal and the first gate of the first HEMT; a second driver connected between the second gate input terminal and a second gate intermediate terminal; a first gate capacitor connected between the first gate input terminal and the second gate input terminal; and a second gate capacitor connected between the second gate intermediate terminal and a second drain of the second HEMT, and the second driver comprising a second FB connected between the second gate input terminal and a second gate intermediate terminal. Original