Patent
US 10,290,623GATE INPUT PROTECTION FOR DEVICES AND SYSTEMS COMPRISING HIGH POWER E-MODE GaN TRANSISTORS
John ROBERTS
US
Copyright © 2026 Matter42. All rights reserved.
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Atlas literature
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US 10,290,623Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Canceled
A GaN power switching device comprising a GaN power transistor D 1 and an integrated gate protection device P for negative ESD spike protection, the GaN power transistor D l comprising an enhancement mode GaN power transistor having a drain, an intrinsic source, and a gate of gate width Wg; the integrated gate protection device P comprising first and second GaN protection transistors P₁ and P2, each comprising an enhancement mode GaN transistor having a source, a drain, a gate of gate width w, smaller than Wg, and having its gate connected to its source, the first and second GaN protection transistors P₁ and P₂ being connected in series as a stack, with the source of the first GaN protection transistor P₁ being connected to the drain of the second GaN protection transistor P2; the drain of the first GaN protection transistor P₁ being connected to a gate input of the GaN power transistor D 1, and the source of the second GaN protection transistor P₂ being connected to the intrinsic source of the GaN power transistor D 1; an effective threshold voltage of the integrated gate protection device P being a sum of threshold voltages for reverse conduction of the GaN protection transistors P₁ and P2, wherein, the 1 2 integrated gate protection device P is normally off, and when a gate input voltage of the GaN power transistor D 1 applied to the drain of P₁ is taken negativ-, by more than the effective threshold voltage, the integrated gate protection device P conducts, and wherein the sum of threshold voltages for reverse conduction of P₁ and P₂ is -3V or less, and gate widths w, of P₁ and P₂ are selected to limit a negative gate voltage excursion of D 1 to maintain a gate voltage of D 1 above-bV. Currently amended
A GaN power switching device comprising a GaN power transistor D 1 and an integrated gate protection device P for negative ESD spike protection, the GaN power transistor D 1 comprising an enhancement mode GaN power transistor having a drain, an intrinsic source, and a gate of gate width Wg; the integrated gate protection device P comprising a plurality of n GaN protection transistors P1, P2,...Pn, each comprising an enhancement mode GaN transistor having a drain, a source and a gate of gate width w g smaller than Wg, the gate of each GaN protection transistor P1, P2,...Pn being connected to its source; the n GaN protection transistors being connected in series as a stack, for i= 1 to n- 1, the source of the ith GaN protection transistor being connected to the drain of the i+ l th GaN protection transistor, the drain of first GaN protection transistor P₁ being connected to a gate input of the GaN power transistor D l, the source of the nth GaN protection transistor Pn being connected to the intrinsic source of the GaN power transistor D 1; an effective threshold voltage of the protection device P being a sum of threshold voltages for reverse conduction of each of the n GaN protection transistors P1, P2,...Pn, wherein, the GaN protection device P is normally off, and when a gate input voltage of the GaN power transistor D 1 applied to the drain of P₁ is taken negative by more than the effective threshold voltage, the GaN protection device P conducts, and a gate width of the protection device P being a combined gate width of the stack of n GaN protection transistors P1, P2,...Pn, the gate width of the protection device P being selected to limit a negative gate voltage excursion of the gate of GaN power transistor D 1; and wherein number n of GaN protection transistors P1, P2,...Pn is selected to set the effective threshold voltage of the GaN protection device P at -3V or less. Currently amended
The device of claim 3 wherein the gate width of the protection device P is selected to limit the negative gate voltage excursion of the GaN power transistor D 1 e- and maintain a gate voltage of D₁ above-lOV. Currently amended
The device of claim 3 further comprising an integrated resistor connected between a gate input terminal of D 1 and a connection te-of the drain of P₁ to the gate of D 1. Currently amended
The device of claim 3,, wherein the gate width of the protection device P is selected to limit the negative g ate voltage excursion of the GaN power transistor D l and maintain a gate voltage of D 1 above-1O V, and further comprising an integrated resistor connected between a gate input terminal of GaN power transistor D 1 and a connection of the drain of P₁ to the gate of GaN power transistor D 1. Currently amended
. Canceled
Canceled
A GaN power switching device comprising a GaN power transistor D 1 and an integrated gate protection device P for positive spike ESD protection, the GaN power transistor D 1 comprising an enhancement mode GaN power transistor having a drain, an intrinsic source and a gate of gate width Wg; the integrated gate protection device P comprising a plurality of n GaN protection transistors P1, P2,...Pn, each comprising an enhancement mode GaN transistor, having a drain, a source and a gate of gate width w g smaller than Wg, the gate of each GaN protection transistor P1, P2,...Pn being connected to its drain; the n GaN protection transistors being connected in series as a stack, for i= 1 to n- 1, the source of the ith GaN protection transistor being connected to the drain of the i+ l th GaN protection transistor, the drain of first GaN protection transistor P₁ being connected to a gate input of the GaN power transistor D l, the source of the nth GaN protection transistor Pn being connected to the intrinsic source of the GaN power transistor D 1; an effective threshold voltage of the protection device P comprising the stack of n GaN protection transistors being the sum of threshold voltages for conduction of each of the n GaN protection transistors P1, P2,...Pn, wherein the GaN protection device P is normally off, and when a gate input voltage of the GaN power transistor D l applied to the drain of P₁ is taken positive by more than the effective threshold voltage, the GaN protection device P conducts, and a gate width of the protection device P being a combined gate width of the stack of n GaN protection transistors P1, P2,...Pn, the gate width of the protection device P being selected to limit a positive gate voltage excursion of the gate of GaN power transistor D 1; and wherein number n of GaN protection transistors P₁ to Pn is selected to set the effective threshold voltage of the GaN protection device P to be at least 8V. Currently amended
The device of claim 9, wherein the gate width of the protection device P is selected to limit a peak gate voltage excursion of the GaN power transistor D 1 to between 1O V and 16V. Currently amended
. Canceled
Canceled
, A GaN power switching device comprising a GaN power transistor D l and an integrated gate protection device P for ESD spike protection, the GaN power transistor D l comprising an enhancement mode GaN power transistor having a drain, an intrinsic source and a gate of gate width Wg; the integrated gate protection device P comprising a GaN protection transistor Pm and a voltage divider, the GaN protection transistor comprising an enhancement mode GaN transistor, having a drain, a source and a gate of gate width w, smaller than Wg, the drain of the GaN protection transistor Pm being connected between the gate and a gate input terminal of the GaN power transistor D 1, and the source of the GaN protection transistor Pm being connected to the intrinsic source of the GaN power transistor D 1; and the voltage divider connected between the gate input terminal of GaN power transistor D₁ and the drain and the source of the protection transistor Pm for controlling a gate voltage to the GaN protection transistor Pm, the voltage divider being configured to divide an input voltage applied to gate input terminal of GaN power transistor D 1 in a required ratio such that when an input voltage at the gate input terminal of GaN power transistor D 1 exceeds a threshold voltage of protection transistor Pm by a selected multiple, the GaN protection transistor Pm conducts,, and wherein, because the GaN protection transistor Pm can conduct in either direction, positive and negative excess voltages are thereby clamped to protect the aN power transistor D 1. Currently amended
The GaN power switching device of claim 13, wherein the voltage divider comprises an integrated voltage divider comprising a string of a plurality n of enhancement mode GaN protection transistors P₁ to Pn, each having a drain, a source and a gate of a gate width smaller than the gate width w g of the GaN protection transistor Pm, and the string of n GaN protection transistors P₁ to Pn being arranged to divide the input voltage in the required ratio; each of the string of GaN protection transistors P₁ to Pn having its gate connected to its drain, with the drain o first transistor P₁ being connected te between the gate and the gate input terminal of GaN power transistor D 1 and the source of nth transistor Pn being connected to the source of protection transistor Pm, and the drain of the nth transistor Pn being connected to the gate of protection transistor Pm. Currently amended
A GaN power switching device comprising a GaN power transistor D 1 and an integrated gate protection device P for negative and positive ESD spike protection, the GaN power transistor D l comprising an enhancement mode GaN power transistor having a drain, an intrinsic source, and a gate of gate width Wg; the integrated gate protection device P comprising a GaN protection transistor Pm comprising an enhancement mode GaN transistor having a drain, a source, and a gate of gate width w g (m) smaller than Wg, the gate of the GaN protection transistor Pm being connected to the source of the GaN protection transistor Pm, the drain of the GaN protection transistor Pm being connected to a gate input of the GaN power transistor D 1, and the source of the GaN protection transistor Pm being connected to the intrinsic source of the GaN power transistor D 1; wherein, the GaN protection device P is normally off, and when a gate input voltage of the GaN power transistor D 1 applied to the drain of the GaN protection transistor Pm is taken negative by more than a threshold voltage for reverse conduction of GaN protection transistor Pm, the protection device P conducts; and a string of a plurality n of enhancement mode GaN protection transistors P₁ to Pn, each having a smaller gate width w g (n) than that of the protection transistor Pm, P₁ to Pn being arranged as a voltage divider; each of the string of GaN protection transistors having its gate connected to its drain, with the drain of the P₁ transistor being connected to the gate input of D₁ and the source of Pn being connected to the source of protection transistor Pm, and the drain of the protection transistor Pn being connected to the gate of protection transistor Pm[[,]]; and wherein, the voltage divider is configured to divide the gate input voltage in a required ratio such that the protection transistor Pm becomes active if the input voltage at the gate input exceeds a threshold voltage multiple of the threshold voltage of protection
The GaN power switching device of claim turn on voltage of a t least 1OV. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
GaN power switching device with two-transistor stack negative ESD protection (P1, P₂ gate-source connected)
GaN power switching device with n-transistor stack negative ESD protection (gate-source connected, effective threshold -3V or less)
Materials described outside the worked examples.
GaN (gallium nitride)
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Threshold voltage for reverse conduction of single GaN protection transistor (approximate) | -1.6 V | GaN |
Effective threshold voltage of negative ESD protection device P (stack), claimed upper limit |
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Atlas literature
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US 10,290,623Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Canceled
A GaN power switching device comprising a GaN power transistor D 1 and an integrated gate protection device P for negative ESD spike protection, the GaN power transistor D l comprising an enhancement mode GaN power transistor having a drain, an intrinsic source, and a gate of gate width Wg; the integrated gate protection device P comprising first and second GaN protection transistors P₁ and P2, each comprising an enhancement mode GaN transistor having a source, a drain, a gate of gate width w, smaller than Wg, and having its gate connected to its source, the first and second GaN protection transistors P₁ and P₂ being connected in series as a stack, with the source of the first GaN protection transistor P₁ being connected to the drain of the second GaN protection transistor P2; the drain of the first GaN protection transistor P₁ being connected to a gate input of the GaN power transistor D 1, and the source of the second GaN protection transistor P₂ being connected to the intrinsic source of the GaN power transistor D 1; an effective threshold voltage of the integrated gate protection device P being a sum of threshold voltages for reverse conduction of the GaN protection transistors P₁ and P2, wherein, the 1 2 integrated gate protection device P is normally off, and when a gate input voltage of the GaN power transistor D 1 applied to the drain of P₁ is taken negativ-, by more than the effective threshold voltage, the integrated gate protection device P conducts, and wherein the sum of threshold voltages for reverse conduction of P₁ and P₂ is -3V or less, and gate widths w, of P₁ and P₂ are selected to limit a negative gate voltage excursion of D 1 to maintain a gate voltage of D 1 above-bV. Currently amended
A GaN power switching device comprising a GaN power transistor D 1 and an integrated gate protection device P for negative ESD spike protection, the GaN power transistor D 1 comprising an enhancement mode GaN power transistor having a drain, an intrinsic source, and a gate of gate width Wg; the integrated gate protection device P comprising a plurality of n GaN protection transistors P1, P2,...Pn, each comprising an enhancement mode GaN transistor having a drain, a source and a gate of gate width w g smaller than Wg, the gate of each GaN protection transistor P1, P2,...Pn being connected to its source; the n GaN protection transistors being connected in series as a stack, for i= 1 to n- 1, the source of the ith GaN protection transistor being connected to the drain of the i+ l th GaN protection transistor, the drain of first GaN protection transistor P₁ being connected to a gate input of the GaN power transistor D l, the source of the nth GaN protection transistor Pn being connected to the intrinsic source of the GaN power transistor D 1; an effective threshold voltage of the protection device P being a sum of threshold voltages for reverse conduction of each of the n GaN protection transistors P1, P2,...Pn, wherein, the GaN protection device P is normally off, and when a gate input voltage of the GaN power transistor D 1 applied to the drain of P₁ is taken negative by more than the effective threshold voltage, the GaN protection device P conducts, and a gate width of the protection device P being a combined gate width of the stack of n GaN protection transistors P1, P2,...Pn, the gate width of the protection device P being selected to limit a negative gate voltage excursion of the gate of GaN power transistor D 1; and wherein number n of GaN protection transistors P1, P2,...Pn is selected to set the effective threshold voltage of the GaN protection device P at -3V or less. Currently amended
The device of claim 3 wherein the gate width of the protection device P is selected to limit the negative gate voltage excursion of the GaN power transistor D 1 e- and maintain a gate voltage of D₁ above-lOV. Currently amended
The device of claim 3 further comprising an integrated resistor connected between a gate input terminal of D 1 and a connection te-of the drain of P₁ to the gate of D 1. Currently amended
The device of claim 3,, wherein the gate width of the protection device P is selected to limit the negative g ate voltage excursion of the GaN power transistor D l and maintain a gate voltage of D 1 above-1O V, and further comprising an integrated resistor connected between a gate input terminal of GaN power transistor D 1 and a connection of the drain of P₁ to the gate of GaN power transistor D 1. Currently amended
. Canceled
Canceled
A GaN power switching device comprising a GaN power transistor D 1 and an integrated gate protection device P for positive spike ESD protection, the GaN power transistor D 1 comprising an enhancement mode GaN power transistor having a drain, an intrinsic source and a gate of gate width Wg; the integrated gate protection device P comprising a plurality of n GaN protection transistors P1, P2,...Pn, each comprising an enhancement mode GaN transistor, having a drain, a source and a gate of gate width w g smaller than Wg, the gate of each GaN protection transistor P1, P2,...Pn being connected to its drain; the n GaN protection transistors being connected in series as a stack, for i= 1 to n- 1, the source of the ith GaN protection transistor being connected to the drain of the i+ l th GaN protection transistor, the drain of first GaN protection transistor P₁ being connected to a gate input of the GaN power transistor D l, the source of the nth GaN protection transistor Pn being connected to the intrinsic source of the GaN power transistor D 1; an effective threshold voltage of the protection device P comprising the stack of n GaN protection transistors being the sum of threshold voltages for conduction of each of the n GaN protection transistors P1, P2,...Pn, wherein the GaN protection device P is normally off, and when a gate input voltage of the GaN power transistor D l applied to the drain of P₁ is taken positive by more than the effective threshold voltage, the GaN protection device P conducts, and a gate width of the protection device P being a combined gate width of the stack of n GaN protection transistors P1, P2,...Pn, the gate width of the protection device P being selected to limit a positive gate voltage excursion of the gate of GaN power transistor D 1; and wherein number n of GaN protection transistors P₁ to Pn is selected to set the effective threshold voltage of the GaN protection device P to be at least 8V. Currently amended
The device of claim 9, wherein the gate width of the protection device P is selected to limit a peak gate voltage excursion of the GaN power transistor D 1 to between 1O V and 16V. Currently amended
. Canceled
Canceled
, A GaN power switching device comprising a GaN power transistor D l and an integrated gate protection device P for ESD spike protection, the GaN power transistor D l comprising an enhancement mode GaN power transistor having a drain, an intrinsic source and a gate of gate width Wg; the integrated gate protection device P comprising a GaN protection transistor Pm and a voltage divider, the GaN protection transistor comprising an enhancement mode GaN transistor, having a drain, a source and a gate of gate width w, smaller than Wg, the drain of the GaN protection transistor Pm being connected between the gate and a gate input terminal of the GaN power transistor D 1, and the source of the GaN protection transistor Pm being connected to the intrinsic source of the GaN power transistor D 1; and the voltage divider connected between the gate input terminal of GaN power transistor D₁ and the drain and the source of the protection transistor Pm for controlling a gate voltage to the GaN protection transistor Pm, the voltage divider being configured to divide an input voltage applied to gate input terminal of GaN power transistor D 1 in a required ratio such that when an input voltage at the gate input terminal of GaN power transistor D 1 exceeds a threshold voltage of protection transistor Pm by a selected multiple, the GaN protection transistor Pm conducts,, and wherein, because the GaN protection transistor Pm can conduct in either direction, positive and negative excess voltages are thereby clamped to protect the aN power transistor D 1. Currently amended
The GaN power switching device of claim 13, wherein the voltage divider comprises an integrated voltage divider comprising a string of a plurality n of enhancement mode GaN protection transistors P₁ to Pn, each having a drain, a source and a gate of a gate width smaller than the gate width w g of the GaN protection transistor Pm, and the string of n GaN protection transistors P₁ to Pn being arranged to divide the input voltage in the required ratio; each of the string of GaN protection transistors P₁ to Pn having its gate connected to its drain, with the drain o first transistor P₁ being connected te between the gate and the gate input terminal of GaN power transistor D 1 and the source of nth transistor Pn being connected to the source of protection transistor Pm, and the drain of the nth transistor Pn being connected to the gate of protection transistor Pm. Currently amended
A GaN power switching device comprising a GaN power transistor D 1 and an integrated gate protection device P for negative and positive ESD spike protection, the GaN power transistor D l comprising an enhancement mode GaN power transistor having a drain, an intrinsic source, and a gate of gate width Wg; the integrated gate protection device P comprising a GaN protection transistor Pm comprising an enhancement mode GaN transistor having a drain, a source, and a gate of gate width w g (m) smaller than Wg, the gate of the GaN protection transistor Pm being connected to the source of the GaN protection transistor Pm, the drain of the GaN protection transistor Pm being connected to a gate input of the GaN power transistor D 1, and the source of the GaN protection transistor Pm being connected to the intrinsic source of the GaN power transistor D 1; wherein, the GaN protection device P is normally off, and when a gate input voltage of the GaN power transistor D 1 applied to the drain of the GaN protection transistor Pm is taken negative by more than a threshold voltage for reverse conduction of GaN protection transistor Pm, the protection device P conducts; and a string of a plurality n of enhancement mode GaN protection transistors P₁ to Pn, each having a smaller gate width w g (n) than that of the protection transistor Pm, P₁ to Pn being arranged as a voltage divider; each of the string of GaN protection transistors having its gate connected to its drain, with the drain of the P₁ transistor being connected to the gate input of D₁ and the source of Pn being connected to the source of protection transistor Pm, and the drain of the protection transistor Pn being connected to the gate of protection transistor Pm[[,]]; and wherein, the voltage divider is configured to divide the gate input voltage in a required ratio such that the protection transistor Pm becomes active if the input voltage at the gate input exceeds a threshold voltage multiple of the threshold voltage of protection
The GaN power switching device of claim turn on voltage of a t least 1OV. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
GaN power switching device with two-transistor stack negative ESD protection (P1, P₂ gate-source connected)
GaN power switching device with n-transistor stack negative ESD protection (gate-source connected, effective threshold -3V or less)
Materials described outside the worked examples.
GaN (gallium nitride)
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Threshold voltage for reverse conduction of single GaN protection transistor (approximate) | -1.6 V | GaN |
Effective threshold voltage of negative ESD protection device P (stack), claimed upper limit |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,290,623Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Canceled
A GaN power switching device comprising a GaN power transistor D 1 and an integrated gate protection device P for negative ESD spike protection, the GaN power transistor D l comprising an enhancement mode GaN power transistor having a drain, an intrinsic source, and a gate of gate width Wg; the integrated gate protection device P comprising first and second GaN protection transistors P₁ and P2, each comprising an enhancement mode GaN transistor having a source, a drain, a gate of gate width w, smaller than Wg, and having its gate connected to its source, the first and second GaN protection transistors P₁ and P₂ being connected in series as a stack, with the source of the first GaN protection transistor P₁ being connected to the drain of the second GaN protection transistor P2; the drain of the first GaN protection transistor P₁ being connected to a gate input of the GaN power transistor D 1, and the source of the second GaN protection transistor P₂ being connected to the intrinsic source of the GaN power transistor D 1; an effective threshold voltage of the integrated gate protection device P being a sum of threshold voltages for reverse conduction of the GaN protection transistors P₁ and P2, wherein, the 1 2 integrated gate protection device P is normally off, and when a gate input voltage of the GaN power transistor D 1 applied to the drain of P₁ is taken negativ-, by more than the effective threshold voltage, the integrated gate protection device P conducts, and wherein the sum of threshold voltages for reverse conduction of P₁ and P₂ is -3V or less, and gate widths w, of P₁ and P₂ are selected to limit a negative gate voltage excursion of D 1 to maintain a gate voltage of D 1 above-bV. Currently amended
A GaN power switching device comprising a GaN power transistor D 1 and an integrated gate protection device P for negative ESD spike protection, the GaN power transistor D 1 comprising an enhancement mode GaN power transistor having a drain, an intrinsic source, and a gate of gate width Wg; the integrated gate protection device P comprising a plurality of n GaN protection transistors P1, P2,...Pn, each comprising an enhancement mode GaN transistor having a drain, a source and a gate of gate width w g smaller than Wg, the gate of each GaN protection transistor P1, P2,...Pn being connected to its source; the n GaN protection transistors being connected in series as a stack, for i= 1 to n- 1, the source of the ith GaN protection transistor being connected to the drain of the i+ l th GaN protection transistor, the drain of first GaN protection transistor P₁ being connected to a gate input of the GaN power transistor D l, the source of the nth GaN protection transistor Pn being connected to the intrinsic source of the GaN power transistor D 1; an effective threshold voltage of the protection device P being a sum of threshold voltages for reverse conduction of each of the n GaN protection transistors P1, P2,...Pn, wherein, the GaN protection device P is normally off, and when a gate input voltage of the GaN power transistor D 1 applied to the drain of P₁ is taken negative by more than the effective threshold voltage, the GaN protection device P conducts, and a gate width of the protection device P being a combined gate width of the stack of n GaN protection transistors P1, P2,...Pn, the gate width of the protection device P being selected to limit a negative gate voltage excursion of the gate of GaN power transistor D 1; and wherein number n of GaN protection transistors P1, P2,...Pn is selected to set the effective threshold voltage of the GaN protection device P at -3V or less. Currently amended
The device of claim 3 wherein the gate width of the protection device P is selected to limit the negative gate voltage excursion of the GaN power transistor D 1 e- and maintain a gate voltage of D₁ above-lOV. Currently amended
The device of claim 3 further comprising an integrated resistor connected between a gate input terminal of D 1 and a connection te-of the drain of P₁ to the gate of D 1. Currently amended
The device of claim 3,, wherein the gate width of the protection device P is selected to limit the negative g ate voltage excursion of the GaN power transistor D l and maintain a gate voltage of D 1 above-1O V, and further comprising an integrated resistor connected between a gate input terminal of GaN power transistor D 1 and a connection of the drain of P₁ to the gate of GaN power transistor D 1. Currently amended
. Canceled
Canceled
A GaN power switching device comprising a GaN power transistor D 1 and an integrated gate protection device P for positive spike ESD protection, the GaN power transistor D 1 comprising an enhancement mode GaN power transistor having a drain, an intrinsic source and a gate of gate width Wg; the integrated gate protection device P comprising a plurality of n GaN protection transistors P1, P2,...Pn, each comprising an enhancement mode GaN transistor, having a drain, a source and a gate of gate width w g smaller than Wg, the gate of each GaN protection transistor P1, P2,...Pn being connected to its drain; the n GaN protection transistors being connected in series as a stack, for i= 1 to n- 1, the source of the ith GaN protection transistor being connected to the drain of the i+ l th GaN protection transistor, the drain of first GaN protection transistor P₁ being connected to a gate input of the GaN power transistor D l, the source of the nth GaN protection transistor Pn being connected to the intrinsic source of the GaN power transistor D 1; an effective threshold voltage of the protection device P comprising the stack of n GaN protection transistors being the sum of threshold voltages for conduction of each of the n GaN protection transistors P1, P2,...Pn, wherein the GaN protection device P is normally off, and when a gate input voltage of the GaN power transistor D l applied to the drain of P₁ is taken positive by more than the effective threshold voltage, the GaN protection device P conducts, and a gate width of the protection device P being a combined gate width of the stack of n GaN protection transistors P1, P2,...Pn, the gate width of the protection device P being selected to limit a positive gate voltage excursion of the gate of GaN power transistor D 1; and wherein number n of GaN protection transistors P₁ to Pn is selected to set the effective threshold voltage of the GaN protection device P to be at least 8V. Currently amended
The device of claim 9, wherein the gate width of the protection device P is selected to limit a peak gate voltage excursion of the GaN power transistor D 1 to between 1O V and 16V. Currently amended
. Canceled
Canceled
, A GaN power switching device comprising a GaN power transistor D l and an integrated gate protection device P for ESD spike protection, the GaN power transistor D l comprising an enhancement mode GaN power transistor having a drain, an intrinsic source and a gate of gate width Wg; the integrated gate protection device P comprising a GaN protection transistor Pm and a voltage divider, the GaN protection transistor comprising an enhancement mode GaN transistor, having a drain, a source and a gate of gate width w, smaller than Wg, the drain of the GaN protection transistor Pm being connected between the gate and a gate input terminal of the GaN power transistor D 1, and the source of the GaN protection transistor Pm being connected to the intrinsic source of the GaN power transistor D 1; and the voltage divider connected between the gate input terminal of GaN power transistor D₁ and the drain and the source of the protection transistor Pm for controlling a gate voltage to the GaN protection transistor Pm, the voltage divider being configured to divide an input voltage applied to gate input terminal of GaN power transistor D 1 in a required ratio such that when an input voltage at the gate input terminal of GaN power transistor D 1 exceeds a threshold voltage of protection transistor Pm by a selected multiple, the GaN protection transistor Pm conducts,, and wherein, because the GaN protection transistor Pm can conduct in either direction, positive and negative excess voltages are thereby clamped to protect the aN power transistor D 1. Currently amended
The GaN power switching device of claim 13, wherein the voltage divider comprises an integrated voltage divider comprising a string of a plurality n of enhancement mode GaN protection transistors P₁ to Pn, each having a drain, a source and a gate of a gate width smaller than the gate width w g of the GaN protection transistor Pm, and the string of n GaN protection transistors P₁ to Pn being arranged to divide the input voltage in the required ratio; each of the string of GaN protection transistors P₁ to Pn having its gate connected to its drain, with the drain o first transistor P₁ being connected te between the gate and the gate input terminal of GaN power transistor D 1 and the source of nth transistor Pn being connected to the source of protection transistor Pm, and the drain of the nth transistor Pn being connected to the gate of protection transistor Pm. Currently amended
A GaN power switching device comprising a GaN power transistor D 1 and an integrated gate protection device P for negative and positive ESD spike protection, the GaN power transistor D l comprising an enhancement mode GaN power transistor having a drain, an intrinsic source, and a gate of gate width Wg; the integrated gate protection device P comprising a GaN protection transistor Pm comprising an enhancement mode GaN transistor having a drain, a source, and a gate of gate width w g (m) smaller than Wg, the gate of the GaN protection transistor Pm being connected to the source of the GaN protection transistor Pm, the drain of the GaN protection transistor Pm being connected to a gate input of the GaN power transistor D 1, and the source of the GaN protection transistor Pm being connected to the intrinsic source of the GaN power transistor D 1; wherein, the GaN protection device P is normally off, and when a gate input voltage of the GaN power transistor D 1 applied to the drain of the GaN protection transistor Pm is taken negative by more than a threshold voltage for reverse conduction of GaN protection transistor Pm, the protection device P conducts; and a string of a plurality n of enhancement mode GaN protection transistors P₁ to Pn, each having a smaller gate width w g (n) than that of the protection transistor Pm, P₁ to Pn being arranged as a voltage divider; each of the string of GaN protection transistors having its gate connected to its drain, with the drain of the P₁ transistor being connected to the gate input of D₁ and the source of Pn being connected to the source of protection transistor Pm, and the drain of the protection transistor Pn being connected to the gate of protection transistor Pm[[,]]; and wherein, the voltage divider is configured to divide the gate input voltage in a required ratio such that the protection transistor Pm becomes active if the input voltage at the gate input exceeds a threshold voltage multiple of the threshold voltage of protection
The GaN power switching device of claim turn on voltage of a t least 1OV. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
GaN power switching device with two-transistor stack negative ESD protection (P1, P₂ gate-source connected)
GaN power switching device with n-transistor stack negative ESD protection (gate-source connected, effective threshold -3V or less)
Materials described outside the worked examples.
GaN (gallium nitride)
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Threshold voltage for reverse conduction of single GaN protection transistor (approximate) | -1.6 V | GaN |
Effective threshold voltage of negative ESD protection device P (stack), claimed upper limit |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 10,290,623Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
Canceled
A GaN power switching device comprising a GaN power transistor D 1 and an integrated gate protection device P for negative ESD spike protection, the GaN power transistor D l comprising an enhancement mode GaN power transistor having a drain, an intrinsic source, and a gate of gate width Wg; the integrated gate protection device P comprising first and second GaN protection transistors P₁ and P2, each comprising an enhancement mode GaN transistor having a source, a drain, a gate of gate width w, smaller than Wg, and having its gate connected to its source, the first and second GaN protection transistors P₁ and P₂ being connected in series as a stack, with the source of the first GaN protection transistor P₁ being connected to the drain of the second GaN protection transistor P2; the drain of the first GaN protection transistor P₁ being connected to a gate input of the GaN power transistor D 1, and the source of the second GaN protection transistor P₂ being connected to the intrinsic source of the GaN power transistor D 1; an effective threshold voltage of the integrated gate protection device P being a sum of threshold voltages for reverse conduction of the GaN protection transistors P₁ and P2, wherein, the 1 2 integrated gate protection device P is normally off, and when a gate input voltage of the GaN power transistor D 1 applied to the drain of P₁ is taken negativ-, by more than the effective threshold voltage, the integrated gate protection device P conducts, and wherein the sum of threshold voltages for reverse conduction of P₁ and P₂ is -3V or less, and gate widths w, of P₁ and P₂ are selected to limit a negative gate voltage excursion of D 1 to maintain a gate voltage of D 1 above-bV. Currently amended
A GaN power switching device comprising a GaN power transistor D 1 and an integrated gate protection device P for negative ESD spike protection, the GaN power transistor D 1 comprising an enhancement mode GaN power transistor having a drain, an intrinsic source, and a gate of gate width Wg; the integrated gate protection device P comprising a plurality of n GaN protection transistors P1, P2,...Pn, each comprising an enhancement mode GaN transistor having a drain, a source and a gate of gate width w g smaller than Wg, the gate of each GaN protection transistor P1, P2,...Pn being connected to its source; the n GaN protection transistors being connected in series as a stack, for i= 1 to n- 1, the source of the ith GaN protection transistor being connected to the drain of the i+ l th GaN protection transistor, the drain of first GaN protection transistor P₁ being connected to a gate input of the GaN power transistor D l, the source of the nth GaN protection transistor Pn being connected to the intrinsic source of the GaN power transistor D 1; an effective threshold voltage of the protection device P being a sum of threshold voltages for reverse conduction of each of the n GaN protection transistors P1, P2,...Pn, wherein, the GaN protection device P is normally off, and when a gate input voltage of the GaN power transistor D 1 applied to the drain of P₁ is taken negative by more than the effective threshold voltage, the GaN protection device P conducts, and a gate width of the protection device P being a combined gate width of the stack of n GaN protection transistors P1, P2,...Pn, the gate width of the protection device P being selected to limit a negative gate voltage excursion of the gate of GaN power transistor D 1; and wherein number n of GaN protection transistors P1, P2,...Pn is selected to set the effective threshold voltage of the GaN protection device P at -3V or less. Currently amended
The device of claim 3 wherein the gate width of the protection device P is selected to limit the negative gate voltage excursion of the GaN power transistor D 1 e- and maintain a gate voltage of D₁ above-lOV. Currently amended
The device of claim 3 further comprising an integrated resistor connected between a gate input terminal of D 1 and a connection te-of the drain of P₁ to the gate of D 1. Currently amended
The device of claim 3,, wherein the gate width of the protection device P is selected to limit the negative g ate voltage excursion of the GaN power transistor D l and maintain a gate voltage of D 1 above-1O V, and further comprising an integrated resistor connected between a gate input terminal of GaN power transistor D 1 and a connection of the drain of P₁ to the gate of GaN power transistor D 1. Currently amended
. Canceled
Canceled
A GaN power switching device comprising a GaN power transistor D 1 and an integrated gate protection device P for positive spike ESD protection, the GaN power transistor D 1 comprising an enhancement mode GaN power transistor having a drain, an intrinsic source and a gate of gate width Wg; the integrated gate protection device P comprising a plurality of n GaN protection transistors P1, P2,...Pn, each comprising an enhancement mode GaN transistor, having a drain, a source and a gate of gate width w g smaller than Wg, the gate of each GaN protection transistor P1, P2,...Pn being connected to its drain; the n GaN protection transistors being connected in series as a stack, for i= 1 to n- 1, the source of the ith GaN protection transistor being connected to the drain of the i+ l th GaN protection transistor, the drain of first GaN protection transistor P₁ being connected to a gate input of the GaN power transistor D l, the source of the nth GaN protection transistor Pn being connected to the intrinsic source of the GaN power transistor D 1; an effective threshold voltage of the protection device P comprising the stack of n GaN protection transistors being the sum of threshold voltages for conduction of each of the n GaN protection transistors P1, P2,...Pn, wherein the GaN protection device P is normally off, and when a gate input voltage of the GaN power transistor D l applied to the drain of P₁ is taken positive by more than the effective threshold voltage, the GaN protection device P conducts, and a gate width of the protection device P being a combined gate width of the stack of n GaN protection transistors P1, P2,...Pn, the gate width of the protection device P being selected to limit a positive gate voltage excursion of the gate of GaN power transistor D 1; and wherein number n of GaN protection transistors P₁ to Pn is selected to set the effective threshold voltage of the GaN protection device P to be at least 8V. Currently amended
The device of claim 9, wherein the gate width of the protection device P is selected to limit a peak gate voltage excursion of the GaN power transistor D 1 to between 1O V and 16V. Currently amended
. Canceled
Canceled
, A GaN power switching device comprising a GaN power transistor D l and an integrated gate protection device P for ESD spike protection, the GaN power transistor D l comprising an enhancement mode GaN power transistor having a drain, an intrinsic source and a gate of gate width Wg; the integrated gate protection device P comprising a GaN protection transistor Pm and a voltage divider, the GaN protection transistor comprising an enhancement mode GaN transistor, having a drain, a source and a gate of gate width w, smaller than Wg, the drain of the GaN protection transistor Pm being connected between the gate and a gate input terminal of the GaN power transistor D 1, and the source of the GaN protection transistor Pm being connected to the intrinsic source of the GaN power transistor D 1; and the voltage divider connected between the gate input terminal of GaN power transistor D₁ and the drain and the source of the protection transistor Pm for controlling a gate voltage to the GaN protection transistor Pm, the voltage divider being configured to divide an input voltage applied to gate input terminal of GaN power transistor D 1 in a required ratio such that when an input voltage at the gate input terminal of GaN power transistor D 1 exceeds a threshold voltage of protection transistor Pm by a selected multiple, the GaN protection transistor Pm conducts,, and wherein, because the GaN protection transistor Pm can conduct in either direction, positive and negative excess voltages are thereby clamped to protect the aN power transistor D 1. Currently amended
The GaN power switching device of claim 13, wherein the voltage divider comprises an integrated voltage divider comprising a string of a plurality n of enhancement mode GaN protection transistors P₁ to Pn, each having a drain, a source and a gate of a gate width smaller than the gate width w g of the GaN protection transistor Pm, and the string of n GaN protection transistors P₁ to Pn being arranged to divide the input voltage in the required ratio; each of the string of GaN protection transistors P₁ to Pn having its gate connected to its drain, with the drain o first transistor P₁ being connected te between the gate and the gate input terminal of GaN power transistor D 1 and the source of nth transistor Pn being connected to the source of protection transistor Pm, and the drain of the nth transistor Pn being connected to the gate of protection transistor Pm. Currently amended
A GaN power switching device comprising a GaN power transistor D 1 and an integrated gate protection device P for negative and positive ESD spike protection, the GaN power transistor D l comprising an enhancement mode GaN power transistor having a drain, an intrinsic source, and a gate of gate width Wg; the integrated gate protection device P comprising a GaN protection transistor Pm comprising an enhancement mode GaN transistor having a drain, a source, and a gate of gate width w g (m) smaller than Wg, the gate of the GaN protection transistor Pm being connected to the source of the GaN protection transistor Pm, the drain of the GaN protection transistor Pm being connected to a gate input of the GaN power transistor D 1, and the source of the GaN protection transistor Pm being connected to the intrinsic source of the GaN power transistor D 1; wherein, the GaN protection device P is normally off, and when a gate input voltage of the GaN power transistor D 1 applied to the drain of the GaN protection transistor Pm is taken negative by more than a threshold voltage for reverse conduction of GaN protection transistor Pm, the protection device P conducts; and a string of a plurality n of enhancement mode GaN protection transistors P₁ to Pn, each having a smaller gate width w g (n) than that of the protection transistor Pm, P₁ to Pn being arranged as a voltage divider; each of the string of GaN protection transistors having its gate connected to its drain, with the drain of the P₁ transistor being connected to the gate input of D₁ and the source of Pn being connected to the source of protection transistor Pm, and the drain of the protection transistor Pn being connected to the gate of protection transistor Pm[[,]]; and wherein, the voltage divider is configured to divide the gate input voltage in a required ratio such that the protection transistor Pm becomes active if the input voltage at the gate input exceeds a threshold voltage multiple of the threshold voltage of protection
The GaN power switching device of claim turn on voltage of a t least 1OV. Currently amended
Layer stacks claimed or described, ordered top of device to substrate.
GaN power switching device with two-transistor stack negative ESD protection (P1, P₂ gate-source connected)
GaN power switching device with n-transistor stack negative ESD protection (gate-source connected, effective threshold -3V or less)
Materials described outside the worked examples.
GaN (gallium nitride)
GaN
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
Threshold voltage for reverse conduction of single GaN protection transistor (approximate) | -1.6 V | GaN |
Effective threshold voltage of negative ESD protection device P (stack), claimed upper limit |
Related documents with shared materials, methods, properties, or citations.
GaN power switching device with n-transistor stack positive ESD protection (gate-drain connected, effective threshold >=8V)
GaN power switching device with protection transistor Pm and voltage divider for bidirectional ESD protection
GaN power switching device with gate-source connected Pm and voltage divider string for negative and positive ESD protection
| — |
GaN |
Effective threshold voltage of positive ESD protection device P (stack), claimed lower limit | — | GaN |
Voltage | 10–16 V | — |
Thickness | 0.1–5 mm | — |
Voltage | 25–150 V | — |
Voltage | ≥ 8 V | — |
Voltage | 1–12 V | — |
Voltage | ≥ 10 V | — |
REDUCED PUNCHTHROUGH BREAKDOWN IN GALLIUM-NITRIDE TRANSISTORS
GaN power switching device with n-transistor stack positive ESD protection (gate-drain connected, effective threshold >=8V)
GaN power switching device with protection transistor Pm and voltage divider for bidirectional ESD protection
GaN power switching device with gate-source connected Pm and voltage divider string for negative and positive ESD protection
| — |
GaN |
Effective threshold voltage of positive ESD protection device P (stack), claimed lower limit | — | GaN |
Voltage | 10–16 V | — |
Thickness | 0.1–5 mm | — |
Voltage | 25–150 V | — |
Voltage | ≥ 8 V | — |
Voltage | 1–12 V | — |
Voltage | ≥ 10 V | — |
REDUCED PUNCHTHROUGH BREAKDOWN IN GALLIUM-NITRIDE TRANSISTORS
GaN power switching device with n-transistor stack positive ESD protection (gate-drain connected, effective threshold >=8V)
GaN power switching device with protection transistor Pm and voltage divider for bidirectional ESD protection
GaN power switching device with gate-source connected Pm and voltage divider string for negative and positive ESD protection
| — |
GaN |
Effective threshold voltage of positive ESD protection device P (stack), claimed lower limit | — | GaN |
Voltage | 10–16 V | — |
Thickness | 0.1–5 mm | — |
Voltage | 25–150 V | — |
Voltage | ≥ 8 V | — |
Voltage | 1–12 V | — |
Voltage | ≥ 10 V | — |
REDUCED PUNCHTHROUGH BREAKDOWN IN GALLIUM-NITRIDE TRANSISTORS
GaN power switching device with n-transistor stack positive ESD protection (gate-drain connected, effective threshold >=8V)
GaN power switching device with protection transistor Pm and voltage divider for bidirectional ESD protection
GaN power switching device with gate-source connected Pm and voltage divider string for negative and positive ESD protection
| — |
GaN |
Effective threshold voltage of positive ESD protection device P (stack), claimed lower limit | — | GaN |
Voltage | 10–16 V | — |
Thickness | 0.1–5 mm | — |
Voltage | 25–150 V | — |
Voltage | ≥ 8 V | — |
Voltage | 1–12 V | — |
Voltage | ≥ 10 V | — |