Patent
US 11,355,625DEVICE AND SEMICONDUCTOR STRUCTURE FOR IMPROVING THE
Chun-Chieh YANG
US
Copyright © 2026 Matter42. All rights reserved.
Patent
Atlas literature
Patent
US 11,355,625Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device, comprising: a first transistor, comprising a first gate terminal, a first source terminal, and a first drain terminal, wherein the first gate terminal is coupled to the first source terminal; and a second transistor, comprising a second gate terminal, a second source terminal, and a second drain terminal, wherein the second gate terminal is coupled to the first drain terminal.
The device of claim 1, wherein each of the first transistor and the second transistor is an E-mode HEMT.
The device of claim 1, wherein each of the first transistor and the second transistor is a p- G aN gate H EMT.
The device of claim 1, wherein the device is an E-mode H EMT formed by the first transistor and the second transistor.
A semiconductor structure, comprising: a substrate; a I II -V compound buffer layer, disposed over the substrate, wherein a top of the I II-V compound buffer layer comprises a first region and a second region; a first I II -V compound layer, disposed in the first region and over the I II -V compound buffer layer; a second I II -V compound layer, disposed in the second region and over the I II-V compound buffer layer; a first gate structure, disposed over the first I II -V compound layer; a second gate structure, disposed over the second I II -V compound layer; a first source region, coupled to the first gate structure; a first drain region, coupled to the second gate structure, wherein the first source region and the first drain region are respectively disposed on two opposite sides of the first gate structure and over the first I II -V compound layer; a second source region; and a second drain region, wherein the second source region and the second drain region are respectively disposed on two opposite sides of the second gate structure and over the second I II -V compound layer.
The semiconductor structure of claim 11, wherein the first gate structure further comp ri ses: a first P-type I II -V compound layer, disposed over the first I II -V compound layer; and a first gate electrode, disposed over the first P-type I II -V compound layer.
The semiconductor structure of claim 11, wherein the second gate structure further comprises: a second P-type I II -V compound layer, disposed over the second I II -V compound layer; and a second gate electrode, disposed over the second P-type I II -V compound layer.
The semiconductor structure of claim 11, wherein a first e-mode H EMT and a second e-mode H EMT are formed in the first region and the second region respectively.
The semiconductor structure of claim 11, wherein the semiconductor structure forms an e-mode H EMT comprising a gate terminal, a source terminal, and a drain terminal, wherein the gate terminal is formed by the first gate structure, the source terminal is formed by the second source region, and the drain terminal is formed by the second drain region.
Layer stacks claimed or described, ordered top of device to substrate.
two-transistor cascode device
No layer stack recorded.
E-mode HEMT formed by first and second transistors
No layer stack recorded.
p-GaN gate HEMT
semiconductor structure with dual-region III-V HEMT
Materials described outside the worked examples.
p-GaN gate
III-V compound buffer layer
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,355,625Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device, comprising: a first transistor, comprising a first gate terminal, a first source terminal, and a first drain terminal, wherein the first gate terminal is coupled to the first source terminal; and a second transistor, comprising a second gate terminal, a second source terminal, and a second drain terminal, wherein the second gate terminal is coupled to the first drain terminal.
The device of claim 1, wherein each of the first transistor and the second transistor is an E-mode HEMT.
The device of claim 1, wherein each of the first transistor and the second transistor is a p- G aN gate H EMT.
The device of claim 1, wherein the device is an E-mode H EMT formed by the first transistor and the second transistor.
A semiconductor structure, comprising: a substrate; a I II -V compound buffer layer, disposed over the substrate, wherein a top of the I II-V compound buffer layer comprises a first region and a second region; a first I II -V compound layer, disposed in the first region and over the I II -V compound buffer layer; a second I II -V compound layer, disposed in the second region and over the I II-V compound buffer layer; a first gate structure, disposed over the first I II -V compound layer; a second gate structure, disposed over the second I II -V compound layer; a first source region, coupled to the first gate structure; a first drain region, coupled to the second gate structure, wherein the first source region and the first drain region are respectively disposed on two opposite sides of the first gate structure and over the first I II -V compound layer; a second source region; and a second drain region, wherein the second source region and the second drain region are respectively disposed on two opposite sides of the second gate structure and over the second I II -V compound layer.
The semiconductor structure of claim 11, wherein the first gate structure further comp ri ses: a first P-type I II -V compound layer, disposed over the first I II -V compound layer; and a first gate electrode, disposed over the first P-type I II -V compound layer.
The semiconductor structure of claim 11, wherein the second gate structure further comprises: a second P-type I II -V compound layer, disposed over the second I II -V compound layer; and a second gate electrode, disposed over the second P-type I II -V compound layer.
The semiconductor structure of claim 11, wherein a first e-mode H EMT and a second e-mode H EMT are formed in the first region and the second region respectively.
The semiconductor structure of claim 11, wherein the semiconductor structure forms an e-mode H EMT comprising a gate terminal, a source terminal, and a drain terminal, wherein the gate terminal is formed by the first gate structure, the source terminal is formed by the second source region, and the drain terminal is formed by the second drain region.
Layer stacks claimed or described, ordered top of device to substrate.
two-transistor cascode device
No layer stack recorded.
E-mode HEMT formed by first and second transistors
No layer stack recorded.
p-GaN gate HEMT
semiconductor structure with dual-region III-V HEMT
Materials described outside the worked examples.
p-GaN gate
III-V compound buffer layer
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,355,625Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device, comprising: a first transistor, comprising a first gate terminal, a first source terminal, and a first drain terminal, wherein the first gate terminal is coupled to the first source terminal; and a second transistor, comprising a second gate terminal, a second source terminal, and a second drain terminal, wherein the second gate terminal is coupled to the first drain terminal.
The device of claim 1, wherein each of the first transistor and the second transistor is an E-mode HEMT.
The device of claim 1, wherein each of the first transistor and the second transistor is a p- G aN gate H EMT.
The device of claim 1, wherein the device is an E-mode H EMT formed by the first transistor and the second transistor.
A semiconductor structure, comprising: a substrate; a I II -V compound buffer layer, disposed over the substrate, wherein a top of the I II-V compound buffer layer comprises a first region and a second region; a first I II -V compound layer, disposed in the first region and over the I II -V compound buffer layer; a second I II -V compound layer, disposed in the second region and over the I II-V compound buffer layer; a first gate structure, disposed over the first I II -V compound layer; a second gate structure, disposed over the second I II -V compound layer; a first source region, coupled to the first gate structure; a first drain region, coupled to the second gate structure, wherein the first source region and the first drain region are respectively disposed on two opposite sides of the first gate structure and over the first I II -V compound layer; a second source region; and a second drain region, wherein the second source region and the second drain region are respectively disposed on two opposite sides of the second gate structure and over the second I II -V compound layer.
The semiconductor structure of claim 11, wherein the first gate structure further comp ri ses: a first P-type I II -V compound layer, disposed over the first I II -V compound layer; and a first gate electrode, disposed over the first P-type I II -V compound layer.
The semiconductor structure of claim 11, wherein the second gate structure further comprises: a second P-type I II -V compound layer, disposed over the second I II -V compound layer; and a second gate electrode, disposed over the second P-type I II -V compound layer.
The semiconductor structure of claim 11, wherein a first e-mode H EMT and a second e-mode H EMT are formed in the first region and the second region respectively.
The semiconductor structure of claim 11, wherein the semiconductor structure forms an e-mode H EMT comprising a gate terminal, a source terminal, and a drain terminal, wherein the gate terminal is formed by the first gate structure, the source terminal is formed by the second source region, and the drain terminal is formed by the second drain region.
Layer stacks claimed or described, ordered top of device to substrate.
two-transistor cascode device
No layer stack recorded.
E-mode HEMT formed by first and second transistors
No layer stack recorded.
p-GaN gate HEMT
semiconductor structure with dual-region III-V HEMT
Materials described outside the worked examples.
p-GaN gate
III-V compound buffer layer
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 11,355,625Patent drawings and their descriptions. Click a drawing to enlarge it.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A device, comprising: a first transistor, comprising a first gate terminal, a first source terminal, and a first drain terminal, wherein the first gate terminal is coupled to the first source terminal; and a second transistor, comprising a second gate terminal, a second source terminal, and a second drain terminal, wherein the second gate terminal is coupled to the first drain terminal.
The device of claim 1, wherein each of the first transistor and the second transistor is an E-mode HEMT.
The device of claim 1, wherein each of the first transistor and the second transistor is a p- G aN gate H EMT.
The device of claim 1, wherein the device is an E-mode H EMT formed by the first transistor and the second transistor.
A semiconductor structure, comprising: a substrate; a I II -V compound buffer layer, disposed over the substrate, wherein a top of the I II-V compound buffer layer comprises a first region and a second region; a first I II -V compound layer, disposed in the first region and over the I II -V compound buffer layer; a second I II -V compound layer, disposed in the second region and over the I II-V compound buffer layer; a first gate structure, disposed over the first I II -V compound layer; a second gate structure, disposed over the second I II -V compound layer; a first source region, coupled to the first gate structure; a first drain region, coupled to the second gate structure, wherein the first source region and the first drain region are respectively disposed on two opposite sides of the first gate structure and over the first I II -V compound layer; a second source region; and a second drain region, wherein the second source region and the second drain region are respectively disposed on two opposite sides of the second gate structure and over the second I II -V compound layer.
The semiconductor structure of claim 11, wherein the first gate structure further comp ri ses: a first P-type I II -V compound layer, disposed over the first I II -V compound layer; and a first gate electrode, disposed over the first P-type I II -V compound layer.
The semiconductor structure of claim 11, wherein the second gate structure further comprises: a second P-type I II -V compound layer, disposed over the second I II -V compound layer; and a second gate electrode, disposed over the second P-type I II -V compound layer.
The semiconductor structure of claim 11, wherein a first e-mode H EMT and a second e-mode H EMT are formed in the first region and the second region respectively.
The semiconductor structure of claim 11, wherein the semiconductor structure forms an e-mode H EMT comprising a gate terminal, a source terminal, and a drain terminal, wherein the gate terminal is formed by the first gate structure, the source terminal is formed by the second source region, and the drain terminal is formed by the second drain region.
Layer stacks claimed or described, ordered top of device to substrate.
two-transistor cascode device
No layer stack recorded.
E-mode HEMT formed by first and second transistors
No layer stack recorded.
p-GaN gate HEMT
semiconductor structure with dual-region III-V HEMT
Materials described outside the worked examples.
p-GaN gate
III-V compound buffer layer
Related documents with shared materials, methods, properties, or citations.
semiconductor structure 200 (cross-sectional embodiment)
first P-type III-V compound layer
second P-type III-V compound layer
silicon substrate
Si
III-V compound buffer layer (GaN-based)
REDUCED PUNCHTHROUGH BREAKDOWN IN GALLIUM-NITRIDE TRANSISTORS
semiconductor structure 200 (cross-sectional embodiment)
first P-type III-V compound layer
second P-type III-V compound layer
silicon substrate
Si
III-V compound buffer layer (GaN-based)
REDUCED PUNCHTHROUGH BREAKDOWN IN GALLIUM-NITRIDE TRANSISTORS
semiconductor structure 200 (cross-sectional embodiment)
first P-type III-V compound layer
second P-type III-V compound layer
silicon substrate
Si
III-V compound buffer layer (GaN-based)
REDUCED PUNCHTHROUGH BREAKDOWN IN GALLIUM-NITRIDE TRANSISTORS
semiconductor structure 200 (cross-sectional embodiment)
first P-type III-V compound layer
second P-type III-V compound layer
silicon substrate
Si
III-V compound buffer layer (GaN-based)