Patent
US 9,263,443SEMICONDUCTOR DEVICE INCLUDING A NORMALLY-OFF TRANSISTOR AND TRANSISTOR CELLS OF A NORMALLY-ON GAN HEMT
Michael Treu
US
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US 9,263,443Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a schematic circuit diagram of a semiconductor switch including a cascode circuit of a normally-off transistor in a first semiconductor die …
FIG. 2 illustrates a schematic cross-sectional view of an arrangement of the first semiconductor die and the second semiconductor die within a package. [0012]
FIG. 3 illustrates a schematic circuit diagram of a normally-on JFET, a gate resistor and a voltage clamping element including semiconductor diodes. [0013]
FIG. 4 illustrates a schematic cross-sectional view of a portion of a SiC semiconductor die including a JFET, a gate resistor and a vertical voltage clamping …
FIG. 5 illustrates a schematic cross-sectional view of a portion of a SiC semiconductor die including a JFET, a gate resistor and a lateral voltage clamping …
FIG. 6 illustrates a schematic cross-sectional view of a portion of a SiC semiconductor die including a JFET, a gate resistor and a lateral voltage clamping …
FIG. 7 illustrates a schematic layout of a JFET, a gate resistor and a voltage clamping element.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a first semiconductor die including a normally-off transistor; and a second semiconductor die including a plurality of transistor cells of a normally-on GaN HEMT, one of a source terminal and a drain terminal of the normally-off transistor being electrically coupled to a gate terminal of the normally-on GaN HEMT, the other one of the source terminal and the drain terminal of the normally-off transistor being electrically coupled to one of a source terminal and a drain terminal of the normally-on GaN HEMT, wherein the second semiconductor die further includes: a gate resistor electrically coupled between the gate terminal of the normally-off normally-on transistor and respective gates of the plurality of transistor cells; and a voltage clamping element electrically coupled between the gate terminal and the one of the source terminal and the drain terminal of the normally-on GaN HEMT.
The semiconductor device of claim 1, wherein the first semiconductor die includes a semiconductor substrate made of Si and the normally-off transistor is a normally-off metal insulator field effect transistor (MISFET).
The semiconductor device of claim 1, wherein the voltage clamping element includes a pn junction diode. 2 of 5 Application Ser. No.: 13/963,080 Attorney Docket No. 1012-0653/2009P₅₁₂₄₀ US O₁
The semiconductor device of claim 1, wherein a clamping voltage of the voltage clamping element is smaller than an electrical breakdown voltage between the source and drain of the normally-off transistor.
The semiconductor device of claim 1, wherein the gate resistor is within a range of 0.5 S₂ to 500 SVG 13963080.12-01-2015.IHQ₈S₄YCPXXIFW2.CLM.2.7.744.1024.790.1059.svg 0.117 0.153 Chemistry Black and white
The semiconductor device of claim 1, wherein a ratio of electrical breakdown voltages of the normally-off transistor and the normally-on GaN HEMT is within a range of 1:5 to 1:100.
The semiconductor device of claim 1, wherein an area of the gate resistor at least partially overlaps with a gate pad area electrically coupled to the gate terminal of the normally-on GaN HEMT.
The semiconductor device of claim 1, wherein the first semiconductor die and the second semiconductor die are arranged chip-on-chip in a single package in a sequence of a leadframe, the second semiconductor die and the first semiconductor die. 3 of 5 Application Ser. No.: 13/963,080 Attorney Docket No. 1012-0653/2009P₅₁₂₄₀ US O₁
Layer stacks claimed or described, ordered top of device to substrate.
cascode semiconductor switch (normally-off transistor + normally-on GaN HEMT)
normally-on GaN HEMT (plurality of transistor cells)
normally-on JFET (SiC-based embodiment)
Materials described outside the worked examples.
silicon
Si
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates a schematic circuit diagram of a semiconductor switch including a cascode circuit of a normally-off transistor in a first semiconductor die …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
gate resistor value range | 0.5–500 Ohm | — |
gate resistor value range (claim) | 0.5–500 Ohm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,263,443Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a schematic circuit diagram of a semiconductor switch including a cascode circuit of a normally-off transistor in a first semiconductor die …
FIG. 2 illustrates a schematic cross-sectional view of an arrangement of the first semiconductor die and the second semiconductor die within a package. [0012]
FIG. 3 illustrates a schematic circuit diagram of a normally-on JFET, a gate resistor and a voltage clamping element including semiconductor diodes. [0013]
FIG. 4 illustrates a schematic cross-sectional view of a portion of a SiC semiconductor die including a JFET, a gate resistor and a vertical voltage clamping …
FIG. 5 illustrates a schematic cross-sectional view of a portion of a SiC semiconductor die including a JFET, a gate resistor and a lateral voltage clamping …
FIG. 6 illustrates a schematic cross-sectional view of a portion of a SiC semiconductor die including a JFET, a gate resistor and a lateral voltage clamping …
FIG. 7 illustrates a schematic layout of a JFET, a gate resistor and a voltage clamping element.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a first semiconductor die including a normally-off transistor; and a second semiconductor die including a plurality of transistor cells of a normally-on GaN HEMT, one of a source terminal and a drain terminal of the normally-off transistor being electrically coupled to a gate terminal of the normally-on GaN HEMT, the other one of the source terminal and the drain terminal of the normally-off transistor being electrically coupled to one of a source terminal and a drain terminal of the normally-on GaN HEMT, wherein the second semiconductor die further includes: a gate resistor electrically coupled between the gate terminal of the normally-off normally-on transistor and respective gates of the plurality of transistor cells; and a voltage clamping element electrically coupled between the gate terminal and the one of the source terminal and the drain terminal of the normally-on GaN HEMT.
The semiconductor device of claim 1, wherein the first semiconductor die includes a semiconductor substrate made of Si and the normally-off transistor is a normally-off metal insulator field effect transistor (MISFET).
The semiconductor device of claim 1, wherein the voltage clamping element includes a pn junction diode. 2 of 5 Application Ser. No.: 13/963,080 Attorney Docket No. 1012-0653/2009P₅₁₂₄₀ US O₁
The semiconductor device of claim 1, wherein a clamping voltage of the voltage clamping element is smaller than an electrical breakdown voltage between the source and drain of the normally-off transistor.
The semiconductor device of claim 1, wherein the gate resistor is within a range of 0.5 S₂ to 500 SVG 13963080.12-01-2015.IHQ₈S₄YCPXXIFW2.CLM.2.7.744.1024.790.1059.svg 0.117 0.153 Chemistry Black and white
The semiconductor device of claim 1, wherein a ratio of electrical breakdown voltages of the normally-off transistor and the normally-on GaN HEMT is within a range of 1:5 to 1:100.
The semiconductor device of claim 1, wherein an area of the gate resistor at least partially overlaps with a gate pad area electrically coupled to the gate terminal of the normally-on GaN HEMT.
The semiconductor device of claim 1, wherein the first semiconductor die and the second semiconductor die are arranged chip-on-chip in a single package in a sequence of a leadframe, the second semiconductor die and the first semiconductor die. 3 of 5 Application Ser. No.: 13/963,080 Attorney Docket No. 1012-0653/2009P₅₁₂₄₀ US O₁
Layer stacks claimed or described, ordered top of device to substrate.
cascode semiconductor switch (normally-off transistor + normally-on GaN HEMT)
normally-on GaN HEMT (plurality of transistor cells)
normally-on JFET (SiC-based embodiment)
Materials described outside the worked examples.
silicon
Si
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates a schematic circuit diagram of a semiconductor switch including a cascode circuit of a normally-off transistor in a first semiconductor die …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
gate resistor value range | 0.5–500 Ohm | — |
gate resistor value range (claim) | 0.5–500 Ohm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,263,443Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a schematic circuit diagram of a semiconductor switch including a cascode circuit of a normally-off transistor in a first semiconductor die …
FIG. 2 illustrates a schematic cross-sectional view of an arrangement of the first semiconductor die and the second semiconductor die within a package. [0012]
FIG. 3 illustrates a schematic circuit diagram of a normally-on JFET, a gate resistor and a voltage clamping element including semiconductor diodes. [0013]
FIG. 4 illustrates a schematic cross-sectional view of a portion of a SiC semiconductor die including a JFET, a gate resistor and a vertical voltage clamping …
FIG. 5 illustrates a schematic cross-sectional view of a portion of a SiC semiconductor die including a JFET, a gate resistor and a lateral voltage clamping …
FIG. 6 illustrates a schematic cross-sectional view of a portion of a SiC semiconductor die including a JFET, a gate resistor and a lateral voltage clamping …
FIG. 7 illustrates a schematic layout of a JFET, a gate resistor and a voltage clamping element.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a first semiconductor die including a normally-off transistor; and a second semiconductor die including a plurality of transistor cells of a normally-on GaN HEMT, one of a source terminal and a drain terminal of the normally-off transistor being electrically coupled to a gate terminal of the normally-on GaN HEMT, the other one of the source terminal and the drain terminal of the normally-off transistor being electrically coupled to one of a source terminal and a drain terminal of the normally-on GaN HEMT, wherein the second semiconductor die further includes: a gate resistor electrically coupled between the gate terminal of the normally-off normally-on transistor and respective gates of the plurality of transistor cells; and a voltage clamping element electrically coupled between the gate terminal and the one of the source terminal and the drain terminal of the normally-on GaN HEMT.
The semiconductor device of claim 1, wherein the first semiconductor die includes a semiconductor substrate made of Si and the normally-off transistor is a normally-off metal insulator field effect transistor (MISFET).
The semiconductor device of claim 1, wherein the voltage clamping element includes a pn junction diode. 2 of 5 Application Ser. No.: 13/963,080 Attorney Docket No. 1012-0653/2009P₅₁₂₄₀ US O₁
The semiconductor device of claim 1, wherein a clamping voltage of the voltage clamping element is smaller than an electrical breakdown voltage between the source and drain of the normally-off transistor.
The semiconductor device of claim 1, wherein the gate resistor is within a range of 0.5 S₂ to 500 SVG 13963080.12-01-2015.IHQ₈S₄YCPXXIFW2.CLM.2.7.744.1024.790.1059.svg 0.117 0.153 Chemistry Black and white
The semiconductor device of claim 1, wherein a ratio of electrical breakdown voltages of the normally-off transistor and the normally-on GaN HEMT is within a range of 1:5 to 1:100.
The semiconductor device of claim 1, wherein an area of the gate resistor at least partially overlaps with a gate pad area electrically coupled to the gate terminal of the normally-on GaN HEMT.
The semiconductor device of claim 1, wherein the first semiconductor die and the second semiconductor die are arranged chip-on-chip in a single package in a sequence of a leadframe, the second semiconductor die and the first semiconductor die. 3 of 5 Application Ser. No.: 13/963,080 Attorney Docket No. 1012-0653/2009P₅₁₂₄₀ US O₁
Layer stacks claimed or described, ordered top of device to substrate.
cascode semiconductor switch (normally-off transistor + normally-on GaN HEMT)
normally-on GaN HEMT (plurality of transistor cells)
normally-on JFET (SiC-based embodiment)
Materials described outside the worked examples.
silicon
Si
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates a schematic circuit diagram of a semiconductor switch including a cascode circuit of a normally-off transistor in a first semiconductor die …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
gate resistor value range | 0.5–500 Ohm | — |
gate resistor value range (claim) | 0.5–500 Ohm | — |
Related documents with shared materials, methods, properties, or citations.
Patent
Atlas literature
Patent
US 9,263,443Patent drawings and their descriptions. Click a drawing to enlarge it.
FIG. 1 illustrates a schematic circuit diagram of a semiconductor switch including a cascode circuit of a normally-off transistor in a first semiconductor die …
FIG. 2 illustrates a schematic cross-sectional view of an arrangement of the first semiconductor die and the second semiconductor die within a package. [0012]
FIG. 3 illustrates a schematic circuit diagram of a normally-on JFET, a gate resistor and a voltage clamping element including semiconductor diodes. [0013]
FIG. 4 illustrates a schematic cross-sectional view of a portion of a SiC semiconductor die including a JFET, a gate resistor and a vertical voltage clamping …
FIG. 5 illustrates a schematic cross-sectional view of a portion of a SiC semiconductor die including a JFET, a gate resistor and a lateral voltage clamping …
FIG. 6 illustrates a schematic cross-sectional view of a portion of a SiC semiconductor die including a JFET, a gate resistor and a lateral voltage clamping …
FIG. 7 illustrates a schematic layout of a JFET, a gate resistor and a voltage clamping element.
Claims define the patent's legal scope. Independent claims stand alone; dependent claims (nested) narrow them. Click a claim to expand its dependents.
A semiconductor device, comprising: a first semiconductor die including a normally-off transistor; and a second semiconductor die including a plurality of transistor cells of a normally-on GaN HEMT, one of a source terminal and a drain terminal of the normally-off transistor being electrically coupled to a gate terminal of the normally-on GaN HEMT, the other one of the source terminal and the drain terminal of the normally-off transistor being electrically coupled to one of a source terminal and a drain terminal of the normally-on GaN HEMT, wherein the second semiconductor die further includes: a gate resistor electrically coupled between the gate terminal of the normally-off normally-on transistor and respective gates of the plurality of transistor cells; and a voltage clamping element electrically coupled between the gate terminal and the one of the source terminal and the drain terminal of the normally-on GaN HEMT.
The semiconductor device of claim 1, wherein the first semiconductor die includes a semiconductor substrate made of Si and the normally-off transistor is a normally-off metal insulator field effect transistor (MISFET).
The semiconductor device of claim 1, wherein the voltage clamping element includes a pn junction diode. 2 of 5 Application Ser. No.: 13/963,080 Attorney Docket No. 1012-0653/2009P₅₁₂₄₀ US O₁
The semiconductor device of claim 1, wherein a clamping voltage of the voltage clamping element is smaller than an electrical breakdown voltage between the source and drain of the normally-off transistor.
The semiconductor device of claim 1, wherein the gate resistor is within a range of 0.5 S₂ to 500 SVG 13963080.12-01-2015.IHQ₈S₄YCPXXIFW2.CLM.2.7.744.1024.790.1059.svg 0.117 0.153 Chemistry Black and white
The semiconductor device of claim 1, wherein a ratio of electrical breakdown voltages of the normally-off transistor and the normally-on GaN HEMT is within a range of 1:5 to 1:100.
The semiconductor device of claim 1, wherein an area of the gate resistor at least partially overlaps with a gate pad area electrically coupled to the gate terminal of the normally-on GaN HEMT.
The semiconductor device of claim 1, wherein the first semiconductor die and the second semiconductor die are arranged chip-on-chip in a single package in a sequence of a leadframe, the second semiconductor die and the first semiconductor die. 3 of 5 Application Ser. No.: 13/963,080 Attorney Docket No. 1012-0653/2009P₅₁₂₄₀ US O₁
Layer stacks claimed or described, ordered top of device to substrate.
cascode semiconductor switch (normally-off transistor + normally-on GaN HEMT)
normally-on GaN HEMT (plurality of transistor cells)
normally-on JFET (SiC-based embodiment)
Materials described outside the worked examples.
silicon
Si
GaN
Measurements and analyses referenced in the patent, with their drawing references.
FIG. 1 illustrates a schematic circuit diagram of a semiconductor switch including a cascode circuit of a normally-off transistor in a first semiconductor die …
Performance values and ranges asserted in the specification or claims.
| Property | Value | Material |
|---|---|---|
gate resistor value range | 0.5–500 Ohm | — |
gate resistor value range (claim) | 0.5–500 Ohm | — |
Related documents with shared materials, methods, properties, or citations.
SiC
SiC
SiC
SiC